diff options
| author | Damien George <damien@micropython.org> | 2023-03-06 18:15:23 +1100 |
|---|---|---|
| committer | Damien George <damien@micropython.org> | 2023-03-08 14:04:14 +1100 |
| commit | 8b3f1d47a66c9a87dc35d2828902759b92ab4dfd (patch) | |
| tree | 696a21a9400ee57f3e4a5f74ca0aa1d36705be44 /ports/stm32/powerctrlboot.c | |
| parent | c551723914ac5ce123216c1dd776bc4fdf25cc65 (diff) | |
stm32/powerctrlboot: Provide custom SystemInit for WB55.
Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>
Signed-off-by: Damien George <damien@micropython.org>
Diffstat (limited to 'ports/stm32/powerctrlboot.c')
| -rw-r--r-- | ports/stm32/powerctrlboot.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/ports/stm32/powerctrlboot.c b/ports/stm32/powerctrlboot.c index b78fcae4b..912c8633a 100644 --- a/ports/stm32/powerctrlboot.c +++ b/ports/stm32/powerctrlboot.c @@ -28,6 +28,24 @@ #include "irq.h" #include "powerctrl.h" +#if defined(STM32WB) +void stm32_system_init(void) { + if (RCC->CR == 0x00000560 && RCC->CFGR == 0x00070005) { + // Wake from STANDBY with HSI enabled as system clock. The second core likely + // also needs HSI to remain enabled, so do as little as possible here. + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + // set CP10 and CP11 Full Access. + SCB->CPACR |= (3 << (10 * 2)) | (3 << (11 * 2)); + #endif + // Disable all interrupts. + RCC->CIER = 0x00000000; + } else { + // Other start-up (eg POR), use standard system init code. + SystemInit(); + } +} +#endif + void powerctrl_config_systick(void) { // Configure SYSTICK to run at 1kHz (1ms interval) SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; |