diff options
| author | Damien George <damien@micropython.org> | 2023-09-14 11:33:41 +1000 |
|---|---|---|
| committer | Damien George <damien@micropython.org> | 2023-09-20 18:56:52 +1000 |
| commit | a3862e726728725248d42ea9173675d523c13911 (patch) | |
| tree | ae37991b4d929c44a95fdcc377bda24a1548514b /ports/stm32/powerctrlboot.c | |
| parent | fa685239687b0ee3d34788b2edd0711e9fc6bc3c (diff) | |
stm32/powerctrlboot: Allow PLL1 Q and R outputs to be enabled on H5.
If a board needs these outputs then it can define MICROPY_HW_CLK_PLLQ/R.
It saves power to not enable them if they are not needed.
Signed-off-by: Damien George <damien@micropython.org>
Diffstat (limited to 'ports/stm32/powerctrlboot.c')
| -rw-r--r-- | ports/stm32/powerctrlboot.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/ports/stm32/powerctrlboot.c b/ports/stm32/powerctrlboot.c index 220375a51..c7802a558 100644 --- a/ports/stm32/powerctrlboot.c +++ b/ports/stm32/powerctrlboot.c @@ -218,13 +218,21 @@ void SystemClock_Config(void) { // Configure PLL1 for use as system clock. LL_RCC_PLL1_ConfigDomain_SYS(pll1_source, MICROPY_HW_CLK_PLLM, MICROPY_HW_CLK_PLLN, MICROPY_HW_CLK_PLLP); - LL_RCC_PLL1_SetQ(MICROPY_HW_CLK_PLLQ); - LL_RCC_PLL1_SetR(MICROPY_HW_CLK_PLLR); LL_RCC_PLL1_SetFRACN(MICROPY_HW_CLK_PLLFRAC); LL_RCC_PLL1_SetVCOInputRange(MICROPY_HW_CLK_PLLVCI_LL); LL_RCC_PLL1_SetVCOOutputRange(MICROPY_HW_CLK_PLLVCO_LL); LL_RCC_PLL1P_Enable(); + #if defined(MICROPY_HW_CLK_PLLQ) + LL_RCC_PLL1_SetQ(MICROPY_HW_CLK_PLLQ); + LL_RCC_PLL1Q_Enable(); + #endif + + #if defined(MICROPY_HW_CLK_PLLR) + LL_RCC_PLL1_SetR(MICROPY_HW_CLK_PLLR); + LL_RCC_PLL1R_Enable(); + #endif + // Enable PLL1. LL_RCC_PLL1_Enable(); while (!LL_RCC_PLL1_IsReady()) { |