diff options
| author | Chris Mason <c.mason@inchipdesign.com.au> | 2019-09-25 21:38:27 +1000 |
|---|---|---|
| committer | Damien George <damien.p.george@gmail.com> | 2019-09-26 17:34:04 +1000 |
| commit | eb12fa38624a6bb4b71ef72f2aadc0f7ca8f27d1 (patch) | |
| tree | 75032761ce641b907a9d37937ed9553dacff6d1f /ports/stm32/powerctrlboot.c | |
| parent | f16e4be3fa16a3532bb93ccf88e867d27fe2ff20 (diff) | |
stm32/powerctrlboot: Add support for HSI at 8MHz on F0 MCUs.
For use with F0 MCUs that don't have HSI48. Select the clock source
explicitly in mpconfigboard.h.
On the NUCLEO_F091RC board use HSE bypass when HSE is chosen because the
NUCLEO clock source is STLINK not a crystal.
Diffstat (limited to 'ports/stm32/powerctrlboot.c')
| -rw-r--r-- | ports/stm32/powerctrlboot.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/ports/stm32/powerctrlboot.c b/ports/stm32/powerctrlboot.c index 0579853ee..766c52dfb 100644 --- a/ports/stm32/powerctrlboot.c +++ b/ports/stm32/powerctrlboot.c @@ -48,7 +48,7 @@ void SystemClock_Config(void) { RCC->CFGR = 0 << RCC_CFGR_PLLMUL_Pos | 3 << RCC_CFGR_PLLSRC_Pos; // PLL mult by 2, src = HSI48/PREDIV RCC->CFGR2 = 1; // Input clock divided by 2 - #else + #elif MICROPY_HW_CLK_USE_HSE // Use HSE and the PLL to get a 48MHz SYSCLK #if MICROPY_HW_CLK_USE_BYPASS @@ -61,6 +61,18 @@ void SystemClock_Config(void) { RCC->CFGR = ((48000000 / HSE_VALUE) - 2) << RCC_CFGR_PLLMUL_Pos | 2 << RCC_CFGR_PLLSRC_Pos; RCC->CFGR2 = 0; // Input clock not divided + #elif MICROPY_HW_CLK_USE_HSI + // Use the 8MHz internal oscillator and the PLL to get a 48MHz SYSCLK + + RCC->CR |= RCC_CR_HSION; + while ((RCC->CR & RCC_CR_HSIRDY) == 0) { + // Wait for HSI to be ready + } + RCC->CFGR = 4 << RCC_CFGR_PLLMUL_Pos | 1 << RCC_CFGR_PLLSRC_Pos; // PLL mult by 6, src = HSI + RCC->CFGR2 = 0; // Input clock not divided + + #else + #error System clock not specified #endif RCC->CR |= RCC_CR_PLLON; // Turn PLL on |