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authorHerwin Grobben <h.grobben@aemics.nl>2025-05-22 12:26:59 +0200
committerDamien George <damien@micropython.org>2025-05-26 12:40:27 +1000
commit2dada065ac4333d8623fd2c7509c47d15d8c9a5e (patch)
tree299fb0aa8aa70524d932adc87712e0db9199ec87 /ports/stm32/qspi.c
parent9dbae39348e2c95190d808bc14a0e8adb1c3b8be (diff)
stm32: Allow QSPI to work on STM32G4.
Adding a QSPI memory chip on a STM32G4 does not work due to some small issues, which are fixed in this commit: - Rename QUADSPI1_xxx alt-func names to QUADSPI_xxx, to match the static names used in `qspi.c`. - Enable `mpu.h` macros on G4. - Don't include I- and D-cache invalidation on G4. Signed-off-by: Damien George <damien@micropython.org>
Diffstat (limited to 'ports/stm32/qspi.c')
-rw-r--r--ports/stm32/qspi.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/ports/stm32/qspi.c b/ports/stm32/qspi.c
index 781aae803..2ef9a4d01 100644
--- a/ports/stm32/qspi.c
+++ b/ports/stm32/qspi.c
@@ -213,11 +213,13 @@ static int qspi_ioctl(void *self_in, uint32_t cmd, uintptr_t arg) {
qspi_memory_map();
break;
case MP_QSPI_IOCTL_MEMORY_MODIFIED: {
+ #if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
uintptr_t *addr_len = (uintptr_t *)arg;
volatile void *addr = (volatile void *)(QSPI_MAP_ADDR + addr_len[0]);
size_t len = addr_len[1];
SCB_InvalidateICache_by_Addr(addr, len);
SCB_InvalidateDCache_by_Addr(addr, len);
+ #endif
break;
}
}