diff options
| author | iabdalkader <i.abdalkader@gmail.com> | 2022-04-08 09:41:19 +0200 |
|---|---|---|
| committer | Damien George <damien@micropython.org> | 2022-04-11 16:12:53 +1000 |
| commit | 36cac5e1547ece2185561c0c1272c6da28b03f30 (patch) | |
| tree | a7a8dc59a4d402eaf705e6eeeeb8f26200290ed3 /ports/stm32/system_stm32.c | |
| parent | a3e5a68c46af76d4d6e8924388b6a943996aa95e (diff) | |
stm32/system_stm32: Allow boards to configure PLL VCI, VCO and FRACN.
This removes hard-coded PLL1/3 VCI, VCO and FRACN.
Diffstat (limited to 'ports/stm32/system_stm32.c')
| -rw-r--r-- | ports/stm32/system_stm32.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/ports/stm32/system_stm32.c b/ports/stm32/system_stm32.c index dfff803e0..bf630fb7c 100644 --- a/ports/stm32/system_stm32.c +++ b/ports/stm32/system_stm32.c @@ -351,9 +351,9 @@ MP_WEAK void SystemClock_Config(void) { #endif #if defined(STM32H7) - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1; - RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; - RCC_OscInitStruct.PLL.PLLFRACN = 0; + RCC_OscInitStruct.PLL.PLLRGE = MICROPY_HW_CLK_PLLVCI; + RCC_OscInitStruct.PLL.PLLVCOSEL = MICROPY_HW_CLK_PLLVCO; + RCC_OscInitStruct.PLL.PLLFRACN = MICROPY_HW_CLK_PLLFRAC; #endif #if defined(STM32F4) || defined(STM32F7) @@ -392,9 +392,9 @@ MP_WEAK void SystemClock_Config(void) { PeriphClkInitStruct.PLL3.PLL3P = MICROPY_HW_CLK_PLL3P; PeriphClkInitStruct.PLL3.PLL3Q = MICROPY_HW_CLK_PLL3Q; PeriphClkInitStruct.PLL3.PLL3R = MICROPY_HW_CLK_PLL3R; - PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_1; - PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE; - PeriphClkInitStruct.PLL3.PLL3FRACN = 0; + PeriphClkInitStruct.PLL3.PLL3RGE = MICROPY_HW_CLK_PLL3VCI; + PeriphClkInitStruct.PLL3.PLL3VCOSEL = MICROPY_HW_CLK_PLL3VCO; + PeriphClkInitStruct.PLL3.PLL3FRACN = MICROPY_HW_CLK_PLL3FRAC; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { __fatal_error("HAL_RCCEx_PeriphCLKConfig"); } |