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authorennyKey <ennyKey@fn.de>2024-12-04 22:33:17 +0100
committerDamien George <damien@micropython.org>2025-06-26 12:36:04 +1000
commit2a46759fe83a5295f7c06e2dab37c3f85848800e (patch)
tree74b893a498f70b121da5b5e8bf3ce535f29eaaaf /ports/stm32/uart.c
parent5c6da117995ef7f9a7396c4048d3e34f56d73ba4 (diff)
stm32/uart: Enable UART FIFO for H7 MCUs.
The H7 has a hardware UART FIFO, so it's worth enabling it, to reduce the chance of missed incoming characters. Note that `HAL_UART_Init(&huart)` does not activate the FIFO, it must be done explicitly by calling `HAL_UARTEx_EnableFifoMode(&huart)`. Signed-off-by: ennyKey <ennyKey@fn.de>
Diffstat (limited to 'ports/stm32/uart.c')
-rw-r--r--ports/stm32/uart.c11
1 files changed, 10 insertions, 1 deletions
diff --git a/ports/stm32/uart.c b/ports/stm32/uart.c
index 91db91395..55fa62214 100644
--- a/ports/stm32/uart.c
+++ b/ports/stm32/uart.c
@@ -653,7 +653,7 @@ bool uart_init(machine_uart_obj_t *uart_obj,
huart.Init.HwFlowCtl = flow;
huart.Init.OverSampling = UART_OVERSAMPLING_16;
- #if defined(STM32G4) // H7 and WB also have fifo..
+ #if defined(STM32G4) || defined(STM32H7) // WB also has a fifo..
huart.FifoMode = UART_FIFOMODE_ENABLE;
#endif
@@ -701,6 +701,12 @@ bool uart_init(machine_uart_obj_t *uart_obj,
uart_obj->char_width = CHAR_WIDTH_8BIT;
}
+ #if defined(STM32H7)
+ HAL_UARTEx_SetTxFifoThreshold(&huart, UART_TXFIFO_THRESHOLD_1_8);
+ HAL_UARTEx_SetRxFifoThreshold(&huart, UART_RXFIFO_THRESHOLD_1_8);
+ HAL_UARTEx_EnableFifoMode(&huart);
+ #endif
+
uart_obj->mp_irq_trigger = 0;
uart_obj->mp_irq_obj = NULL;
@@ -1141,6 +1147,9 @@ size_t uart_tx_data(machine_uart_obj_t *self, const void *src_in, size_t num_cha
// timeout_char by FIFO size + 1.
// STM32G4 has 8 words FIFO.
timeout = (8 + 1) * self->timeout_char;
+ #elif defined(STM32H7)
+ // STM32H7 has 16 words FIFO.
+ timeout = (16 + 1) * self->timeout_char;
#else
// The timeout specified here is for waiting for the TX data register to
// become empty (ie between chars), as well as for the final char to be