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authorDamien George <damien@micropython.org>2021-05-25 22:15:58 +1000
committerDamien George <damien@micropython.org>2021-05-26 16:24:00 +1000
commit4ee8ec6931e6a5958d2a5710c6a8f7cd7c0f3862 (patch)
tree5c4db51b5c5d1009c81fed83f3d899951af8f852 /py/asmarm.c
parentc732b80f0584156b6ff98e8baa90c011539bf88a (diff)
py/asmarm: Use builtin func to flush I- and D-cache on ARM 7 archs.
The inline assembler code does not work for __ARM_ARCH == 7. Signed-off-by: Damien George <damien@micropython.org>
Diffstat (limited to 'py/asmarm.c')
-rw-r--r--py/asmarm.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/py/asmarm.c b/py/asmarm.c
index e91421578..5662d75e1 100644
--- a/py/asmarm.c
+++ b/py/asmarm.c
@@ -40,7 +40,7 @@
void asm_arm_end_pass(asm_arm_t *as) {
if (as->base.pass == MP_ASM_PASS_EMIT) {
- #if defined(__linux__) && defined(__GNUC__)
+ #if (defined(__linux__) && defined(__GNUC__)) || __ARM_ARCH == 7
char *start = mp_asm_base_get_code(&as->base);
char *end = start + mp_asm_base_get_code_size(&as->base);
__builtin___clear_cache(start, end);
@@ -48,10 +48,10 @@ void asm_arm_end_pass(asm_arm_t *as) {
// flush I- and D-cache
asm volatile (
"0:"
- "mrc p15, 0, r15, c7, c10, 3\n"
+ "mrc p15, 0, r15, c7, c10, 3\n" // test and clean D-cache
"bne 0b\n"
"mov r0, #0\n"
- "mcr p15, 0, r0, c7, c7, 0\n"
+ "mcr p15, 0, r0, c7, c7, 0\n" // invalidate I-cache and D-cache
: : : "r0", "cc");
#endif
}