py/emitnative: Refactor Viper register-indexed load/stores.

This commit cleans up the Viper code generation blocks for
register-indexed load and store operations.

An attempt is made to simplify the code in the common code generator
code block, by moving architecture-specific code to the appropriate
native generation backends whenever possible.  This should make that
specific bit of code in the Viper generator clearer and easier to
maintain in the long term.

To achieve this, six generic assembler meta-opcodes have been
introduced, named `ASM_{LOAD,STORE}{8,16,32}_REG_REG_REG`.  A
platform-independent implementation for those operations is provided, so
backends that cannot emit a shorter sequence for the requested operation
or are fine with the platform-independent implementation can just not
provide said meta-opcodes.

Signed-off-by: Alessandro Gatti <a.gatti@frob.it>

1 files changed, 0 insertions, 20 deletions

diff --git a/py/asmthumb.c b/py/asmthumb.c
index 73684c0f5..420815e80 100644
--- a/py/asmthumb.c
+++ b/py/asmthumb.c
@@ -491,26 +491,6 @@ void asm_thumb_ldrh_reg_reg_i12_optimised(asm_thumb_t *as, uint reg_dest, uint r
     }
 }
 
-void asm_thumb_ldrh_reg_reg_reg(asm_thumb_t *as, uint reg_dest, uint reg_base, uint reg_index) {
-    asm_thumb_lsl_rlo_rlo_i5(as, reg_index, reg_index, 1);
-    asm_thumb_ldrh_rlo_rlo_rlo(as, reg_dest, reg_base, reg_index);
-}
-
-void asm_thumb_ldr_reg_reg_reg(asm_thumb_t *as, uint reg_dest, uint reg_base, uint reg_index) {
-    asm_thumb_lsl_rlo_rlo_i5(as, reg_index, reg_index, 2);
-    asm_thumb_ldr_rlo_rlo_rlo(as, reg_dest, reg_base, reg_index);
-}
-
-void asm_thumb_strh_reg_reg_reg(asm_thumb_t *as, uint reg_val, uint reg_base, uint reg_index) {
-    asm_thumb_lsl_rlo_rlo_i5(as, reg_index, reg_index, 1);
-    asm_thumb_strh_rlo_rlo_rlo(as, reg_val, reg_base, reg_index);
-}
-
-void asm_thumb_str_reg_reg_reg(asm_thumb_t *as, uint reg_val, uint reg_base, uint reg_index) {
-    asm_thumb_lsl_rlo_rlo_i5(as, reg_index, reg_index, 2);
-    asm_thumb_str_rlo_rlo_rlo(as, reg_val, reg_base, reg_index);
-}
-
 // this could be wrong, because it should have a range of +/- 16MiB...
 #define OP_BW_HI(byte_offset) (0xf000 | (((byte_offset) >> 12) & 0x07ff))
 #define OP_BW_LO(byte_offset) (0xb800 | (((byte_offset) >> 1) & 0x07ff))