diff options
| author | Damien George <damien@micropython.org> | 2020-06-25 13:09:07 +1000 |
|---|---|---|
| committer | Damien George <damien@micropython.org> | 2020-06-27 00:24:04 +1000 |
| commit | aa26fe62d8728c95d447475ced9b4a03380025ea (patch) | |
| tree | 6a0147babbb940d6d0aa261a2c3fd41aaa8cd026 /py/asmxtensa.h | |
| parent | 137df817575e06b7bd765fb230a99d108f1d4f61 (diff) | |
py/asm: Add funcs/macros to emit machine code for logical-shift-right.
Signed-off-by: Damien George <damien@micropython.org>
Diffstat (limited to 'py/asmxtensa.h')
| -rw-r--r-- | py/asmxtensa.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/py/asmxtensa.h b/py/asmxtensa.h index 5eb40daf7..43f1b608e 100644 --- a/py/asmxtensa.h +++ b/py/asmxtensa.h @@ -243,6 +243,10 @@ static inline void asm_xtensa_op_sll(asm_xtensa_t *as, uint reg_dest, uint reg_s asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRR(0, 1, 10, reg_dest, reg_src, 0)); } +static inline void asm_xtensa_op_srl(asm_xtensa_t *as, uint reg_dest, uint reg_src) { + asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRR(0, 1, 9, reg_dest, 0, reg_src)); +} + static inline void asm_xtensa_op_sra(asm_xtensa_t *as, uint reg_dest, uint reg_src) { asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRR(0, 1, 11, reg_dest, 0, reg_src)); } @@ -372,6 +376,11 @@ void asm_xtensa_call_ind_win(asm_xtensa_t *as, uint idx); asm_xtensa_op_ssl((as), (reg_shift)); \ asm_xtensa_op_sll((as), (reg_dest), (reg_dest)); \ } while (0) +#define ASM_LSR_REG_REG(as, reg_dest, reg_shift) \ + do { \ + asm_xtensa_op_ssr((as), (reg_shift)); \ + asm_xtensa_op_srl((as), (reg_dest), (reg_dest)); \ + } while (0) #define ASM_ASR_REG_REG(as, reg_dest, reg_shift) \ do { \ asm_xtensa_op_ssr((as), (reg_shift)); \ |