py/emitnative: Optimise Viper register offset load/stores on Xtensa.

This commit improves the emitted code sequences for address generation
in the Viper subsystem when loading/storing 16 and 32 bit values via a
register offset.

The Xtensa opcodes ADDX2 and ADDX4 are used to avoid performing the
extra shifts to align the final operation offset.  Those opcodes are
available on both xtensa and xtensawin MicroPython architectures.

Signed-off-by: Alessandro Gatti <a.gatti@frob.it>

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