diff options
| author | Alessandro Gatti <a.gatti@frob.it> | 2025-05-22 12:34:12 +0200 |
|---|---|---|
| committer | Damien George <damien@micropython.org> | 2025-06-10 11:29:02 +1000 |
| commit | 1f5ba6998bb1895354f5afcd7bb52d83a02733be (patch) | |
| tree | 71345700615e2d3397e77dc79415c343bdec73fd /py/emitnative.c | |
| parent | 78ee1bac60a89f13d62395c1f7b6b122e26af98a (diff) | |
py/asmthumb: Extend load/store generators with ARMv7-M opcodes.
This commit lets the Thumb native code generator backend emit ARMv7-M
specific opcodes for indexed load/store operations if possible.
Now T3 opcode encodings are used if the generator backend is configured
to allow emitting ARMv7-M opcodes and if the (unsigned) scaled index
fits in 12 bits. Or, in other words, LDR{B,H}.W and STR{B,H}.W opcodes
are now emitted if possible.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
Diffstat (limited to 'py/emitnative.c')
| -rw-r--r-- | py/emitnative.c | 43 |
1 files changed, 6 insertions, 37 deletions
diff --git a/py/emitnative.c b/py/emitnative.c index 577bcddfb..c1965fc91 100644 --- a/py/emitnative.c +++ b/py/emitnative.c @@ -1540,12 +1540,7 @@ static void emit_native_load_subscr(emit_t *emit) { #ifdef ASM_LOAD8_REG_REG_OFFSET ASM_LOAD8_REG_REG_OFFSET(emit->as, REG_RET, reg_base, index_value); #else - #if N_THUMB - if (index_value >= 0 && index_value < 32) { - asm_thumb_ldrb_rlo_rlo_i5(emit->as, REG_RET, reg_base, index_value); - break; - } - #elif N_RV32 + #if N_RV32 if (FIT_SIGNED(index_value, 12)) { asm_rv32_opcode_lbu(emit->as, REG_RET, reg_base, index_value); break; @@ -1572,12 +1567,7 @@ static void emit_native_load_subscr(emit_t *emit) { #ifdef ASM_LOAD16_REG_REG_OFFSET ASM_LOAD16_REG_REG_OFFSET(emit->as, REG_RET, reg_base, index_value); #else - #if N_THUMB - if (index_value >= 0 && index_value < 32) { - asm_thumb_ldrh_rlo_rlo_i5(emit->as, REG_RET, reg_base, index_value); - break; - } - #elif N_RV32 + #if N_RV32 if (FIT_SIGNED(index_value, 11)) { asm_rv32_opcode_lhu(emit->as, REG_RET, reg_base, index_value << 1); break; @@ -1604,12 +1594,7 @@ static void emit_native_load_subscr(emit_t *emit) { #ifdef ASM_LOAD32_REG_REG_OFFSET ASM_LOAD32_REG_REG_OFFSET(emit->as, REG_RET, reg_base, index_value); #else - #if N_THUMB - if (index_value >= 0 && index_value < 32) { - asm_thumb_ldr_rlo_rlo_i5(emit->as, REG_RET, reg_base, index_value); - break; - } - #elif N_RV32 + #if N_RV32 if (FIT_SIGNED(index_value, 10)) { asm_rv32_opcode_lw(emit->as, REG_RET, reg_base, index_value << 2); break; @@ -1824,13 +1809,7 @@ static void emit_native_store_subscr(emit_t *emit) { #ifdef ASM_STORE8_REG_REG_OFFSET ASM_STORE8_REG_REG_OFFSET(emit->as, reg_value, reg_base, index_value); #else - // TODO optimise to use thumb strb r1, [r2, r3] - #if N_THUMB - if (index_value >= 0 && index_value < 32) { - asm_thumb_strb_rlo_rlo_i5(emit->as, reg_value, reg_base, index_value); - break; - } - #elif N_RV32 + #if N_RV32 if (FIT_SIGNED(index_value, 12)) { asm_rv32_opcode_sb(emit->as, reg_value, reg_base, index_value); break; @@ -1860,12 +1839,7 @@ static void emit_native_store_subscr(emit_t *emit) { #ifdef ASM_STORE16_REG_REG_OFFSET ASM_STORE16_REG_REG_OFFSET(emit->as, reg_value, reg_base, index_value); #else - #if N_THUMB - if (index_value >= 0 && index_value < 32) { - asm_thumb_strh_rlo_rlo_i5(emit->as, reg_value, reg_base, index_value); - break; - } - #elif N_RV32 + #if N_RV32 if (FIT_SIGNED(index_value, 11)) { asm_rv32_opcode_sh(emit->as, reg_value, reg_base, index_value << 1); break; @@ -1891,12 +1865,7 @@ static void emit_native_store_subscr(emit_t *emit) { #ifdef ASM_STORE32_REG_REG_OFFSET ASM_STORE32_REG_REG_OFFSET(emit->as, reg_value, reg_base, index_value); #else - #if N_THUMB - if (index_value >= 0 && index_value < 32) { - asm_thumb_str_rlo_rlo_i5(emit->as, reg_value, reg_base, index_value); - break; - } - #elif N_RV32 + #if N_RV32 if (FIT_SIGNED(index_value, 10)) { asm_rv32_opcode_sw(emit->as, reg_value, reg_base, index_value << 2); break; |