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| author | Alessandro Gatti <a.gatti@frob.it> | 2025-09-19 14:50:05 +0200 |
|---|---|---|
| committer | Alessandro Gatti <a.gatti@frob.it> | 2025-09-19 15:51:37 +0200 |
| commit | cb7ca6f1bc9c77969d465025f63afdd96892577a (patch) | |
| tree | 54550c5794f8a3d4ac45fc1123e55d98d1fab62c /py/mpconfig.h | |
| parent | 42ea7bc32af49f305ece4f4e4601accea9df0534 (diff) | |
py/asmrv32: Use RV32 Zba opcodes if possible.
This commit adds optional support for selected Zba opcodes (address
generation) to speed up Viper and native code generation on MCUs where
those opcodes are supported (namely RP2350).
Right now support for these opcodes is opt-in, as extension detection
granularity on the RISC-V platform is still a bit in flux. Relying on
the 'B' bit in the MISA register may yield both false positives and
false negatives depending on the RISC-V implementation the check runs
on.
As a side-effect of Zba support, regular non-byte load/stores have been
made shorter by two bytes. Whilst this makes code using Zba take up the
same space as non-Zba code, the former will still be faster as it will
have to process just one instruction instead of two, without stalling
registers between the shift and the addition needed to compute the final
offset.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
Diffstat (limited to 'py/mpconfig.h')
| -rw-r--r-- | py/mpconfig.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/py/mpconfig.h b/py/mpconfig.h index 303eb08f9..ae44b461d 100644 --- a/py/mpconfig.h +++ b/py/mpconfig.h @@ -421,6 +421,11 @@ #define MICROPY_EMIT_RV32 (0) #endif +// Whether to emit RISC-V RV32 Zba opcodes in native code +#ifndef MICROPY_EMIT_RV32_ZBA +#define MICROPY_EMIT_RV32_ZBA (0) +#endif + // Whether to enable the RISC-V RV32 inline assembler #ifndef MICROPY_EMIT_INLINE_RV32 #define MICROPY_EMIT_INLINE_RV32 (0) |