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authoryn386 <wf.yn386@gmail.com>2022-09-14 15:29:15 +0900
committerDamien George <damien@micropython.org>2022-11-18 13:55:14 +1100
commit65d82066a8267d7dd96d747d09f9ed3883d40078 (patch)
tree5d05589e8c91ce9617b8725c337fa2b005cacd35 /py/objstringio.h
parent4dcfd19bbfa5e1009bd4e0fe95f41a47452493f9 (diff)
stm32/pyb_i2c: Fix failing pyb.I2C(dma=True) after receiving 1 byte.
Excuting the code: i2c = I2C(1, I2C.CONTROLLER, dma=True) tmp = i2c.recv(1, i2c_addr) recv_data = bytearray(56) i2c.recv(recv_data, i2c_addr) The second i2c.recv() fails with OSError: [Errno 110] ETIMEDOUT. When receiving greater than or equal to 2 bytes at first i2c.recv(), the second i2c.recv() succeeds. This issue does not occur without DMA. Details of change: when executing I2C with DMA: - Bit 11 of I2Cx_CR2 (DMA Request Enable) should be 1 to indicate that DMA transfer is enabled. This bit is set after I2C event interrupt is enabled in HAL_I2C_Master_Transmit_DMA()/HAL_I2C_Master_Receive_DMA(), so DMA Request Enable bit might be 0 in IRQHandler. - In case of data receive: - When only 1 byte receiption, clear I2Cx_CR1's bit 10 (ACK). - When only 2 byte receiption, clear I2Cx_CR1's bit 10 (ACK) and set bit 11 (POS). - When greater than or equal to 2 byte receiption, bit 12 of I2Cx_CR2 (DMA Last Transfer) should set to generate NACK when DMA transfer completed. Otherwise, the I2C bus may be busy after received data from peripheral.
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