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authorDamien George <damien.p.george@gmail.com>2018-08-17 01:12:05 +1000
committerDamien George <damien.p.george@gmail.com>2018-08-17 14:11:37 +1000
commita0a29724c820340cf574cc174159fde5fabb8fd7 (patch)
tree8d7f77f1e1ce1e0f9a143d83c319445f1f4fd2fe /py
parent1ad44acb1522a44a42bfcb0cd017289918915cbc (diff)
py/emitnative: Fix bug with store of 16 and 32 values in viper ARM mode.
Diffstat (limited to 'py')
-rw-r--r--py/emitnative.c7
1 files changed, 2 insertions, 5 deletions
diff --git a/py/emitnative.c b/py/emitnative.c
index 6756e50ef..5db496a22 100644
--- a/py/emitnative.c
+++ b/py/emitnative.c
@@ -1472,10 +1472,6 @@ STATIC void emit_native_store_subscr(emit_t *emit) {
}
#endif
ASM_MOV_REG_IMM(emit->as, reg_index, index_value << 1);
- #if N_ARM
- asm_arm_strh_reg_reg_reg(emit->as, reg_value, reg_base, reg_index);
- return;
- #endif
ASM_ADD_REG_REG(emit->as, reg_index, reg_base); // add 2*index to base
reg_base = reg_index;
}
@@ -1492,11 +1488,12 @@ STATIC void emit_native_store_subscr(emit_t *emit) {
break;
}
#endif
- ASM_MOV_REG_IMM(emit->as, reg_index, index_value << 2);
#if N_ARM
+ ASM_MOV_REG_IMM(emit->as, reg_index, index_value);
asm_arm_str_reg_reg_reg(emit->as, reg_value, reg_base, reg_index);
return;
#endif
+ ASM_MOV_REG_IMM(emit->as, reg_index, index_value << 2);
ASM_ADD_REG_REG(emit->as, reg_index, reg_base); // add 4*index to base
reg_base = reg_index;
}