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| author | Chris Mason <c.mason@inchipdesign.com.au> | 2019-09-21 18:20:12 +1000 |
|---|---|---|
| committer | Damien George <damien.p.george@gmail.com> | 2019-09-26 17:32:22 +1000 |
| commit | f16e4be3fa16a3532bb93ccf88e867d27fe2ff20 (patch) | |
| tree | 08923a78f24688cf8454d9ccba82b02af6e6b0e6 /py | |
| parent | 3328b7d71f2758d6e278cd5f3c230d427f46ff01 (diff) | |
stm32/powerctrlboot: Fix clock and PLL selection for HSI48 on F0 MCUs.
Before this patch the UART baudrate on F0 MCUs was wrong because the
stm32lib SystemCoreClockUpdate sets SystemCoreClock to 8MHz instead of
48MHz if HSI48 is routed directly to SYSCLK.
The workaround is to use HSI48 -> PREDIV (/2) -> PLL (*2) -> SYSCLK.
Fixes issue #5049.
Diffstat (limited to 'py')
0 files changed, 0 insertions, 0 deletions