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| author | Oliver Joos <oliver.joos@hispeed.ch> | 2025-12-18 13:47:37 +0100 |
|---|---|---|
| committer | Damien George <damien@micropython.org> | 2026-01-14 17:08:08 +1100 |
| commit | 230bbbbdf5793008d2cdfa40b33f7473312c1d55 (patch) | |
| tree | 3bf6452ddde094f476442f7d84ffbbd311a3b839 /tests/net_inet/ssl_cert.py | |
| parent | 6b13e6c4987c6fd103847e7b36a3f0fcd0ff42d9 (diff) | |
stm32/boards/NUCLEO_H7x3: Add UART1, remove UART5, slow down PLL1Q.HEADorigin/masterorigin/HEADmaster
STM32CubeMX shows a conflict of UART5 with ETH MII.
However UART1 can be used with TX and RX on the pin headers.
PLL1Q is reduced from 200 to 100 MHz because it may be used for FDCAN
or SDMMC. FDCAN needs <= 150 MHz, and 100 MHz is enough for an SDCard
connected to pin headers to work reliably.
Signed-off-by: Oliver Joos <oliver.joos@hispeed.ch>
Diffstat (limited to 'tests/net_inet/ssl_cert.py')
0 files changed, 0 insertions, 0 deletions