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-rw-r--r--ports/rp2/CMakeLists.txt1
-rw-r--r--ports/rp2/main.c19
-rw-r--r--ports/rp2/modmachine.c4
-rw-r--r--ports/rp2/mpconfigport.h4
-rw-r--r--ports/rp2/rp2_psram.c198
-rw-r--r--ports/rp2/rp2_psram.h44
6 files changed, 270 insertions, 0 deletions
diff --git a/ports/rp2/CMakeLists.txt b/ports/rp2/CMakeLists.txt
index f89e2792c..1a5029c15 100644
--- a/ports/rp2/CMakeLists.txt
+++ b/ports/rp2/CMakeLists.txt
@@ -165,6 +165,7 @@ set(MICROPY_SOURCE_PORT
pendsv.c
rp2_flash.c
rp2_pio.c
+ rp2_psram.c
rp2_dma.c
uart.c
usbd.c
diff --git a/ports/rp2/main.c b/ports/rp2/main.c
index 58da63c06..764af6b74 100644
--- a/ports/rp2/main.c
+++ b/ports/rp2/main.c
@@ -46,6 +46,7 @@
#include "mpnetworkport.h"
#include "genhdr/mpversion.h"
#include "mp_usbd.h"
+#include "rp2_psram.h"
#include "pico/stdlib.h"
#include "pico/binary_info.h"
@@ -93,6 +94,10 @@ int main(int argc, char **argv) {
// Hook for setting up anything that needs to be super early in the boot-up process.
MICROPY_BOARD_STARTUP();
+ #if MICROPY_HW_ENABLE_PSRAM
+ size_t psram_size = psram_init(MICROPY_HW_PSRAM_CS_PIN);
+ #endif
+
#if MICROPY_HW_ENABLE_UART_REPL
bi_decl(bi_program_feature("UART REPL"))
setup_default_uart();
@@ -120,7 +125,21 @@ int main(int argc, char **argv) {
// Initialise stack extents and GC heap.
mp_cstack_init_with_top(&__StackTop, &__StackTop - &__StackBottom);
+
+ #if MICROPY_HW_ENABLE_PSRAM
+ if (psram_size) {
+ #if MICROPY_GC_SPLIT_HEAP
+ gc_init(&__GcHeapStart, &__GcHeapEnd);
+ gc_add((void *)PSRAM_BASE, (void *)(PSRAM_BASE + psram_size));
+ #else
+ gc_init((void *)PSRAM_BASE, (void *)(PSRAM_BASE + psram_size));
+ #endif
+ } else {
+ gc_init(&__GcHeapStart, &__GcHeapEnd);
+ }
+ #else
gc_init(&__GcHeapStart, &__GcHeapEnd);
+ #endif
#if MICROPY_PY_LWIP
// lwIP doesn't allow to reinitialise itself by subsequent calls to this function
diff --git a/ports/rp2/modmachine.c b/ports/rp2/modmachine.c
index 31665a764..bf4e43a61 100644
--- a/ports/rp2/modmachine.c
+++ b/ports/rp2/modmachine.c
@@ -31,6 +31,7 @@
#include "mp_usbd.h"
#include "modmachine.h"
#include "uart.h"
+#include "rp2_psram.h"
#include "clocks_extra.h"
#include "hardware/pll.h"
#include "hardware/structs/rosc.h"
@@ -115,6 +116,9 @@ static void mp_machine_set_freq(size_t n_args, const mp_obj_t *args) {
setup_default_uart();
mp_uart_init();
#endif
+ #if MICROPY_HW_ENABLE_PSRAM
+ psram_init(MICROPY_HW_PSRAM_CS_PIN);
+ #endif
}
static void mp_machine_idle(void) {
diff --git a/ports/rp2/mpconfigport.h b/ports/rp2/mpconfigport.h
index 38dcad1da..28022ba42 100644
--- a/ports/rp2/mpconfigport.h
+++ b/ports/rp2/mpconfigport.h
@@ -81,6 +81,10 @@
#define MICROPY_CONFIG_ROM_LEVEL (MICROPY_CONFIG_ROM_LEVEL_EXTRA_FEATURES)
#endif
+#ifndef MICROPY_HW_ENABLE_PSRAM
+#define MICROPY_HW_ENABLE_PSRAM (0)
+#endif
+
// Memory allocation policies
#define MICROPY_GC_STACK_ENTRY_TYPE uint16_t
#define MICROPY_ALLOC_PATH_MAX (128)
diff --git a/ports/rp2/rp2_psram.c b/ports/rp2/rp2_psram.c
new file mode 100644
index 000000000..bb063f4af
--- /dev/null
+++ b/ports/rp2/rp2_psram.c
@@ -0,0 +1,198 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2025 Phil Howard
+ * Mike Bell
+ * Kirk D. Benell
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "py/mphal.h"
+
+#if MICROPY_HW_ENABLE_PSRAM
+
+#include "hardware/structs/ioqspi.h"
+#include "hardware/structs/qmi.h"
+#include "hardware/structs/xip_ctrl.h"
+#include "hardware/clocks.h"
+#include "hardware/sync.h"
+#include "rp2_psram.h"
+
+size_t __no_inline_not_in_flash_func(psram_detect)(void) {
+ int psram_size = 0;
+
+ // Try and read the PSRAM ID via direct_csr.
+ qmi_hw->direct_csr = 30 << QMI_DIRECT_CSR_CLKDIV_LSB | QMI_DIRECT_CSR_EN_BITS;
+
+ // Need to poll for the cooldown on the last XIP transfer to expire
+ // (via direct-mode BUSY flag) before it is safe to perform the first
+ // direct-mode operation
+ while ((qmi_hw->direct_csr & QMI_DIRECT_CSR_BUSY_BITS) != 0) {
+ }
+
+ // Exit out of QMI in case we've inited already
+ qmi_hw->direct_csr |= QMI_DIRECT_CSR_ASSERT_CS1N_BITS;
+
+ // Transmit as quad.
+ qmi_hw->direct_tx = QMI_DIRECT_TX_OE_BITS | QMI_DIRECT_TX_IWIDTH_VALUE_Q << QMI_DIRECT_TX_IWIDTH_LSB | 0xf5;
+
+ while ((qmi_hw->direct_csr & QMI_DIRECT_CSR_BUSY_BITS) != 0) {
+ }
+
+ (void)qmi_hw->direct_rx;
+
+ qmi_hw->direct_csr &= ~(QMI_DIRECT_CSR_ASSERT_CS1N_BITS);
+
+ // Read the id
+ qmi_hw->direct_csr |= QMI_DIRECT_CSR_ASSERT_CS1N_BITS;
+ uint8_t kgd = 0;
+ uint8_t eid = 0;
+
+ for (size_t i = 0; i < 7; i++) {
+ if (i == 0) {
+ qmi_hw->direct_tx = 0x9f;
+ } else {
+ qmi_hw->direct_tx = 0xff;
+ }
+
+ while ((qmi_hw->direct_csr & QMI_DIRECT_CSR_TXEMPTY_BITS) == 0) {
+ }
+
+ while ((qmi_hw->direct_csr & QMI_DIRECT_CSR_BUSY_BITS) != 0) {
+ }
+
+ if (i == 5) {
+ kgd = qmi_hw->direct_rx;
+ } else if (i == 6) {
+ eid = qmi_hw->direct_rx;
+ } else {
+ (void)qmi_hw->direct_rx;
+ }
+ }
+
+ // Disable direct csr.
+ qmi_hw->direct_csr &= ~(QMI_DIRECT_CSR_ASSERT_CS1N_BITS | QMI_DIRECT_CSR_EN_BITS);
+
+ if (kgd == 0x5D) {
+ psram_size = 1024 * 1024; // 1 MiB
+ uint8_t size_id = eid >> 5;
+ if (eid == 0x26 || size_id == 2) {
+ psram_size *= 8; // 8 MiB
+ } else if (size_id == 0) {
+ psram_size *= 2; // 2 MiB
+ } else if (size_id == 1) {
+ psram_size *= 4; // 4 MiB
+ }
+ }
+
+ return psram_size;
+}
+
+size_t __no_inline_not_in_flash_func(psram_init)(uint cs_pin) {
+ gpio_set_function(cs_pin, GPIO_FUNC_XIP_CS1);
+
+ uint32_t intr_stash = save_and_disable_interrupts();
+
+ size_t psram_size = psram_detect();
+
+ if (!psram_size) {
+ restore_interrupts(intr_stash);
+ return 0;
+ }
+
+ // Enable direct mode, PSRAM CS, clkdiv of 10.
+ qmi_hw->direct_csr = 10 << QMI_DIRECT_CSR_CLKDIV_LSB | \
+ QMI_DIRECT_CSR_EN_BITS | \
+ QMI_DIRECT_CSR_AUTO_CS1N_BITS;
+ while (qmi_hw->direct_csr & QMI_DIRECT_CSR_BUSY_BITS) {
+ }
+
+ // Enable QPI mode on the PSRAM
+ const uint CMD_QPI_EN = 0x35;
+ qmi_hw->direct_tx = QMI_DIRECT_TX_NOPUSH_BITS | CMD_QPI_EN;
+
+ while (qmi_hw->direct_csr & QMI_DIRECT_CSR_BUSY_BITS) {
+ }
+
+ // Set PSRAM timing for APS6404
+ //
+ // Using an rxdelay equal to the divisor isn't enough when running the APS6404 close to 133MHz.
+ // So: don't allow running at divisor 1 above 100MHz (because delay of 2 would be too late),
+ // and add an extra 1 to the rxdelay if the divided clock is > 100MHz (i.e. sys clock > 200MHz).
+ const int max_psram_freq = 133000000;
+ const int clock_hz = clock_get_hz(clk_sys);
+ int divisor = (clock_hz + max_psram_freq - 1) / max_psram_freq;
+ if (divisor == 1 && clock_hz > 100000000) {
+ divisor = 2;
+ }
+ int rxdelay = divisor;
+ if (clock_hz / divisor > 100000000) {
+ rxdelay += 1;
+ }
+
+ // - Max select must be <= 8us. The value is given in multiples of 64 system clocks.
+ // - Min deselect must be >= 18ns. The value is given in system clock cycles - ceil(divisor / 2).
+ const int clock_period_fs = 1000000000000000ll / clock_hz;
+ const int max_select = (125 * 1000000) / clock_period_fs; // 125 = 8000ns / 64
+ const int min_deselect = (18 * 1000000 + (clock_period_fs - 1)) / clock_period_fs - (divisor + 1) / 2;
+
+ qmi_hw->m[1].timing = 1 << QMI_M1_TIMING_COOLDOWN_LSB |
+ QMI_M1_TIMING_PAGEBREAK_VALUE_1024 << QMI_M1_TIMING_PAGEBREAK_LSB |
+ max_select << QMI_M1_TIMING_MAX_SELECT_LSB |
+ min_deselect << QMI_M1_TIMING_MIN_DESELECT_LSB |
+ rxdelay << QMI_M1_TIMING_RXDELAY_LSB |
+ divisor << QMI_M1_TIMING_CLKDIV_LSB;
+
+ // Set PSRAM commands and formats
+ qmi_hw->m[1].rfmt =
+ QMI_M0_RFMT_PREFIX_WIDTH_VALUE_Q << QMI_M0_RFMT_PREFIX_WIDTH_LSB | \
+ QMI_M0_RFMT_ADDR_WIDTH_VALUE_Q << QMI_M0_RFMT_ADDR_WIDTH_LSB | \
+ QMI_M0_RFMT_SUFFIX_WIDTH_VALUE_Q << QMI_M0_RFMT_SUFFIX_WIDTH_LSB | \
+ QMI_M0_RFMT_DUMMY_WIDTH_VALUE_Q << QMI_M0_RFMT_DUMMY_WIDTH_LSB | \
+ QMI_M0_RFMT_DATA_WIDTH_VALUE_Q << QMI_M0_RFMT_DATA_WIDTH_LSB | \
+ QMI_M0_RFMT_PREFIX_LEN_VALUE_8 << QMI_M0_RFMT_PREFIX_LEN_LSB | \
+ 6 << QMI_M0_RFMT_DUMMY_LEN_LSB;
+
+ qmi_hw->m[1].rcmd = 0xEB;
+
+ qmi_hw->m[1].wfmt =
+ QMI_M0_WFMT_PREFIX_WIDTH_VALUE_Q << QMI_M0_WFMT_PREFIX_WIDTH_LSB | \
+ QMI_M0_WFMT_ADDR_WIDTH_VALUE_Q << QMI_M0_WFMT_ADDR_WIDTH_LSB | \
+ QMI_M0_WFMT_SUFFIX_WIDTH_VALUE_Q << QMI_M0_WFMT_SUFFIX_WIDTH_LSB | \
+ QMI_M0_WFMT_DUMMY_WIDTH_VALUE_Q << QMI_M0_WFMT_DUMMY_WIDTH_LSB | \
+ QMI_M0_WFMT_DATA_WIDTH_VALUE_Q << QMI_M0_WFMT_DATA_WIDTH_LSB | \
+ QMI_M0_WFMT_PREFIX_LEN_VALUE_8 << QMI_M0_WFMT_PREFIX_LEN_LSB;
+
+ qmi_hw->m[1].wcmd = 0x38;
+
+ // Disable direct mode
+ qmi_hw->direct_csr = 0;
+
+ // Enable writes to PSRAM
+ hw_set_bits(&xip_ctrl_hw->ctrl, XIP_CTRL_WRITABLE_M1_BITS);
+
+ restore_interrupts(intr_stash);
+
+ return psram_size;
+}
+
+#endif
diff --git a/ports/rp2/rp2_psram.h b/ports/rp2/rp2_psram.h
new file mode 100644
index 000000000..0eddf6341
--- /dev/null
+++ b/ports/rp2/rp2_psram.h
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2025 Phil Howard
+ * Mike Bell
+ * Kirk D. Benell
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "pico/stdlib.h"
+
+#ifndef MICROPY_INCLUDED_RP2_RP2_PSRAM_H
+#define MICROPY_INCLUDED_RP2_RP2_PSRAM_H
+
+#if MICROPY_HW_ENABLE_PSRAM
+#ifndef MICROPY_HW_PSRAM_CS_PIN
+#error "MICROPY_HW_ENABLE_PSRAM requires MICROPY_HW_PSRAM_CS_PIN"
+#endif
+
+#define PSRAM_BASE _u(0x11000000)
+
+extern size_t psram_init(uint cs_pin);
+#endif
+
+#endif
generated by cgit v1.2.3 (git 2.46.0) at 2025-11-17 05:24:20 +0000