diff options
| -rw-r--r-- | ports/stm32/boards/OPENMV_N6/bdev.c | 41 | ||||
| -rw-r--r-- | ports/stm32/boards/OPENMV_N6/board.c | 131 | ||||
| -rw-r--r-- | ports/stm32/boards/OPENMV_N6/board.ld | 39 | ||||
| -rw-r--r-- | ports/stm32/boards/OPENMV_N6/manifest.py | 3 | ||||
| -rw-r--r-- | ports/stm32/boards/OPENMV_N6/mpconfigboard.h | 167 | ||||
| -rw-r--r-- | ports/stm32/boards/OPENMV_N6/mpconfigboard.mk | 30 | ||||
| -rw-r--r-- | ports/stm32/boards/OPENMV_N6/partition_stm32n657xx.h | 5 | ||||
| -rw-r--r-- | ports/stm32/boards/OPENMV_N6/pins.csv | 142 | ||||
| -rw-r--r-- | ports/stm32/boards/OPENMV_N6/stm32n6xx_hal_conf.h | 18 |
9 files changed, 576 insertions, 0 deletions
diff --git a/ports/stm32/boards/OPENMV_N6/bdev.c b/ports/stm32/boards/OPENMV_N6/bdev.c new file mode 100644 index 000000000..c6c918bd6 --- /dev/null +++ b/ports/stm32/boards/OPENMV_N6/bdev.c @@ -0,0 +1,41 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2025 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "storage.h" +#include "xspi.h" + +#if MICROPY_HW_SPIFLASH_ENABLE_CACHE +#error "Cannot enable MICROPY_HW_SPIFLASH_ENABLE_CACHE" +#endif + +// External SPI flash uses hardware XSPI interface. +const mp_spiflash_config_t spiflash_config = { + .bus_kind = MP_SPIFLASH_BUS_QSPI, + .bus.u_qspi.data = (void *)&xspi_flash2, + .bus.u_qspi.proto = &xspi_proto, +}; + +spi_bdev_t spi_bdev; diff --git a/ports/stm32/boards/OPENMV_N6/board.c b/ports/stm32/boards/OPENMV_N6/board.c new file mode 100644 index 000000000..1f82d10ba --- /dev/null +++ b/ports/stm32/boards/OPENMV_N6/board.c @@ -0,0 +1,131 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2024-2025 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/mphal.h" +#include "boardctrl.h" +#include "xspi.h" + +// Values for OTP fuses for VDDIO2/3, to select low voltage mode (<2.5V). +// See RM0486, Section 5, Table 18. +#define BSEC_HW_CONFIG_ID (124U) +#define BSEC_HWS_HSLV_VDDIO3 (1U << 15) +#define BSEC_HWS_HSLV_VDDIO2 (1U << 16) + +#define OMV_BOOT_MAGIC_ADDR (0x3401FFFCU) +#define OMV_BOOT_MAGIC_VALUE (0xB00710ADU) + +void mboot_board_early_init(void) { + // TODO: move some of the below code to a common location for all N6 boards? + + // Enable PWR, BSEC and SYSCFG clocks. + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR); + LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_BSEC); + LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_SYSCFG); + + // Program high speed IO optimization fuses if they aren't already set. + uint32_t fuse; + BSEC_HandleTypeDef hbsec = { .Instance = BSEC }; + const uint32_t mask = BSEC_HWS_HSLV_VDDIO2 | BSEC_HWS_HSLV_VDDIO3; + if (HAL_BSEC_OTP_Read(&hbsec, BSEC_HW_CONFIG_ID, &fuse) != HAL_OK) { + fuse = 0; + } else if ((fuse & mask) != mask) { + // Program the fuse, and read back the set value. + if (HAL_BSEC_OTP_Program(&hbsec, BSEC_HW_CONFIG_ID, fuse | mask, HAL_BSEC_NORMAL_PROG) != HAL_OK) { + fuse = 0; + } else if (HAL_BSEC_OTP_Read(&hbsec, BSEC_HW_CONFIG_ID, &fuse) != HAL_OK) { + fuse = 0; + } + } + + // Enable Vdd ADC, needed for the ADC to work. + LL_PWR_EnableVddADC(); + + // Configure VDDIO2. Only enable 1.8V mode if the fuse is set. + LL_PWR_EnableVddIO2(); + if (fuse & BSEC_HWS_HSLV_VDDIO2) { + LL_PWR_SetVddIO2VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_1V8); + } + SYSCFG->VDDIO2CCCR |= SYSCFG_VDDIO2CCCR_EN; // enable IO compensation + + // Configure VDDIO3. Only enable 1.8V mode if the fuse is set. + LL_PWR_EnableVddIO3(); + if (fuse & BSEC_HWS_HSLV_VDDIO3) { + LL_PWR_SetVddIO3VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_1V8); + } + SYSCFG->VDDIO3CCCR |= SYSCFG_VDDIO3CCCR_EN; // enable IO compensation + + // Configure VDDIO4. + LL_PWR_EnableVddIO4(); + LL_PWR_SetVddIO4VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_3V3); + SYSCFG->VDDIO4CCCR |= SYSCFG_VDDIO4CCCR_EN; // enable IO compensation + + // Enable VDD for ADC and USB. + LL_PWR_EnableVddADC(); + LL_PWR_EnableVddUSB(); + + // Enable XSPI in memory-mapped mode. + xspi_init(); +} + +void board_enter_bootloader(unsigned int n_args, const void *args) { + // Support both OpenMV bootloader and mboot. + *((uint32_t *)OMV_BOOT_MAGIC_ADDR) = OMV_BOOT_MAGIC_VALUE; + SCB_CleanDCache(); + boardctrl_maybe_enter_mboot(n_args, args); +} + +void board_early_init(void) { + // TODO: if (HAL_PWREx_ConfigSupply(PWR_EXTERNAL_SOURCE_SUPPLY ) != HAL_OK) + + LL_PWR_EnableWakeUpPin(LL_PWR_WAKEUP_PIN3 | LL_PWR_WAKEUP_PIN2); + LL_PWR_SetWakeUpPinPolarityLow(LL_PWR_WAKEUP_PIN3 | LL_PWR_WAKEUP_PIN2); +} + +void board_leave_standby(void) { + // TODO: move some of the below code to a common location for all N6 boards? + + // Enable PWR, BSEC and SYSCFG clocks. + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR); + LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_BSEC); + LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_SYSCFG); + + // Configure VDDIO2 (1.8V mode selection is retained). + LL_PWR_EnableVddIO2(); + SYSCFG->VDDIO2CCCR |= SYSCFG_VDDIO2CCCR_EN; // enable IO compensation + + // Configure VDDIO3 (1.8V mode selection is retained). + LL_PWR_EnableVddIO3(); + SYSCFG->VDDIO3CCCR |= SYSCFG_VDDIO3CCCR_EN; // enable IO compensation + + // Configure VDDIO4. + LL_PWR_EnableVddIO4(); + LL_PWR_SetVddIO4VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_3V3); + SYSCFG->VDDIO4CCCR |= SYSCFG_VDDIO4CCCR_EN; // enable IO compensation + + // Enable VDD for ADC and USB. + LL_PWR_EnableVddADC(); + LL_PWR_EnableVddUSB(); +} diff --git a/ports/stm32/boards/OPENMV_N6/board.ld b/ports/stm32/boards/OPENMV_N6/board.ld new file mode 100644 index 000000000..e9ded785f --- /dev/null +++ b/ports/stm32/boards/OPENMV_N6/board.ld @@ -0,0 +1,39 @@ +/* + Linker script for OPENMV_N6. + + Note: upper 512k of SRAM2 is copied from external flash upon reset. +*/ + +/* Specify the memory areas */ +MEMORY +{ + FLEXRAM_S (xrw) : ORIGIN = 0x34000000, LENGTH = 80K + SRAM2_S_RAM (xrw) : ORIGIN = 0x34100000, LENGTH = 1024K + SRAM2_S_FSBL (xrw) : ORIGIN = 0x34180400, LENGTH = 511K /* mboot firmware, not needed after mboot exits */ + EXT_FLASH (rx) : ORIGIN = 0x70080000, LENGTH = 3584K + EXT_FLASH_FS (rx) : ORIGIN = 0x70400000, LENGTH = 4M + EXT_FLASH_ROMFS (rx) : ORIGIN = 0x70800000, LENGTH = 24M +} + +REGION_ALIAS("IRAM", FLEXRAM_S); +REGION_ALIAS("RAM", SRAM2_S_RAM); +REGION_ALIAS("FLASH_APP", EXT_FLASH); + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 2K; +_minimum_heap_size = 16K; + +/* Define the stack. The stack is full descending so begins just above last byte + of RAM. Note that EABI requires the stack to be 8-byte aligned for a call. */ +_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve; +_sstack = _estack - 16K; /* tunable */ + +/* RAM extents for the garbage collector */ +_ram_start = ORIGIN(RAM); +_ram_end = ORIGIN(RAM) + LENGTH(RAM); +_heap_start = _ebss; /* heap starts just after statically allocated memory */ +_heap_end = _sstack; + +/* ROMFS location */ +_micropy_hw_romfs_part0_start = ORIGIN(EXT_FLASH_ROMFS); +_micropy_hw_romfs_part0_size = LENGTH(EXT_FLASH_ROMFS); diff --git a/ports/stm32/boards/OPENMV_N6/manifest.py b/ports/stm32/boards/OPENMV_N6/manifest.py new file mode 100644 index 000000000..62990220f --- /dev/null +++ b/ports/stm32/boards/OPENMV_N6/manifest.py @@ -0,0 +1,3 @@ +include("$(PORT_DIR)/boards/manifest.py") +require("bundle-networking") +require("aioble") diff --git a/ports/stm32/boards/OPENMV_N6/mpconfigboard.h b/ports/stm32/boards/OPENMV_N6/mpconfigboard.h new file mode 100644 index 000000000..ed7bb548a --- /dev/null +++ b/ports/stm32/boards/OPENMV_N6/mpconfigboard.h @@ -0,0 +1,167 @@ +#define MICROPY_HW_BOARD_NAME "OpenMV N6" +#define MICROPY_HW_MCU_NAME "STM32N657X0" + +#define MICROPY_GC_STACK_ENTRY_TYPE uint32_t +#define MICROPY_ALLOC_GC_STACK_SIZE (128) +#define MICROPY_FATFS_EXFAT (1) + +#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (0) +#define MICROPY_HW_HAS_SWITCH (0) +#define MICROPY_HW_HAS_FLASH (1) +#define MICROPY_HW_SDCARD_MOUNT_AT_BOOT (0) +#define MICROPY_HW_ENABLE_RNG (1) +#define MICROPY_HW_ENABLE_RTC (1) +#define MICROPY_HW_ENABLE_DAC (0) +#define MICROPY_HW_ENABLE_USB (1) +#define MICROPY_HW_ENABLE_SDCARD (1) +#define MICROPY_PY_PYB_LEGACY (0) + +#define MICROPY_BOARD_ENTER_BOOTLOADER board_enter_bootloader +#define MICROPY_BOARD_EARLY_INIT board_early_init +#define MICROPY_BOARD_LEAVE_STANDBY board_leave_standby() + +// HSE is 48MHz, this gives a CPU frequency of 800MHz. +#define MICROPY_HW_CLK_PLLM (6) +#define MICROPY_HW_CLK_PLLN (100) +#define MICROPY_HW_CLK_PLLP1 (1) +#define MICROPY_HW_CLK_PLLP2 (1) +#define MICROPY_HW_CLK_PLLFRAC (0) + +// The LSE is a 32kHz crystal. +#define MICROPY_HW_RTC_USE_LSE (1) +#define MICROPY_HW_RTC_USE_US (1) + +// External SPI flash. +#define MICROPY_HW_XSPIFLASH_SIZE_BITS_LOG2 (28) // 256Mbit + +// ROMFS config +#define MICROPY_HW_ROMFS_ENABLE_EXTERNAL_XSPI (1) +#define MICROPY_HW_ROMFS_XSPI_SPIBDEV_OBJ (&spi_bdev) +#define MICROPY_HW_ROMFS_ENABLE_PART0 (1) + +// SPI flash, block device config. +#define MICROPY_HW_BDEV_SPIFLASH (&spi_bdev) +#define MICROPY_HW_BDEV_SPIFLASH_EXTENDED (&spi_bdev) +#define MICROPY_HW_BDEV_SPIFLASH_CONFIG (&spiflash_config) +#define MICROPY_HW_BDEV_SPIFLASH_OFFSET_BYTES (4 * 1024 * 1024) +#define MICROPY_HW_BDEV_SPIFLASH_SIZE_BYTES (4 * 1024 * 1024) + +// UART buses +#define MICROPY_HW_UART2_TX (pyb_pin_BT_TXD) +#define MICROPY_HW_UART2_RX (pyb_pin_BT_RXD) +#define MICROPY_HW_UART2_RTS (pyb_pin_BT_RTS) +#define MICROPY_HW_UART2_CTS (pyb_pin_BT_CTS) +#define MICROPY_HW_UART3_TX (pyb_pin_UART3_TX) +#define MICROPY_HW_UART3_RX (pyb_pin_UART3_RX) +#define MICROPY_HW_UART4_TX (pyb_pin_UART4_TX) +#define MICROPY_HW_UART4_RX (pyb_pin_UART4_RX) +#define MICROPY_HW_UART7_TX (pyb_pin_UART7_TX) +#define MICROPY_HW_UART7_RX (pyb_pin_UART7_RX) + +// I2C buses +#define MICROPY_HW_I2C2_SCL (pyb_pin_I2C2_SCL) +#define MICROPY_HW_I2C2_SDA (pyb_pin_I2C2_SDA) +#define MICROPY_HW_I2C4_SCL (pyb_pin_I2C4_SCL) +#define MICROPY_HW_I2C4_SDA (pyb_pin_I2C4_SDA) + +// SPI buses +#define MICROPY_HW_SPI2_NSS (pyb_pin_SPI2_CS) +#define MICROPY_HW_SPI2_SCK (pyb_pin_SPI2_SCK) +#define MICROPY_HW_SPI2_MISO (pyb_pin_SPI2_MISO) +#define MICROPY_HW_SPI2_MOSI (pyb_pin_SPI2_MOSI) +#define MICROPY_HW_SPI4_NSS (pyb_pin_SPI4_CS) +#define MICROPY_HW_SPI4_SCK (pyb_pin_SPI4_SCK) +#define MICROPY_HW_SPI4_MISO (pyb_pin_SPI4_MISO) +#define MICROPY_HW_SPI4_MOSI (pyb_pin_SPI4_MOSI) + +// USER is pulled high, and pressing the button makes the input go low. +#define MICROPY_HW_USRSW_PIN (pyb_pin_BUTTON) +#define MICROPY_HW_USRSW_PULL (GPIO_NOPULL) +#define MICROPY_HW_USRSW_EXTI_MODE (GPIO_MODE_IT_FALLING) +#define MICROPY_HW_USRSW_PRESSED (0) + +// LEDs +#define MICROPY_HW_LED1 (pyb_pin_LED_RED) +#define MICROPY_HW_LED2 (pyb_pin_LED_GREEN) +#define MICROPY_HW_LED3 (pyb_pin_LED_BLUE) +#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_low(pin)) +#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_high(pin)) + +// SD Card SDMMC +// SD_VSELECT: low(default)=3.3V IO, high=1.8V IO +// SD_RESET: drive low to turn off SD VCC (pulled high by default) +// SD_DETECT: pulled high in hardware, goes low when SD inserted +#define MICROPY_HW_SDCARD_SDMMC (1) +#define MICROPY_HW_SDCARD_CK (pyb_pin_SD_SDIO_CK) +#define MICROPY_HW_SDCARD_CMD (pyb_pin_SD_SDIO_CMD) +#define MICROPY_HW_SDCARD_D0 (pyb_pin_SD_SDIO_D0) +#define MICROPY_HW_SDCARD_D1 (pyb_pin_SD_SDIO_D1) +#define MICROPY_HW_SDCARD_D2 (pyb_pin_SD_SDIO_D2) +#define MICROPY_HW_SDCARD_D3 (pyb_pin_SD_SDIO_D3) +#define MICROPY_HW_SDCARD_DETECT_PIN (pyb_pin_SD_DETECT) +#define MICROPY_HW_SDCARD_DETECT_PULL (GPIO_NOPULL) +#define MICROPY_HW_SDCARD_DETECT_PRESENT (GPIO_PIN_RESET) + +// WiFi SDMMC +#define MICROPY_HW_SDIO_SDMMC (2) +#define MICROPY_HW_SDIO_CK (pyb_pin_WL_SDIO_CK) +#define MICROPY_HW_SDIO_CMD (pyb_pin_WL_SDIO_CMD) +#define MICROPY_HW_SDIO_D0 (pyb_pin_WL_SDIO_D0) +#define MICROPY_HW_SDIO_D1 (pyb_pin_WL_SDIO_D1) +#define MICROPY_HW_SDIO_D2 (pyb_pin_WL_SDIO_D2) +#define MICROPY_HW_SDIO_D3 (pyb_pin_WL_SDIO_D3) + +// USB config +#define MICROPY_HW_USB_HS (1) +#define MICROPY_HW_USB_HS_IN_FS (1) +#define MICROPY_HW_USB_MAIN_DEV (USB_PHY_HS_ID) +#define MICROPY_HW_USB_VID 0x37C5 +#define MICROPY_HW_USB_PID 0x1206 +#define MICROPY_HW_USB_PID_CDC (MICROPY_HW_USB_PID) +#define MICROPY_HW_USB_PID_MSC (MICROPY_HW_USB_PID) +#define MICROPY_HW_USB_PID_CDC_MSC (MICROPY_HW_USB_PID) +#define MICROPY_HW_USB_PID_CDC_HID (MICROPY_HW_USB_PID) +#define MICROPY_HW_USB_PID_CDC_MSC_HID (MICROPY_HW_USB_PID) + +// Murata 1YN configuration +#define CYW43_CHIPSET_FIRMWARE_INCLUDE_FILE "lib/cyw43-driver/firmware/w43439_sdio_1yn_7_95_59_combined.h" +#define CYW43_WIFI_NVRAM_INCLUDE_FILE "lib/cyw43-driver/firmware/wifi_nvram_1yn.h" +#define CYW43_BT_FIRMWARE_INCLUDE_FILE "lib/cyw43-driver/firmware/cyw43_btfw_1yn.h" + +// Bluetooth config +#define MICROPY_HW_BLE_UART_ID (PYB_UART_2) +#define MICROPY_HW_BLE_UART_BAUDRATE (115200) +#define MICROPY_HW_BLE_UART_BAUDRATE_SECONDARY (3000000) +#define MICROPY_HW_BLE_UART_BAUDRATE_DOWNLOAD_FIRMWARE (3000000) + +/******************************************************************************/ +// Bootloader configuration + +#define MBOOT_BOARD_EARLY_INIT(initial_r0) mboot_board_early_init() + +#define MBOOT_FSLOAD (1) +#define MBOOT_VFS_FAT (1) + +#define MBOOT_SPIFLASH_CS (pyb_pin_XSPIM_P2_CS) +#define MBOOT_SPIFLASH_SCK (pyb_pin_XSPIM_P2_SCK) +#define MBOOT_SPIFLASH_MOSI (pyb_pin_XSPIM_P2_IO0) +#define MBOOT_SPIFLASH_MISO (pyb_pin_XSPIM_P2_IO1) +#define MBOOT_SPIFLASH_ADDR (0x70000000) +#define MBOOT_SPIFLASH_BYTE_SIZE (32 * 1024 * 1024) +#define MBOOT_SPIFLASH_LAYOUT "/0x70000000/8192*4Kg" +#define MBOOT_SPIFLASH_ERASE_BLOCKS_PER_PAGE (1) +#define MBOOT_SPIFLASH_SPIFLASH (&spi_bdev.spiflash) +#define MBOOT_SPIFLASH_CONFIG (&spiflash_config) + +/******************************************************************************/ +// Function and variable declarations + +extern const struct _mp_spiflash_config_t spiflash_config; +extern struct _spi_bdev_t spi_bdev; + +void mboot_board_early_init(void); +void mboot_board_entry_init(void); + +void board_enter_bootloader(unsigned int n_args, const void *args); +void board_early_init(void); +void board_leave_standby(void); diff --git a/ports/stm32/boards/OPENMV_N6/mpconfigboard.mk b/ports/stm32/boards/OPENMV_N6/mpconfigboard.mk new file mode 100644 index 000000000..0283a486c --- /dev/null +++ b/ports/stm32/boards/OPENMV_N6/mpconfigboard.mk @@ -0,0 +1,30 @@ +# This board requires a bootloader, either mboot or OpenMV's bootloader. +USE_MBOOT = 1 + +MCU_SERIES = n6 +CMSIS_MCU = STM32N657xx +AF_FILE = boards/stm32n657_af.csv +ifeq ($(BUILDING_MBOOT),1) +SYSTEM_FILE = $(STM32LIB_CMSIS_BASE)/Source/Templates/system_stm32$(MCU_SERIES)xx_fsbl.o +else +SYSTEM_FILE = $(STM32LIB_CMSIS_BASE)/Source/Templates/system_stm32$(MCU_SERIES)xx_s.o +endif +STM32_N6_HEADER_VERSION = 2.3 +DKEL = $(STM32_CUBE_PROGRAMMER)/bin/ExternalLoader/MX25UM51245G_STM32N6570-NUCLEO.stldr + +LD_FILES = boards/OPENMV_N6/board.ld boards/common_n6_flash.ld +TEXT0_ADDR = 0x70080000 + +# MicroPython settings +MICROPY_FLOAT_IMPL = double +MICROPY_PY_BLUETOOTH ?= 1 +MICROPY_BLUETOOTH_NIMBLE ?= 1 +MICROPY_BLUETOOTH_BTSTACK ?= 0 +MICROPY_PY_LWIP ?= 1 +MICROPY_PY_NETWORK_CYW43 ?= 1 +MICROPY_PY_SSL ?= 1 +MICROPY_SSL_MBEDTLS ?= 1 +MICROPY_VFS_LFS2 ?= 1 + +# Board specific frozen modules +FROZEN_MANIFEST ?= $(BOARD_DIR)/manifest.py diff --git a/ports/stm32/boards/OPENMV_N6/partition_stm32n657xx.h b/ports/stm32/boards/OPENMV_N6/partition_stm32n657xx.h new file mode 100644 index 000000000..ac38dac74 --- /dev/null +++ b/ports/stm32/boards/OPENMV_N6/partition_stm32n657xx.h @@ -0,0 +1,5 @@ +// This board does not use any security settings, so can just stay in secure +// mode without configuring the SAU. + +static inline void TZ_SAU_Setup(void) { +} diff --git a/ports/stm32/boards/OPENMV_N6/pins.csv b/ports/stm32/boards/OPENMV_N6/pins.csv new file mode 100644 index 000000000..b05b8b57f --- /dev/null +++ b/ports/stm32/boards/OPENMV_N6/pins.csv @@ -0,0 +1,142 @@ +,PA0 +,PA1 +,PA2 +,PA3 +,PA4 +,PA5 +,PA6 +,PA7 +,PA8 +,PA9 +,PA10 +SPI2_CS,PA11 +SPI2_SCK,PA12 +UART4_RX,PA11 +UART4_TX,PA12 +P3,PA11 +P2,PA12 +,PA13 +,PA14 +,PA15 +,PB0 +,PB1 +,PB2 +,PB3 +,PB4 +,PB5 +SPI4_MISO,PB6 +SPI4_MOSI,PB7 +,PB8 +,PB9 +I2C2_SCL,PB10 +I2C2_SDA,PB11 +UART3_TX,PB10 +UART3_RX,PB11 +P4,PB10 +P5,PB11 +,PB12 +,PB13 +,PB14 +,PB15 +,PC0 +,PC1 +,PC2 +,PC3 +,PC4 +,PC5 +,PC6 +,PC7 +,PC8 +,PC9 +,PC10 +,PC11 +,PC12 +P11,PC13 +,PC14 +,PC15 +,PD0 +,PD1 +,PD2 +,PD3 +,PD4 +,PD5 +P10,PD6 +SPI2_MOSI,PD7 +P0,PD7 +,PD8 +,PD9 +,PD10 +SPI2_MISO,PD11 +P1,PD11 +,PD12 +P8,PD13 +,PD14 +,PD15 +,PE0 +,PE1 +,PE2 +,PE3 +,PE4 +,PE5 +,PE6 +UART7_RX,PE7 +UART7_TX,PE8 +,PE9 +,PE10 +SPI4_CS,PE11 +SPI4_SCK,PE12 +I2C4_SCL,PE13 +I2C4_SDA,PE14 +,PE15 +P6,PG0 +P9,PG12 +P7,PG13 +,PG15 + +BUTTON,PF4 +LED_RED,PG10 +LED_GREEN,PA7 +LED_BLUE,PB1 + +-XSPIM_P2_DQS,PN0 +-XSPIM_P2_CS,PN1 +-XSPIM_P2_IO0,PN2 +-XSPIM_P2_IO1,PN3 +-XSPIM_P2_IO2,PN4 +-XSPIM_P2_IO3,PN5 +-XSPIM_P2_SCK,PN6 +-XSPIM_P2_NCLK,PN7 +-XSPIM_P2_IO4,PN8 +-XSPIM_P2_IO5,PN9 +-XSPIM_P2_IO6,PN10 +-XSPIM_P2_IO7,PN11 +-FLASH_RESET,PN12 + +-WL_REG_ON,PB12 +-WL_HOST_WAKE,PB14 +-WL_SDIO_D0,PB8 +-WL_SDIO_D1,PG8 +-WL_SDIO_D2,PB9 +-WL_SDIO_D3,PB4 +-WL_SDIO_CMD,PA0 +-WL_SDIO_CK,PD2 +-WL_I2S_SDO,PG14 +-WL_I2S_WS,PB15 +-WL_I2S_SCLK,PB13 +-BT_RXD,PF6 +-BT_TXD,PD5 +-BT_CTS,PG5 +-BT_RTS,PF3 +-BT_REG_ON,PD10 +-BT_HOST_WAKE,PD14 +-BT_DEV_WAKE,PD15 + +-SD_SDIO_D0,PC8 +-SD_SDIO_D1,PC9 +-SD_SDIO_D2,PC10 +-SD_SDIO_D3,PC11 +-SD_SDIO_CK,PC12 +-SD_SDIO_CMD,PH2 +-SD_RESET,PC7 +-SD_DETECT,PC6 +-SD_VSELECT,PG6 diff --git a/ports/stm32/boards/OPENMV_N6/stm32n6xx_hal_conf.h b/ports/stm32/boards/OPENMV_N6/stm32n6xx_hal_conf.h new file mode 100644 index 000000000..4012d56e5 --- /dev/null +++ b/ports/stm32/boards/OPENMV_N6/stm32n6xx_hal_conf.h @@ -0,0 +1,18 @@ +/* This file is part of the MicroPython project, http://micropython.org/ + * The MIT License (MIT) + * Copyright (c) 2019 Damien P. George + */ +#ifndef MICROPY_INCLUDED_STM32N6XX_HAL_CONF_H +#define MICROPY_INCLUDED_STM32N6XX_HAL_CONF_H + +// Oscillator values in Hz +#define HSE_VALUE (48000000) +#define LSE_VALUE (32768) + +// Oscillator timeouts in ms +#define HSE_STARTUP_TIMEOUT (100) +#define LSE_STARTUP_TIMEOUT (5000) + +#include "boards/stm32n6xx_hal_conf_base.h" + +#endif // MICROPY_INCLUDED_STM32N6XX_HAL_CONF_H |