diff options
| -rw-r--r-- | ports/stm32/Makefile | 1 | ||||
| -rw-r--r-- | ports/stm32/boards/stm32h7xx_hal_conf_base.h | 1 | ||||
| -rw-r--r-- | ports/stm32/uart.c | 63 |
3 files changed, 38 insertions, 27 deletions
diff --git a/ports/stm32/Makefile b/ports/stm32/Makefile index 475d8f100..58dc76200 100644 --- a/ports/stm32/Makefile +++ b/ports/stm32/Makefile @@ -404,6 +404,7 @@ HAL_SRC_C += $(addprefix $(STM32LIB_HAL_BASE)/Src/stm32$(MCU_SERIES)xx_,\ hal_tim.c \ hal_tim_ex.c \ hal_uart.c \ + ll_rcc.c \ ll_utils.c \ ) diff --git a/ports/stm32/boards/stm32h7xx_hal_conf_base.h b/ports/stm32/boards/stm32h7xx_hal_conf_base.h index 7882adf15..670dee383 100644 --- a/ports/stm32/boards/stm32h7xx_hal_conf_base.h +++ b/ports/stm32/boards/stm32h7xx_hal_conf_base.h @@ -95,6 +95,7 @@ #include "stm32h7xx_ll_adc.h" #include "stm32h7xx_ll_lpuart.h" #include "stm32h7xx_ll_pwr.h" +#include "stm32h7xx_ll_rcc.h" #include "stm32h7xx_ll_rtc.h" #include "stm32h7xx_ll_usart.h" diff --git a/ports/stm32/uart.c b/ports/stm32/uart.c index 1823596df..908361874 100644 --- a/ports/stm32/uart.c +++ b/ports/stm32/uart.c @@ -837,48 +837,57 @@ uint32_t uart_get_source_freq(pyb_uart_obj_t *self) { uart_clk = LSE_VALUE; break; } - #elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) + + #elif defined(STM32H5) || defined(STM32H7) + uint32_t csel; + unsigned int bus_pclk; + + #if defined(STM32H5) + if (1 <= self->uart_id && self->uart_id <= 10) { + csel = RCC->CCIPR1 >> ((self->uart_id - 1) * 3); + } else { + csel = RCC->CCIPR2 >> ((self->uart_id - 11) * 3); + } + bus_pclk = self->uart_id == 1 ? 2 : 1; + #elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) if (self->uart_id == 1 || self->uart_id == 6 || self->uart_id == 9 || self->uart_id == 10) { csel = RCC->CDCCIP2R >> 3; + bus_pclk = 2; } else { csel = RCC->CDCCIP2R; + bus_pclk = 1; } - switch (csel & 3) { - case 0: - if (self->uart_id == 1 || self->uart_id == 6 || self->uart_id == 9 || self->uart_id == 10) { - uart_clk = HAL_RCC_GetPCLK2Freq(); - } else { - uart_clk = HAL_RCC_GetPCLK1Freq(); - } - break; - case 3: - uart_clk = HSI_VALUE; - break; - case 4: - uart_clk = CSI_VALUE; - break; - case 5: - uart_clk = LSE_VALUE; - break; - default: - break; - } - #elif defined(STM32H7) - uint32_t csel; + #else if (self->uart_id == 1 || self->uart_id == 6) { csel = RCC->D2CCIP2R >> 3; + bus_pclk = 2; } else { csel = RCC->D2CCIP2R; + bus_pclk = 1; } - switch (csel & 3) { + #endif + + switch (csel & 7) { case 0: - if (self->uart_id == 1 || self->uart_id == 6) { - uart_clk = HAL_RCC_GetPCLK2Freq(); - } else { + if (bus_pclk == 1) { uart_clk = HAL_RCC_GetPCLK1Freq(); + } else { + uart_clk = HAL_RCC_GetPCLK2Freq(); } break; + case 1: { + LL_PLL_ClocksTypeDef PLL_Clocks; + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + uart_clk = PLL_Clocks.PLL_Q_Frequency; + break; + } + case 2: { + LL_PLL_ClocksTypeDef PLL_Clocks; + LL_RCC_GetPLL3ClockFreq(&PLL_Clocks); + uart_clk = PLL_Clocks.PLL_Q_Frequency; + break; + } case 3: uart_clk = HSI_VALUE; break; |