diff options
| -rw-r--r-- | ports/stm32/boards/stm32l072_af.csv | 84 | ||||
| -rw-r--r-- | ports/stm32/boards/stm32l072xz.ld | 27 | ||||
| -rw-r--r-- | ports/stm32/boards/stm32l0xx_hal_conf_base.h | 91 |
3 files changed, 202 insertions, 0 deletions
diff --git a/ports/stm32/boards/stm32l072_af.csv b/ports/stm32/boards/stm32l072_af.csv new file mode 100644 index 000000000..0b1115b16 --- /dev/null +++ b/ports/stm32/boards/stm32l072_af.csv @@ -0,0 +1,84 @@ +Port,Pin,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,, +,,SPI1/SPI2/I2S2/USART1/2/LPUART1/USB/LPTIM1/TSC/TIM2/21/22/EVENTOUT/SYS_AF,SPI1/SPI2/I2S2/I2C1/TIM2/21,SPI1/SPI2/I2S2/LPUART1/USART5/USB/LPTIM1/TIM2/3/EVENTOUT/SYS_AF,I2C1/TSC/EVENTOUT,I2C1/USART1/2/LPUART1/TIM3/22/EVENTOUT,SPI2/I2S2/I2C2/USART1/TIM2/21/22,I2C1/2/LPUART1/USART4/UASRT5/TIM21/EVENTOUT,I2C3/LPUART1/COMP1/2/TIM3,,ADC +PortA,PA0,,,TIM2_CH1,TSC_G1_IO1,USART2_CTS,TIM2_ETR,USART4_TX,COMP1_OUT,,ADC_IN0 +PortA,PA1,EVENTOUT,,TIM2_CH2,TSC_G1_IO2,USART2_RTS_DE,TIM21_ETR,USART4_RX,,,ADC_IN1 +PortA,PA2,TIM21_CH1,,TIM2_CH3,TSC_G1_IO3,USART2_TX,,LPUART1_TX,COMP2_OUT,,ADC_IN2 +PortA,PA3,TIM21_CH2,,TIM2_CH4,TSC_G1_IO4,USART2_RX,,LPUART1_RX,,,ADC_IN3 +PortA,PA4,SPI1_NSS,,,TSC_G2_IO1,USART2_CK,TIM22_ETR,,,,ADC_IN4 +PortA,PA5,SPI1_SCK,,TIM2_ETR,TSC_G2_IO2,,TIM2_CH1,,,,ADC_IN5 +PortA,PA6,SPI1_MISO,,TIM3_CH1,TSC_G2_IO3,LPUART1_CTS,TIM22_CH1,EVENTOUT,COMP1_OUT,,ADC_IN6 +PortA,PA7,SPI1_MOSI,,TIM3_CH2,TSC_G2_IO4,,TIM22_CH2,EVENTOUT,COMP2_OUT,,ADC_IN7 +PortA,PA8,MCO,,USB_CRS_SYNC,EVENTOUT,USART1_CK,,,I2C3_SCL,, +PortA,PA9,MCO,,,TSC_G4_IO1,USART1_TX,,I2C1_SCL,I2C3_SMBA,, +PortA,PA10,,,,TSC_G4_IO2,USART1_RX,,I2C1_SDA,,, +PortA,PA11,SPI1_MISO,,EVENTOUT,TSC_G4_IO3,USART1_CTS,,,COMP1_OUT,, +PortA,PA12,SPI1_MOSI,,EVENTOUT,TSC_G4_IO4,USART1_RTS_DE,,,COMP2_OUT,, +PortA,PA13,SWDIO,,USB_NOE,,,,LPUART1_RX,,, +PortA,PA14,SWCLK,,,,USART2_TX,,LPUART1_TX,,, +PortA,PA15,SPI1_NSS,,TIM2_ETR,EVENTOUT,USART2_RX,TIM2_CH1,USART4_RTS_DE,,, +PortB,PB0,EVENTOUT,,TIM3_CH3,TSC_G3_IO2,,,,,,ADC_IN8 +PortB,PB1,,,TIM3_CH4,TSC_G3_IO3,LPUART1_RTS_DE,,,,,ADC_IN9 +PortB,PB2,,,LPTIM1_OUT,TSC_G3_IO4,,,,I2C3_SMBA,, +PortB,PB3,SPI1_SCK,,TIM2_CH2,TSC_G5_IO1,EVENTOUT,USART1_RTS_DE,USART5_TX,,, +PortB,PB4,SPI1_MISO,,TIM3_CH1,TSC_G5_IO2,TIM22_CH1,USART1_CTS,USART5_RX,I2C3_SDA,, +PortB,PB5,SPI1_MOSI,,LPTIM1_IN1,I2C1_SMBA,TIM3_CH2/TIM22_CH2,USART1_CK,USART5_CK/USART5_RTS_DE,,, +PortB,PB6,USART1_TX,I2C1_SCL,LPTIM1_ETR,TSC_G5_IO3,,,,,, +PortB,PB7,USART1_RX,I2C1_SDA,LPTIM1_IN2,TSC_G5_IO4,,,USART4_CTS,,, +PortB,PB8,,,,TSC_SYNC,I2C1_SCL,,,,, +PortB,PB9,,,EVENTOUT,,I2C1_SDA,SPI2_NSS/I2S2_WS,,,, +PortB,PB10,,,TIM2_CH3,TSC_SYNC,LPUART1_TX,SPI2_SCK,I2C2_SCL,LPUART1_RX,, +PortB,PB11,EVENTOUT,,TIM2_CH4,TSC_G6_IO1,LPUART1_RX,,I2C2_SDA,LPUART1_TX,, +PortB,PB12,SPI2_NSS/I2S2_WS,,LPUART1_RTS_DE,TSC_G6_IO2,I2C2_SMBA,,EVENTOUT,,, +PortB,PB13,SPI2_SCK/I2S2_CK,,MCO,TSC_G6_IO3,LPUART1_CTS,I2C2_SCL,TIM21_CH1,,, +PortB,PB14,SPI2_MISO/I2S2_MCK,,RTC_OUT,TSC_G6_IO4,LPUART1_RTS_DE,I2C2_SDA,TIM21_CH2,,, +PortB,PB15,SPI2_MOSI/I2S2_SD,,RTC_REFIN,,,,,,, +PortC,PC0,LPTIM1_IN1,,EVENTOUT,TSC_G7_IO1,,,LPUART1_RX,I2C3_SCL,,ADC_IN10 +PortC,PC1,LPTIM1_OUT,,EVENTOUT,TSC_G7_IO2,,,LPUART1_TX,I2C3_SDA,,ADC_IN11 +PortC,PC2,LPTIM1_IN2,,SPI2_MISO/I2S2_MCK,TSC_G7_IO3,,,,,,ADC_IN12 +PortC,PC3,LPTIM1_ETR,,SPI2_MOSI/I2S2_SD,TSC_G7_IO4,,,,,,ADC_IN13 +PortC,PC4,EVENTOUT,,LPUART1_TX,,,,,,,ADC_IN14 +PortC,PC5,LPUART1_RX,,TSC_G3_IO1,,,,,,,ADC_IN15 +PortC,PC6,TIM22_CH1,,TIM3_CH1,TSC_G8_IO1,,,,,, +PortC,PC7,TIM22_CH2,,TIM3_CH2,TSC_G8_IO2,,,,,, +PortC,PC8,TIM22_ETR,,TIM3_CH3,TSC_G8_IO3,,,,,, +PortC,PC9,TIM21_ETR,,USB_NOE/TIM3_CH4,TSC_G8_IO4,,,,I2C3_SDA,, +PortC,PC10,LPUART1_TX,,,,,,USART4_TX,,, +PortC,PC11,LPUART1_RX,,,,,,USART4_RX,,, +PortC,PC12,,,USART5_TX,,,,USART4_CK,,, +PortC,PC13,,,,,,,,,, +PortC,PC14,,,,,,,,,, +PortC,PC15,,,,,,,,,, +PortD,PD0,TIM21_CH1,SPI2_NSS/I2S2_WS,,,,,,,, +PortD,PD1,,SPI2_SCK/I2S2_CK,,,,,,,, +PortD,PD2,LPUART1_RTS_DE,,TIM3_ETR,,,,USART5_RX,,, +PortD,PD3,USART2_CTS,,SPI2_MISO/I2S2_MCK,,,,,,, +PortD,PD4,USART2_RTS_DE,SPI2_MOSI/I2S2_SD,,,,,,,, +PortD,PD5,USART2_TX,,,,,,,,, +PortD,PD6,USART2_RX,,,,,,,,, +PortD,PD7,USART2_CK,TIM21_CH2,,,,,,,, +PortD,PD8,LPUART1_TX,,,,,,,,, +PortD,PD9,LPUART1_RX,,,,,,,,, +PortD,PD10,,,,,,,,,, +PortD,PD11,LPUART1_CTS,,,,,,,,, +PortD,PD12,LPUART1_RTS_DE,,,,,,,,, +PortD,PD13,,,,,,,,,, +PortD,PD14,,,,,,,,,, +PortD,PD15,USB_CRS_SYNC,,,,,,,,, +PortE,PE0,,,EVENTOUT,,,,,,, +PortE,PE1,,,EVENTOUT,,,,,,, +PortE,PE2,,,TIM3_ETR,,,,,,, +PortE,PE3,TIM22_CH1,,TIM3_CH1,,,,,,, +PortE,PE4,TIM22_CH2,,TIM3_CH2,,,,,,, +PortE,PE5,TIM21_CH1,,TIM3_CH3,,,,,,, +PortE,PE6,TIM21_CH2,,TIM3_CH4,,,,,,, +PortE,PE7,,,,,,,USART5_CK/USART5_RTS_DE,,, +PortE,PE8,,,,,,,USART4_TX,,, +PortE,PE9,TIM2_CH1,,TIM2_ETR,,,,USART4_RX,,, +PortE,PE10,TIM2_CH2,,,,,,USART5_TX,,, +PortE,PE11,TIM2_CH3,,,,,,USART5_RX,,, +PortE,PE12,TIM2_CH4,,SPI1_NSS,,,,,,, +PortE,PE13,,,SPI1_SCK,,,,,,, +PortE,PE14,,,SPI1_MISO,,,,,,, +PortE,PE15,,,SPI1_MOSI,,,,,,, +PortH,PH0,USB_CRS_SYNC,,,,,,,,, +PortH,PH1,,,,,,,,,, diff --git a/ports/stm32/boards/stm32l072xz.ld b/ports/stm32/boards/stm32l072xz.ld new file mode 100644 index 000000000..538950747 --- /dev/null +++ b/ports/stm32/boards/stm32l072xz.ld @@ -0,0 +1,27 @@ +/* + GNU linker script for STM32F072xZ +*/ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 192K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 2K; +_minimum_heap_size = 8K; + +_ram_start = ORIGIN(RAM); +_ram_end = ORIGIN(RAM) + LENGTH(RAM); + +/* Define the top end of the stack. The stack is full descending so begins just + above last byte of RAM. Note that EABI requires the stack to be 8-byte + aligned for a call. */ +_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve; +_sstack = _estack - 4K; + +/* RAM extents for the main heap */ +_heap_start = _ebss; +_heap_end = _sstack; diff --git a/ports/stm32/boards/stm32l0xx_hal_conf_base.h b/ports/stm32/boards/stm32l0xx_hal_conf_base.h new file mode 100644 index 000000000..ed524fecc --- /dev/null +++ b/ports/stm32/boards/stm32l0xx_hal_conf_base.h @@ -0,0 +1,91 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef MICROPY_INCLUDED_STM32L0XX_HAL_CONF_BASE_H +#define MICROPY_INCLUDED_STM32L0XX_HAL_CONF_BASE_H + +// Include various HAL modules for convenience +#include "stm32l0xx_hal_dma.h" +#include "stm32l0xx_hal_adc.h" +#include "stm32l0xx_hal_cortex.h" +#include "stm32l0xx_hal_crc.h" +#include "stm32l0xx_hal_dac.h" +#include "stm32l0xx_hal_flash.h" +#include "stm32l0xx_hal_gpio.h" +#include "stm32l0xx_hal_i2c.h" +#include "stm32l0xx_hal_i2s.h" +#include "stm32l0xx_hal_iwdg.h" +#include "stm32l0xx_hal_pcd.h" +#include "stm32l0xx_hal_pwr.h" +#include "stm32l0xx_hal_rcc.h" +#include "stm32l0xx_hal_rtc.h" +#include "stm32l0xx_hal_spi.h" +#include "stm32l0xx_hal_tim.h" +#include "stm32l0xx_hal_uart.h" +#include "stm32l0xx_hal_usart.h" +#include "stm32l0xx_hal_wwdg.h" + +// Enable various HAL modules +#define HAL_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_CRC_MODULE_ENABLED +#define HAL_DAC_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_I2S_MODULE_ENABLED +#define HAL_IWDG_MODULE_ENABLED +#define HAL_PCD_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +#define HAL_USART_MODULE_ENABLED +#define HAL_WWDG_MODULE_ENABLED + +// Oscillator values in Hz +#define HSI_VALUE (16000000) +#define HSI48_VALUE (48000000) +#define LSI_VALUE (37000) +#define MSI_VALUE (2097152) + +// SysTick has the highest priority +#define TICK_INT_PRIORITY (0x00) + +// Miscellaneous HAL settings +#define PREFETCH_ENABLE 1 +#define PREREAD_ENABLE 0 +#define BUFFER_CACHE_DISABLE 0 +#define USE_RTOS 0 +#define USE_SPI_CRC 0 + +// HAL parameter assertions are disabled +#define assert_param(expr) ((void)0) + +#endif // MICROPY_INCLUDED_STM32L0XX_HAL_CONF_BASE_H |