diff options
| -rw-r--r-- | ports/stm32/Makefile | 4 | ||||
| -rw-r--r-- | ports/stm32/adc.c | 11 | ||||
| -rw-r--r-- | ports/stm32/adc.h | 2 | ||||
| -rw-r--r-- | ports/stm32/boards/STM32H7B3I_DK/mpconfigboard.h | 86 | ||||
| -rw-r--r-- | ports/stm32/boards/STM32H7B3I_DK/mpconfigboard.mk | 18 | ||||
| -rw-r--r-- | ports/stm32/boards/STM32H7B3I_DK/pins.csv | 191 | ||||
| -rw-r--r-- | ports/stm32/boards/STM32H7B3I_DK/stm32h7xx_hal_conf.h | 19 | ||||
| -rw-r--r-- | ports/stm32/boards/stm32h7b3.ld | 30 | ||||
| -rw-r--r-- | ports/stm32/boards/stm32h7b3_af.csv | 175 | ||||
| -rw-r--r-- | ports/stm32/extint.c | 4 | ||||
| -rw-r--r-- | ports/stm32/flash.c | 4 | ||||
| -rw-r--r-- | ports/stm32/machine_adc.c | 9 | ||||
| -rw-r--r-- | ports/stm32/main.c | 3 | ||||
| -rw-r--r-- | ports/stm32/mpconfigboard_common.h | 11 | ||||
| -rw-r--r-- | ports/stm32/powerctrl.c | 24 | ||||
| -rw-r--r-- | ports/stm32/rtc.c | 17 | ||||
| -rw-r--r-- | ports/stm32/stm32_it.c | 4 | ||||
| -rw-r--r-- | ports/stm32/system_stm32.c | 6 | ||||
| -rw-r--r-- | ports/stm32/timer.c | 5 | ||||
| -rw-r--r-- | ports/stm32/uart.c | 27 | ||||
| -rw-r--r-- | ports/stm32/usbd_conf.c | 17 |
21 files changed, 655 insertions, 12 deletions
diff --git a/ports/stm32/Makefile b/ports/stm32/Makefile index 1614db235..7a869d3c0 100644 --- a/ports/stm32/Makefile +++ b/ports/stm32/Makefile @@ -77,7 +77,7 @@ CFLAGS_CORTEX_M = -mthumb # Select hardware floating-point support SUPPORTS_HARDWARE_FP_SINGLE = 0 SUPPORTS_HARDWARE_FP_DOUBLE = 0 -ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),STM32F765xx STM32F767xx STM32F769xx STM32H743xx STM32H750xx)) +ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),STM32F765xx STM32F767xx STM32F769xx STM32H743xx STM32H750xx STM32H7A3xx STM32H7A3xxQ STM32H7B3xx STM32H7B3xxQ)) CFLAGS_CORTEX_M += -mfpu=fpv5-d16 -mfloat-abi=hard SUPPORTS_HARDWARE_FP_SINGLE = 1 SUPPORTS_HARDWARE_FP_DOUBLE = 1 @@ -424,7 +424,7 @@ HAL_SRC_C += $(addprefix $(HAL_DIR)/Src/stm32$(MCU_SERIES)xx_,\ ) endif -ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),STM32H743xx STM32H750xx)) +ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),STM32H743xx STM32H750xx STM32H7A3xx STM32H7A3xxQ STM32H7B3xx STM32H7B3xxQ)) HAL_SRC_C += $(addprefix $(HAL_DIR)/Src/stm32$(MCU_SERIES)xx_, hal_fdcan.c) else ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),f0 f4 f7 h7 l4)) diff --git a/ports/stm32/adc.c b/ports/stm32/adc.c index dd2702d6f..ceb6584d0 100644 --- a/ports/stm32/adc.c +++ b/ports/stm32/adc.c @@ -55,7 +55,11 @@ #define PIN_ADC_MASK PIN_ADC1 #define pin_adc_table pin_adc1 -#if defined(STM32H7) +#if defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || \ + defined(STM32H7B3xx) || defined(STM32H7B3xxQ) +#define ADCALLx (ADC2) +#define pin_adcall_table pin_adc2 +#elif defined(STM32H7) // On the H7 ADC3 is used for ADCAll to be able to read internal // channels. For all other GPIO channels, ADC12 is used instead. #define ADCALLx (ADC3) @@ -137,6 +141,8 @@ defined(STM32F767xx) || defined(STM32F769xx) #define VBAT_DIV (4) #elif defined(STM32H743xx) || defined(STM32H747xx) || \ + defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || \ + defined(STM32H7B3xx) || defined(STM32H7B3xxQ) || \ defined(STM32H750xx) #define VBAT_DIV (4) #elif defined(STM32L432xx) || \ @@ -227,6 +233,9 @@ STATIC void adc_wait_for_eoc_or_timeout(ADC_HandleTypeDef *adcHandle, int32_t ti STATIC void adcx_clock_enable(ADC_HandleTypeDef *adch) { #if defined(STM32F0) || defined(STM32F4) || defined(STM32F7) ADCx_CLK_ENABLE(); + #elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) + __HAL_RCC_ADC12_CLK_ENABLE(); + __HAL_RCC_ADC_CONFIG(RCC_ADCCLKSOURCE_CLKP); #elif defined(STM32H7) if (adch->Instance == ADC3) { __HAL_RCC_ADC3_CLK_ENABLE(); diff --git a/ports/stm32/adc.h b/ports/stm32/adc.h index 64864b196..5821eb9d6 100644 --- a/ports/stm32/adc.h +++ b/ports/stm32/adc.h @@ -48,6 +48,8 @@ static inline void adc_deselect_vbat(ADC_TypeDef *adc, uint32_t channel) { adc_common = ADC_COMMON_REGISTER(0); #elif defined(STM32F7) adc_common = ADC123_COMMON; + #elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) + adc_common = ADC12_COMMON; #elif defined(STM32H7) adc_common = adc == ADC3 ? ADC3_COMMON : ADC12_COMMON; #endif diff --git a/ports/stm32/boards/STM32H7B3I_DK/mpconfigboard.h b/ports/stm32/boards/STM32H7B3I_DK/mpconfigboard.h new file mode 100644 index 000000000..02f5fcac2 --- /dev/null +++ b/ports/stm32/boards/STM32H7B3I_DK/mpconfigboard.h @@ -0,0 +1,86 @@ +#define MICROPY_HW_BOARD_NAME "STM32H7B3I-DK" +#define MICROPY_HW_MCU_NAME "STM32H7B3LIH6Q" + +#define MICROPY_HW_ENABLE_RTC (1) +#define MICROPY_HW_ENABLE_RNG (1) +#define MICROPY_HW_ENABLE_ADC (1) +#define MICROPY_HW_ENABLE_DAC (1) +#define MICROPY_HW_ENABLE_USB (1) +#define MICROPY_HW_ENABLE_SDCARD (1) +#define MICROPY_HW_HAS_SWITCH (1) +#define MICROPY_HW_HAS_FLASH (0) + +#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (0) + +// The board has a 24MHz HSE, the following gives 280MHz CPU speed +#define MICROPY_HW_CLK_PLLM (12) +#define MICROPY_HW_CLK_PLLN (280) +#define MICROPY_HW_CLK_PLLP (2) +#define MICROPY_HW_CLK_PLLQ (2) +#define MICROPY_HW_CLK_PLLR (2) + +// The USB clock is set using PLL3 (48Mhz usb clock) +#define MICROPY_HW_CLK_PLL3M (12) +#define MICROPY_HW_CLK_PLL3N (192) +#define MICROPY_HW_CLK_PLL3P (17) +#define MICROPY_HW_CLK_PLL3Q (8) +#define MICROPY_HW_CLK_PLL3R (2) + +// 6 wait states when running at 280MHz (VOS0 range) +#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_6 + +#if 0 +// 512MBit external OSPI flash, used for either the filesystem or XIP memory mapped +#define MICROPY_HW_OSPIFLASH_SIZE_BITS_LOG2 (29) +#define MICROPY_HW_OSPIFLASH_CS (pin_G6) +#define MICROPY_HW_OSPIFLASH_CLK (pin_B2) +#define MICROPY_HW_OSPIFLASH_DQS (pin_C5) +#define MICROPY_HW_OSPIFLASH_IO0 (pin_P8) +#define MICROPY_HW_OSPIFLASH_IO1 (pin_F9) +#define MICROPY_HW_OSPIFLASH_IO2 (pin_F7) +#define MICROPY_HW_OSPIFLASH_IO3 (pin_F6) +#define MICROPY_HW_OSPIFLASH_IO4 (pin_C1) +#define MICROPY_HW_OSPIFLASH_IO5 (pin_H3) +#define MICROPY_HW_OSPIFLASH_IO6 (pin_D6) +#define MICROPY_HW_OSPIFLASH_IO7 (pin_G14) +#endif + +// UART buses +#define MICROPY_HW_UART1_TX (pin_A9) +#define MICROPY_HW_UART1_RX (pin_A10) +#define MICROPY_HW_UART4_TX (pin_H13) // Arduino Connector CN11-Pin1 +#define MICROPY_HW_UART4_RX (pin_H14) // Arduino Connector CN11-Pin2 +#define MICROPY_HW_UART_REPL PYB_UART_1 +#define MICROPY_HW_UART_REPL_BAUD 115200 + +// USRSW is pulled low. Pressing the button makes the input go high. +#define MICROPY_HW_USRSW_PIN (pin_C13) +#define MICROPY_HW_USRSW_PULL (GPIO_NOPULL) +#define MICROPY_HW_USRSW_EXTI_MODE (GPIO_MODE_IT_RISING) +#define MICROPY_HW_USRSW_PRESSED (1) + +// LEDs +#define MICROPY_HW_LED1 (pin_G11) // red +#define MICROPY_HW_LED2 (pin_G2) // blue +#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_low(pin)) +#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_high(pin)) + +// USB config +#define MICROPY_HW_USB_FS (0) +#define MICROPY_HW_USB_HS (1) +#define MICROPY_HW_USB_HS_IN_FS (1) +#define MICROPY_HW_USB_MAIN_DEV (USB_PHY_HS_ID) +#define MICROPY_HW_USB_CDC_NUM (2) +#define MICROPY_HW_USB_MSC (0) + +// SD card detect switch +#define MICROPY_HW_SDCARD_DETECT_PIN (pin_I8) +#define MICROPY_HW_SDCARD_DETECT_PULL (GPIO_PULLUP) +#define MICROPY_HW_SDCARD_DETECT_PRESENT (GPIO_PIN_RESET) + +#define MICROPY_HW_SDMMC_D0 (pin_C8) +#define MICROPY_HW_SDMMC_D1 (pin_C9) +#define MICROPY_HW_SDMMC_D2 (pin_C10) +#define MICROPY_HW_SDMMC_D3 (pin_C11) +#define MICROPY_HW_SDMMC_CK (pin_C12) +#define MICROPY_HW_SDMMC_CMD (pin_D2) diff --git a/ports/stm32/boards/STM32H7B3I_DK/mpconfigboard.mk b/ports/stm32/boards/STM32H7B3I_DK/mpconfigboard.mk new file mode 100644 index 000000000..380ade8d0 --- /dev/null +++ b/ports/stm32/boards/STM32H7B3I_DK/mpconfigboard.mk @@ -0,0 +1,18 @@ +USE_MBOOT ?= 0 + +# MCU settings +MCU_SERIES = h7 +CMSIS_MCU = STM32H7B3xxQ +MICROPY_FLOAT_IMPL = double +AF_FILE = boards/stm32h7b3_af.csv + +ifeq ($(USE_MBOOT),1) +# When using Mboot all the text goes together after the filesystem +LD_FILES = boards/stm32h743.ld boards/common_blifs.ld +TEXT0_ADDR = 0x08040000 +else +# When not using Mboot the ISR text goes first, then the rest after the filesystem +LD_FILES = boards/stm32h7b3.ld boards/common_ifs.ld +TEXT0_ADDR = 0x08000000 +TEXT1_ADDR = 0x08040000 +endif diff --git a/ports/stm32/boards/STM32H7B3I_DK/pins.csv b/ports/stm32/boards/STM32H7B3I_DK/pins.csv new file mode 100644 index 000000000..e005e38af --- /dev/null +++ b/ports/stm32/boards/STM32H7B3I_DK/pins.csv @@ -0,0 +1,191 @@ +,PA0 +,PA1 +,PA2 +,PA3 +,PA4 +,PA5 +,PA6 +,PA7 +,PA8 +,PA9 +,PA10 +,PA11 +,PA12 +,PA13 +,PA14 +,PA15 +,PB0 +,PB1 +,PB2 +,PB3 +,PB4 +,PB5 +,PB6 +,PB7 +,PB8 +,PB9 +,PB10 +,PB11 +,PB12 +,PB13 +,PB14 +,PB15 +,PC0 +,PC1 +,PC2 +,PC3 +,PC4 +,PC5 +,PC6 +,PC7 +,PC8 +,PC9 +,PC10 +,PC11 +,PC12 +,PC13 +,PC14 +,PC15 +,PD0 +,PD1 +,PD2 +,PD3 +,PD4 +,PD5 +,PD6 +,PD7 +,PD8 +,PD9 +,PD10 +,PD11 +,PD12 +,PD13 +,PD14 +,PD15 +,PE0 +,PE1 +,PE2 +,PE3 +,PE4 +,PE5 +,PE6 +,PE7 +,PE8 +,PE9 +,PE10 +,PE11 +,PE12 +,PE13 +,PE14 +,PE15 +,PF0 +,PF1 +,PF2 +,PF3 +,PF4 +,PF5 +,PF6 +,PF7 +,PF8 +,PF9 +,PF10 +,PF11 +,PF12 +,PF13 +,PF14 +,PF15 +,PG0 +,PG1 +,PG2 +,PG3 +,PG4 +,PG5 +,PG6 +,PG7 +,PG8 +,PG9 +,PG10 +,PG11 +,PG12 +,PG13 +,PG14 +,PG15 +,PH0 +,PH1 +,PH2 +,PH3 +,PH4 +,PH5 +,PH6 +,PH7 +,PH8 +,PH9 +,PH10 +,PH11 +,PH12 +,PH13 +,PH14 +,PH15 +,PI0 +,PI1 +,PI2 +,PI3 +,PI4 +,PI5 +,PI6 +,PI7 +,PI8 +,PI9 +,PI10 +,PI11 +,PI12 +,PI13 +,PI14 +,PI15 +DAC1,PA4 +DAC2,PA5 +LED1,G11 +LED2,G2 +SW,PC13 +I2C1_SDA,PB9 +I2C1_SCL,PB8 +I2C2_SDA,PF0 +I2C2_SCL,PF1 +I2C4_SCL,PF14 +I2C4_SDA,PF15 +SD_D0,PC8 +SD_D1,PC9 +SD_D2,PC10 +SD_D3,PC11 +SD_CMD,PD2 +SD_CK,PC12 +SD_SW,PG2 +OTG_FS_POWER,PG6 +OTG_FS_OVER_CURRENT,PG7 +USB_VBUS,PA9 +USB_ID,PA10 +USB_DM,PA11 +USB_DP,PA12 +UART2_TX,PD5 +UART2_RX,PD6 +UART2_RTS,PD4 +UART2_CTS,PD3 +UART3_TX,PD8 +UART3_RX,PD9 +UART5_TX,PB6 +UART5_RX,PB12 +UART6_TX,PC6 +UART6_RX,PC7 +UART7_TX,PF7 +UART7_RX,PF6 +UART8_TX,PE1 +UART8_RX,PE0 +ETH_MDC,PC1 +ETH_MDIO,PA2 +ETH_RMII_REF_CLK,PA1 +ETH_RMII_CRS_DV,PA7 +ETH_RMII_RXD0,PC4 +ETH_RMII_RXD1,PC5 +ETH_RMII_TX_EN,PG11 +ETH_RMII_TXD0,PG13 +ETH_RMII_TXD1,PB13 diff --git a/ports/stm32/boards/STM32H7B3I_DK/stm32h7xx_hal_conf.h b/ports/stm32/boards/STM32H7B3I_DK/stm32h7xx_hal_conf.h new file mode 100644 index 000000000..70c3246a8 --- /dev/null +++ b/ports/stm32/boards/STM32H7B3I_DK/stm32h7xx_hal_conf.h @@ -0,0 +1,19 @@ +/* This file is part of the MicroPython project, http://micropython.org/ + * The MIT License (MIT) + * Copyright (c) 2019 Damien P. George + */ +#ifndef MICROPY_INCLUDED_STM32H7XX_HAL_CONF_H +#define MICROPY_INCLUDED_STM32H7XX_HAL_CONF_H + +#include "boards/stm32h7xx_hal_conf_base.h" + +// Oscillator values in Hz +#define HSE_VALUE (24000000) +#define LSE_VALUE (32768) +#define EXTERNAL_CLOCK_VALUE (12288000) + +// Oscillator timeouts in ms +#define HSE_STARTUP_TIMEOUT (5000) +#define LSE_STARTUP_TIMEOUT (5000) + +#endif // MICROPY_INCLUDED_STM32H7XX_HAL_CONF_H diff --git a/ports/stm32/boards/stm32h7b3.ld b/ports/stm32/boards/stm32h7b3.ld new file mode 100644 index 000000000..cccea983f --- /dev/null +++ b/ports/stm32/boards/stm32h7b3.ld @@ -0,0 +1,30 @@ +/* + GNU linker script for STM32H7B3 +*/ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K + FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 128K /* sector 0, 128K */ + FLASH_FS (r) : ORIGIN = 0x08020000, LENGTH = 128K /* sector 1, 128K */ + FLASH_TEXT (rx) : ORIGIN = 0x08040000, LENGTH = 1792K /* sectors 6*128 + 8*128 */ + DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K /* Used for storage cache */ + RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 512K /* AXI SRAM */ + RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 2K; +_minimum_heap_size = 16K; + +/* Define the stack. The stack is full descending so begins just above last byte + of RAM. Note that EABI requires the stack to be 8-byte aligned for a call. */ +_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve; +_sstack = _estack - 16K; /* tunable */ + +/* RAM extents for the garbage collector */ +_ram_start = ORIGIN(RAM); +_ram_end = ORIGIN(RAM) + LENGTH(RAM); +_heap_start = _ebss; /* heap starts just after statically allocated memory */ +_heap_end = _sstack; diff --git a/ports/stm32/boards/stm32h7b3_af.csv b/ports/stm32/boards/stm32h7b3_af.csv new file mode 100644 index 000000000..0e1747161 --- /dev/null +++ b/ports/stm32/boards/stm32h7b3_af.csv @@ -0,0 +1,175 @@ +Port,,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15, +,,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15,ADC +PortA,PA0,,TIM2_CH1/TIM2_ETR,TIM5_CH1,TIM8_ETR,TIM15_BKIN,I2S6_WS/SPI6_NSS,,USART2_CTS/USART2_NSS,UART4_TX,SDMMC2_CMD,SAI2_SD_B,,,,,EVENTOUT/EVENTOUT,ADC1_INP16, +PortA,PA0_C,,TIM2_CH1/TIM2_ETR,TIM5_CH1,TIM8_ETR,TIM15_BKIN,I2S6_WS/SPI6_NSS,,USART2_CTS/USART2_NSS,UART4_TX,SDMMC2_CMD,SAI2_SD_B,,,,,EVENTOUT/EVENTOUT,ADC1_INP16, +PortA,PA1,,TIM2_CH2,TIM5_CH2,LPTIM3_OUT,TIM15_CH1N,,,USART2_DE/USART2_RTS,UART4_RX,OCTOSPIM_P1_IO3,SAI2_MCLK_B,OCTOSPIM_P1_DQS,,,LTDC_R2,EVENTOUT/EVENTOUT,ADC1_INN16/ADC1_INP17, +PortA,PA10,,TIM1_CH3,,LPUART1_RX,,,,USART1_RX,,,USB_OTG_HS_ID,MDIOS_MDIO,LTDC_B4,DCMI_D1/PSSI_D1,LTDC_B1,EVENTOUT/EVENTOUT,, +PortA,PA11,,TIM1_CH4,,LPUART1_CTS,,I2S2_WS/SPI2_NSS,UART4_RX,USART1_CTS/USART1_NSS,,FDCAN1_RX,,,,,LTDC_R4,EVENTOUT/EVENTOUT,, +PortA,PA12,,TIM1_ETR,,LPUART1_DE/LPUART1_RTS,,I2S2_CK/SPI2_SCK,UART4_TX,USART1_DE/USART1_RTS,SAI2_FS_B,FDCAN1_TX,,,,,LTDC_R5,EVENTOUT/EVENTOUT,, +PortA,PA13,DEBUG_JTMS/SWDIO,,,,,,,,,,,,,,,EVENTOUT/EVENTOUT,, +PortA,PA14,DEBUG_JTCK/SWCLK,,,,,,,,,,,,,,,EVENTOUT/EVENTOUT,, +PortA,PA15,DEBUG_JTDI,TIM2_CH1/TIM2_ETR,,,CEC,I2S1_WS/SPI1_NSS,I2S3_WS/SPI3_NSS,I2S6_WS/SPI6_NSS,UART4_DE/UART4_RTS,LTDC_R3,,UART7_TX,,,LTDC_B6,EVENTOUT/EVENTOUT,, +PortA,PA1_C,,TIM2_CH2,TIM5_CH2,LPTIM3_OUT,TIM15_CH1N,,,USART2_DE/USART2_RTS,UART4_RX,OCTOSPIM_P1_IO3,SAI2_MCLK_B,OCTOSPIM_P1_DQS,,,LTDC_R2,EVENTOUT/EVENTOUT,ADC1_INN16/ADC1_INP17, +PortA,PA2,,TIM2_CH3,TIM5_CH3,,TIM15_CH1,,DFSDM2_CKIN1,USART2_TX,SAI2_SCK_B,,,,MDIOS_MDIO,,LTDC_R1,EVENTOUT/EVENTOUT,ADC1_INP14, +PortA,PA3,,TIM2_CH4,TIM5_CH4,OCTOSPIM_P1_CLK,TIM15_CH2,I2S6_MCK,,USART2_RX,,LTDC_B2,USB_OTG_HS_ULPI_D0,,,,LTDC_B5,EVENTOUT/EVENTOUT,ADC1_INP15, +PortA,PA4,,,TIM5_ETR,,,I2S1_WS/SPI1_NSS,I2S3_WS/SPI3_NSS,USART2_CK,I2S6_WS/SPI6_NSS,,,,,DCMI_HSYNC/PSSI_DE,LTDC_VSYNC,EVENTOUT/EVENTOUT,ADC1_INP18, +PortA,PA5,PWR_NDSTOP2,TIM2_CH1/TIM2_ETR,,TIM8_CH1N,,I2S1_CK/SPI1_SCK,,,I2S6_CK/SPI6_SCK,,USB_OTG_HS_ULPI_CK,,,PSSI_D14,LTDC_R4,EVENTOUT/EVENTOUT,ADC1_INN18/ADC1_INP19, +PortA,PA6,,TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,I2S1_SDI/SPI1_MISO,OCTOSPIM_P1_IO3,,I2S6_SDI/SPI6_MISO,TIM13_CH1,TIM8_BKIN_COMP1/TIM8_BKIN_COMP2,MDIOS_MDC,TIM1_BKIN_COMP1/TIM1_BKIN_COMP2,DCMI_PIXCLK/PSSI_PDCK,LTDC_G2,EVENTOUT/EVENTOUT,ADC1_INP3/ADC2_INP3, +PortA,PA7,,TIM1_CH1N,TIM3_CH2,TIM8_CH1N,DFSDM2_DATIN1,I2S1_SDO/SPI1_MOSI,,,I2S6_SDO/SPI6_MOSI,TIM14_CH1,OCTOSPIM_P1_IO2,,FMC_SDNWE,,LTDC_VSYNC,EVENTOUT/EVENTOUT,ADC1_INN3/ADC1_INP7/ADC2_INN3/ADC2_INP7, +PortA,PA8,RCC_MCO_1,TIM1_CH1,,TIM8_BKIN2,I2C3_SCL,,,USART1_CK,,,USB_OTG_HS_SOF,UART7_RX,TIM8_BKIN2_COMP1/TIM8_BKIN2_COMP2,LTDC_B3,LTDC_R6,EVENTOUT/EVENTOUT,, +PortA,PA9,,TIM1_CH2,,LPUART1_TX,I2C3_SMBA,I2S2_CK/SPI2_SCK,,USART1_TX,,,,,,DCMI_D0/PSSI_D0,LTDC_R5,EVENTOUT/EVENTOUT,, +PortB,PB0,,TIM1_CH2N,TIM3_CH3,TIM8_CH2N,DFSDM2_CKOUT,,DFSDM1_CKOUT,,UART4_CTS,LTDC_R3,USB_OTG_HS_ULPI_D1,OCTOSPIM_P1_IO1,,,LTDC_G1,EVENTOUT/EVENTOUT,ADC1_INN5/ADC1_INP9/ADC2_INN5/ADC2_INP9, +PortB,PB1,,TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,DFSDM1_DATIN1,,,LTDC_R6,USB_OTG_HS_ULPI_D2,OCTOSPIM_P1_IO0,,,LTDC_G0,EVENTOUT/EVENTOUT,ADC1_INP5/ADC2_INP5, +PortB,PB10,,TIM2_CH3,,LPTIM2_IN1,I2C2_SCL,I2S2_CK/SPI2_SCK,DFSDM1_DATIN7,USART3_TX,,OCTOSPIM_P1_NCS,USB_OTG_HS_ULPI_D3,,,,LTDC_G4,EVENTOUT/EVENTOUT,, +PortB,PB11,,TIM2_CH4,,LPTIM2_ETR,I2C2_SDA,,DFSDM1_CKIN7,USART3_RX,,,USB_OTG_HS_ULPI_D4,,,,LTDC_G5,EVENTOUT/EVENTOUT,, +PortB,PB12,,TIM1_BKIN,,OCTOSPIM_P1_NCLK,I2C2_SMBA,I2S2_WS/SPI2_NSS,DFSDM1_DATIN1,USART3_CK,,FDCAN2_RX,USB_OTG_HS_ULPI_D5,DFSDM2_DATIN1,,TIM1_BKIN_COMP1/TIM1_BKIN_COMP2,UART5_RX,EVENTOUT/EVENTOUT,, +PortB,PB13,,TIM1_CH1N,,LPTIM2_OUT,DFSDM2_CKIN1,I2S2_CK/SPI2_SCK,DFSDM1_CKIN1,USART3_CTS/USART3_NSS,,FDCAN2_TX,USB_OTG_HS_ULPI_D6,,SDMMC1_D0,DCMI_D2/PSSI_D2,UART5_TX,EVENTOUT/EVENTOUT,, +PortB,PB14,,TIM1_CH2N,TIM12_CH1,TIM8_CH2N,USART1_TX,I2S2_SDI/SPI2_MISO,DFSDM1_DATIN2,USART3_DE/USART3_RTS,UART4_DE/UART4_RTS,SDMMC2_D0,,,,,LTDC_CLK,EVENTOUT/EVENTOUT,, +PortB,PB15,RTC_REFIN,TIM1_CH3N,TIM12_CH2,TIM8_CH3N,USART1_RX,I2S2_SDO/SPI2_MOSI,DFSDM1_CKIN2,,UART4_CTS,SDMMC2_D1,,,,,LTDC_G7,EVENTOUT/EVENTOUT,, +PortB,PB2,RTC_OUT_ALARM,,SAI1_D1,,DFSDM1_CKIN1,,SAI1_SD_A,I2S3_SDO/SPI3_MOSI,,OCTOSPIM_P1_CLK,OCTOSPIM_P1_DQS,,,,,EVENTOUT/EVENTOUT,, +PortB,PB3,DEBUG_JTDO/SWO,TIM2_CH2,,,,I2S1_CK/SPI1_SCK,I2S3_CK/SPI3_SCK,,I2S6_CK/SPI6_SCK,SDMMC2_D2,CRS_SYNC,UART7_RX,,,,EVENTOUT/EVENTOUT,, +PortB,PB4,,TIM16_BKIN,TIM3_CH1,,,I2S1_SDI/SPI1_MISO,I2S3_SDI/SPI3_MISO,I2S2_WS/SPI2_NSS,I2S6_SDI/SPI6_MISO,SDMMC2_D3,,UART7_TX,,,,EVENTOUT/EVENTOUT,, +PortB,PB5,,TIM17_BKIN,TIM3_CH2,,I2C1_SMBA,I2S1_SDO/SPI1_MOSI,I2C4_SMBA,I2S3_SDO/SPI3_MOSI,I2S6_SDO/SPI6_MOSI,FDCAN2_RX,USB_OTG_HS_ULPI_D7,LTDC_B5,FMC_SDCKE1,DCMI_D10/PSSI_D10,UART5_RX,EVENTOUT/EVENTOUT,, +PortB,PB6,,TIM16_CH1N,TIM4_CH1,,I2C1_SCL,CEC,I2C4_SCL,USART1_TX,LPUART1_TX,FDCAN2_TX,OCTOSPIM_P1_NCS,DFSDM1_DATIN5,FMC_SDNE1,DCMI_D5/PSSI_D5,UART5_TX,EVENTOUT/EVENTOUT,, +PortB,PB7,,TIM17_CH1N,TIM4_CH2,,I2C1_SDA,,I2C4_SDA,USART1_RX,LPUART1_RX,,,DFSDM1_CKIN5,FMC_NL,DCMI_VSYNC/PSSI_RDY,,EVENTOUT/EVENTOUT,, +PortB,PB8,,TIM16_CH1,TIM4_CH3,DFSDM1_CKIN7,I2C1_SCL,,I2C4_SCL,SDMMC1_CKIN,UART4_RX,FDCAN1_RX,SDMMC2_D4,,SDMMC1_D4,DCMI_D6/PSSI_D6,LTDC_B6,EVENTOUT/EVENTOUT,, +PortB,PB9,,TIM17_CH1,TIM4_CH4,DFSDM1_DATIN7,I2C1_SDA,I2S2_WS/SPI2_NSS,I2C4_SDA,SDMMC1_CDIR,UART4_TX,FDCAN1_TX,SDMMC2_D5,I2C4_SMBA,SDMMC1_D5,DCMI_D7/PSSI_D7,LTDC_B7,EVENTOUT/EVENTOUT,, +PortC,PC0,,,,DFSDM1_CKIN0,,,DFSDM1_DATIN4,,SAI2_FS_B,FMC_A25,USB_OTG_HS_ULPI_STP,LTDC_G2,FMC_SDNWE,,LTDC_R5,EVENTOUT/EVENTOUT,ADC1_INP10/ADC2_INP10, +PortC,PC1,DEBUG_TRACED0,,SAI1_D1,DFSDM1_DATIN0,DFSDM1_CKIN4,I2S2_SDO/SPI2_MOSI,SAI1_SD_A,,,SDMMC2_CK,OCTOSPIM_P1_IO4,,MDIOS_MDC,,LTDC_G5,EVENTOUT/EVENTOUT,ADC1_INN10/ADC1_INP11/ADC2_INN10/ADC2_INP11, +PortC,PC10,,,,DFSDM1_CKIN5,DFSDM2_CKIN0,,I2S3_CK/SPI3_SCK,USART3_TX,UART4_TX,OCTOSPIM_P1_IO1,LTDC_B1,SWPMI1_RX,SDMMC1_D2,DCMI_D8/PSSI_D8,LTDC_R2,EVENTOUT/EVENTOUT,, +PortC,PC11,,,,DFSDM1_DATIN5,DFSDM2_DATIN0,,I2S3_SDI/SPI3_MISO,USART3_RX,UART4_RX,OCTOSPIM_P1_NCS,,,SDMMC1_D3,DCMI_D4/PSSI_D4,LTDC_B4,EVENTOUT/EVENTOUT,, +PortC,PC12,DEBUG_TRACED3,,TIM15_CH1,,DFSDM2_CKOUT,I2S6_CK/SPI6_SCK,I2S3_SDO/SPI3_MOSI,USART3_CK,UART5_TX,,,,SDMMC1_CK,DCMI_D9/PSSI_D9,LTDC_R6,EVENTOUT/EVENTOUT,, +PortC,PC13,,,,,,,,,,,,,,,,EVENTOUT/EVENTOUT,, +PortC,PC14-OSC32_IN,,,,,,,,,,,,,,,,EVENTOUT/EVENTOUT,, +PortC,PC15-OSC32_OUT,,,,,,,,,,,,,,,,EVENTOUT/EVENTOUT,, +PortC,PC2,PWR_CSTOP,,,DFSDM1_CKIN1,,I2S2_SDI/SPI2_MISO,DFSDM1_CKOUT,,,OCTOSPIM_P1_IO2,USB_OTG_HS_ULPI_DIR,OCTOSPIM_P1_IO5,FMC_SDNE0,,,EVENTOUT/EVENTOUT,ADC1_INN11/ADC1_INP12/ADC2_INN11/ADC2_INP12, +PortC,PC2_C,PWR_CSTOP,,,DFSDM1_CKIN1,,I2S2_SDI/SPI2_MISO,DFSDM1_CKOUT,,,OCTOSPIM_P1_IO2,USB_OTG_HS_ULPI_DIR,OCTOSPIM_P1_IO5,FMC_SDNE0,,,EVENTOUT/EVENTOUT,ADC1_INN11/ADC1_INP12/ADC2_INN11/ADC2_INP12, +PortC,PC3,PWR_CSLEEP,,,DFSDM1_DATIN1,,I2S2_SDO/SPI2_MOSI,,,,OCTOSPIM_P1_IO0,USB_OTG_HS_ULPI_NXT,OCTOSPIM_P1_IO6,FMC_SDCKE0,,,EVENTOUT/EVENTOUT,ADC2_INP1, +PortC,PC3_C,PWR_CSLEEP,,,DFSDM1_DATIN1,,I2S2_SDO/SPI2_MOSI,,,,OCTOSPIM_P1_IO0,USB_OTG_HS_ULPI_NXT,OCTOSPIM_P1_IO6,FMC_SDCKE0,,,EVENTOUT/EVENTOUT,ADC2_INP1, +PortC,PC4,,,,DFSDM1_CKIN2,,I2S1_MCK,,,,SPDIFRX_IN3,,,FMC_SDNE0,,LTDC_R7,EVENTOUT/EVENTOUT,ADC1_INP4/ADC2_INP4, +PortC,PC5,,,SAI1_D3,DFSDM1_DATIN2,PSSI_D15,,,,,SPDIFRX_IN4,OCTOSPIM_P1_DQS,,FMC_SDCKE0,COMP1_OUT,LTDC_DE,EVENTOUT/EVENTOUT,ADC1_INN4/ADC1_INP8/ADC2_INN4/ADC2_INP8, +PortC,PC6,,,TIM3_CH1,TIM8_CH1,DFSDM1_CKIN3,I2S2_MCK,,USART6_TX,SDMMC1_D0DIR,FMC_NWAIT,SDMMC2_D6,,SDMMC1_D6,DCMI_D0/PSSI_D0,LTDC_HSYNC,EVENTOUT/EVENTOUT,, +PortC,PC7,DEBUG_TRGIO,,TIM3_CH2,TIM8_CH2,DFSDM1_DATIN3,,I2S3_MCK,USART6_RX,SDMMC1_D123DIR,FMC_NE1,SDMMC2_D7,SWPMI1_TX,SDMMC1_D7,DCMI_D1/PSSI_D1,LTDC_G6,EVENTOUT/EVENTOUT,, +PortC,PC8,DEBUG_TRACED1,,TIM3_CH3,TIM8_CH3,,,,USART6_CK,UART5_DE/UART5_RTS,FMC_NCE/FMC_NE2,FMC_INT,SWPMI1_RX,SDMMC1_D0,DCMI_D2/PSSI_D2,,EVENTOUT/EVENTOUT,, +PortC,PC9,RCC_MCO_2,,TIM3_CH4,TIM8_CH4,I2C3_SDA,I2S_CKIN,,,UART5_CTS,OCTOSPIM_P1_IO0,LTDC_G3,SWPMI1_SUSPEND,SDMMC1_D1,DCMI_D3/PSSI_D3,LTDC_B2,EVENTOUT/EVENTOUT,, +PortD,PD0,,,,DFSDM1_CKIN6,,,,,UART4_RX,FDCAN1_RX,,UART9_CTS,FMC_D2/FMC_DA2,,LTDC_B1,EVENTOUT/EVENTOUT,, +PortD,PD1,,,,DFSDM1_DATIN6,,,,,UART4_TX,FDCAN1_TX,,,FMC_D3/FMC_DA3,,,EVENTOUT/EVENTOUT,, +PortD,PD10,,,,DFSDM1_CKOUT,DFSDM2_CKOUT,,,USART3_CK,,,,,FMC_D15/FMC_DA15,,LTDC_B3,EVENTOUT/EVENTOUT,, +PortD,PD11,,,,LPTIM2_IN2,I2C4_SMBA,,,USART3_CTS/USART3_NSS,,OCTOSPIM_P1_IO0,SAI2_SD_A,,FMC_A16/FMC_CLE,,,EVENTOUT/EVENTOUT,, +PortD,PD12,,LPTIM1_IN1,TIM4_CH1,LPTIM2_IN1,I2C4_SCL,,,USART3_DE/USART3_RTS,,OCTOSPIM_P1_IO1,SAI2_FS_A,,FMC_A17/FMC_ALE,DCMI_D12/PSSI_D12,,EVENTOUT/EVENTOUT,, +PortD,PD13,,LPTIM1_OUT,TIM4_CH2,,I2C4_SDA,,,,,OCTOSPIM_P1_IO3,SAI2_SCK_A,UART9_DE/UART9_RTS,FMC_A18,DCMI_D13/PSSI_D13,,EVENTOUT/EVENTOUT,, +PortD,PD14,,,TIM4_CH3,,,,,,UART8_CTS,,,UART9_RX,FMC_D0/FMC_DA0,,,EVENTOUT/EVENTOUT,, +PortD,PD15,,,TIM4_CH4,,,,,,UART8_DE/UART8_RTS,,,UART9_TX,FMC_D1/FMC_DA1,,,EVENTOUT/EVENTOUT,, +PortD,PD2,DEBUG_TRACED2,,TIM3_ETR,,TIM15_BKIN,,,,UART5_RX,LTDC_B7,,,SDMMC1_CMD,DCMI_D11/PSSI_D11,LTDC_B2,EVENTOUT/EVENTOUT,, +PortD,PD3,,,,DFSDM1_CKOUT,,I2S2_CK/SPI2_SCK,,USART2_CTS/USART2_NSS,,,,,FMC_CLK,DCMI_D5/PSSI_D5,LTDC_G7,EVENTOUT/EVENTOUT,, +PortD,PD4,,,,,,,,USART2_DE/USART2_RTS,,,OCTOSPIM_P1_IO4,,FMC_NOE,,,EVENTOUT/EVENTOUT,, +PortD,PD5,,,,,,,,USART2_TX,,,OCTOSPIM_P1_IO5,,FMC_NWE,,,EVENTOUT/EVENTOUT,, +PortD,PD6,,,SAI1_D1,DFSDM1_CKIN4,DFSDM1_DATIN1,I2S3_SDO/SPI3_MOSI,SAI1_SD_A,USART2_RX,,,OCTOSPIM_P1_IO6,SDMMC2_CK,FMC_NWAIT,DCMI_D10/PSSI_D10,LTDC_B2,EVENTOUT/EVENTOUT,, +PortD,PD7,,,,DFSDM1_DATIN4,,I2S1_SDO/SPI1_MOSI,DFSDM1_CKIN1,USART2_CK,,SPDIFRX_IN1,OCTOSPIM_P1_IO7,SDMMC2_CMD,FMC_NE1,,,EVENTOUT/EVENTOUT,, +PortD,PD8,,,,DFSDM1_CKIN3,,,,USART3_TX,,SPDIFRX_IN2,,,FMC_D13/FMC_DA13,,,EVENTOUT/EVENTOUT,, +PortD,PD9,,,,DFSDM1_DATIN3,,,,USART3_RX,,,,,FMC_D14/FMC_DA14,,,EVENTOUT/EVENTOUT,, +PortD,PDR_ON,,,,,,,,,,,,,,,,EVENTOUT,, +PortE,PE0,,LPTIM1_ETR,TIM4_ETR,,LPTIM2_ETR,,,,UART8_RX,,SAI2_MCLK_A,,FMC_NBL0,DCMI_D2/PSSI_D2,LTDC_R0,EVENTOUT/EVENTOUT,, +PortE,PE1,,LPTIM1_IN2,,,,,,,UART8_TX,,,,FMC_NBL1,DCMI_D3/PSSI_D3,LTDC_R6,EVENTOUT/EVENTOUT,, +PortE,PE10,,TIM1_CH2N,,DFSDM1_DATIN4,,,,UART7_CTS,,,OCTOSPIM_P1_IO7,,FMC_D7/FMC_DA7,,,EVENTOUT/EVENTOUT,, +PortE,PE11,,TIM1_CH2,,DFSDM1_CKIN4,,SPI4_NSS,,,,,SAI2_SD_B,OCTOSPIM_P1_NCS,FMC_D8/FMC_DA8,,LTDC_G3,EVENTOUT/EVENTOUT,, +PortE,PE12,,TIM1_CH3N,,DFSDM1_DATIN5,,SPI4_SCK,,,,,SAI2_SCK_B,,FMC_D9/FMC_DA9,COMP1_OUT,LTDC_B4,EVENTOUT/EVENTOUT,, +PortE,PE13,,TIM1_CH3,,DFSDM1_CKIN5,,SPI4_MISO,,,,,SAI2_FS_B,,FMC_D10/FMC_DA10,COMP2_OUT,LTDC_DE,EVENTOUT/EVENTOUT,, +PortE,PE14,,TIM1_CH4,,,,SPI4_MOSI,,,,,SAI2_MCLK_B,,FMC_D11/FMC_DA11,,LTDC_CLK,EVENTOUT/EVENTOUT,, +PortE,PE15,,TIM1_BKIN,,,,,,,,,,USART10_CK,FMC_D12/FMC_DA12,TIM1_BKIN_COMP1/TIM1_BKIN_COMP2,LTDC_R7,EVENTOUT/EVENTOUT,, +PortE,PE2,DEBUG_TRACECLK,,SAI1_CK1,,,SPI4_SCK,SAI1_MCLK_A,,,OCTOSPIM_P1_IO2,,USART10_RX,FMC_A23,,,EVENTOUT/EVENTOUT,, +PortE,PE3,DEBUG_TRACED0,,,,TIM15_BKIN,,SAI1_SD_B,,,,,USART10_TX,FMC_A19,,,EVENTOUT/EVENTOUT,, +PortE,PE4,DEBUG_TRACED1,,SAI1_D2,DFSDM1_DATIN3,TIM15_CH1N,SPI4_NSS,SAI1_FS_A,,,,,,FMC_A20,DCMI_D4/PSSI_D4,LTDC_B0,EVENTOUT/EVENTOUT,, +PortE,PE5,DEBUG_TRACED2,,SAI1_CK2,DFSDM1_CKIN3,TIM15_CH1,SPI4_MISO,SAI1_SCK_A,,,,,,FMC_A21,DCMI_D6/PSSI_D6,LTDC_G0,EVENTOUT/EVENTOUT,, +PortE,PE6,DEBUG_TRACED3,TIM1_BKIN2,SAI1_D1,,TIM15_CH2,SPI4_MOSI,SAI1_SD_A,,,,SAI2_MCLK_B,TIM1_BKIN2_COMP1/TIM1_BKIN2_COMP2,FMC_A22,DCMI_D7/PSSI_D7,LTDC_G1,EVENTOUT/EVENTOUT,, +PortE,PE7,,TIM1_ETR,,DFSDM1_DATIN2,,,,UART7_RX,,,OCTOSPIM_P1_IO4,,FMC_D4/FMC_DA4,,,EVENTOUT/EVENTOUT,, +PortE,PE8,,TIM1_CH1N,,DFSDM1_CKIN2,,,,UART7_TX,,,OCTOSPIM_P1_IO5,,FMC_D5/FMC_DA5,COMP2_OUT,,EVENTOUT/EVENTOUT,, +PortE,PE9,,TIM1_CH1,,DFSDM1_CKOUT,,,,UART7_DE/UART7_RTS,,,OCTOSPIM_P1_IO6,,FMC_D6/FMC_DA6,,,EVENTOUT/EVENTOUT,, +PortF,PF0,,,,,I2C2_SDA,,,,,OCTOSPIM_P2_IO0,,,FMC_A0,,,EVENTOUT/EVENTOUT,, +PortF,PF1,,,,,I2C2_SCL,,,,,OCTOSPIM_P2_IO1,,,FMC_A1,,,EVENTOUT/EVENTOUT,, +PortF,PF10,,TIM16_BKIN,SAI1_D3,,PSSI_D15,,,,,OCTOSPIM_P1_CLK,,,,DCMI_D11/PSSI_D11,LTDC_DE,EVENTOUT/EVENTOUT,, +PortF,PF11,,,,,,SPI5_MOSI,,,,OCTOSPIM_P1_NCLK,SAI2_SD_B,,FMC_SDNRAS,DCMI_D12/PSSI_D12,,EVENTOUT/EVENTOUT,ADC1_INP2, +PortF,PF12,,,,,,,,,,OCTOSPIM_P2_DQS,,,FMC_A6,,,EVENTOUT/EVENTOUT,ADC1_INN2/ADC1_INP6, +PortF,PF13,,,,DFSDM1_DATIN6,I2C4_SMBA,,,,,,,,FMC_A7,,,EVENTOUT/EVENTOUT,ADC2_INP2, +PortF,PF14,,,,DFSDM1_CKIN6,I2C4_SCL,,,,,,,,FMC_A8,,,EVENTOUT/EVENTOUT,ADC2_INN2/ADC2_INP6, +PortF,PF15,,,,,I2C4_SDA,,,,,,,,FMC_A9,,,EVENTOUT/EVENTOUT,, +PortF,PF2,,,,,I2C2_SMBA,,,,,OCTOSPIM_P2_IO2,,,FMC_A2,,,EVENTOUT/EVENTOUT,, +PortF,PF3,,,,,,,,,,OCTOSPIM_P2_IO3,,,FMC_A3,,,EVENTOUT/EVENTOUT,, +PortF,PF4,,,,,,,,,,OCTOSPIM_P2_CLK,,,FMC_A4,,,EVENTOUT/EVENTOUT,, +PortF,PF5,,,,,,,,,,OCTOSPIM_P2_NCLK,,,FMC_A5,,,EVENTOUT/EVENTOUT,, +PortF,PF6,,TIM16_CH1,,,,SPI5_NSS,SAI1_SD_B,UART7_RX,,,OCTOSPIM_P1_IO3,,,,,EVENTOUT/EVENTOUT,, +PortF,PF7,,TIM17_CH1,,,,SPI5_SCK,SAI1_MCLK_B,UART7_TX,,,OCTOSPIM_P1_IO2,,,,,EVENTOUT/EVENTOUT,, +PortF,PF8,,TIM16_CH1N,,,,SPI5_MISO,SAI1_SCK_B,UART7_DE/UART7_RTS,,TIM13_CH1,OCTOSPIM_P1_IO0,,,,,EVENTOUT/EVENTOUT,, +PortF,PF9,,TIM17_CH1N,,,,SPI5_MOSI,SAI1_FS_B,UART7_CTS,,TIM14_CH1,OCTOSPIM_P1_IO1,,,,,EVENTOUT/EVENTOUT,, +PortG,PG0,,,,,,,,,,OCTOSPIM_P2_IO4,,UART9_RX,FMC_A10,,,EVENTOUT/EVENTOUT,, +PortG,PG1,,,,,,,,,,OCTOSPIM_P2_IO5,,UART9_TX,FMC_A11,,,EVENTOUT/EVENTOUT,, +PortG,PG10,,,,OCTOSPIM_P2_IO6,,I2S1_WS/SPI1_NSS,,,,LTDC_G3,SAI2_SD_B,SDMMC2_D1,FMC_NE3,DCMI_D2/PSSI_D2,LTDC_B2,EVENTOUT/EVENTOUT,, +PortG,PG11,,LPTIM1_IN2,,,,I2S1_CK/SPI1_SCK,,,SPDIFRX_IN1,OCTOSPIM_P2_IO7,SDMMC2_D2,USART10_RX,,DCMI_D3/PSSI_D3,LTDC_B3,EVENTOUT/EVENTOUT,, +PortG,PG12,,LPTIM1_IN1,,OCTOSPIM_P2_NCS,,I2S6_SDI/SPI6_MISO,,USART6_DE/USART6_RTS,SPDIFRX_IN2,LTDC_B4,SDMMC2_D3,USART10_TX,FMC_NE4,,LTDC_B1,EVENTOUT/EVENTOUT,, +PortG,PG13,DEBUG_TRACED0,LPTIM1_OUT,,,,I2S6_CK/SPI6_SCK,,USART6_CTS/USART6_NSS,,,SDMMC2_D6,USART10_CTS/USART10_NSS,FMC_A24,,LTDC_R0,EVENTOUT/EVENTOUT,, +PortG,PG14,DEBUG_TRACED1,LPTIM1_ETR,,,,I2S6_SDO/SPI6_MOSI,,USART6_TX,,OCTOSPIM_P1_IO7,SDMMC2_D7,USART10_DE/USART10_RTS,FMC_A25,,LTDC_B0,EVENTOUT/EVENTOUT,, +PortG,PG15,,,,,,,,USART6_CTS/USART6_NSS,,OCTOSPIM_P2_DQS,,USART10_CK,FMC_SDNCAS,DCMI_D13/PSSI_D13,,EVENTOUT/EVENTOUT,, +PortG,PG2,,,,TIM8_BKIN,,,,,,,,TIM8_BKIN_COMP1/TIM8_BKIN_COMP2,FMC_A12,,,EVENTOUT/EVENTOUT,, +PortG,PG3,,,,TIM8_BKIN2,,,,,,,,TIM8_BKIN2_COMP1/TIM8_BKIN2_COMP2,FMC_A13,,,EVENTOUT/EVENTOUT,, +PortG,PG4,,TIM1_BKIN2,,,,,,,,,,TIM1_BKIN2_COMP1/TIM1_BKIN2_COMP2,FMC_A14/FMC_BA0,,,EVENTOUT/EVENTOUT,, +PortG,PG5,,TIM1_ETR,,,,,,,,,,,FMC_A15/FMC_BA1,,,EVENTOUT/EVENTOUT,, +PortG,PG6,,TIM17_BKIN,,,,,,,,,OCTOSPIM_P1_NCS,,FMC_NE3,DCMI_D12/PSSI_D12,LTDC_R7,EVENTOUT/EVENTOUT,, +PortG,PG7,,,,,,,SAI1_MCLK_A,USART6_CK,,OCTOSPIM_P2_DQS,,,FMC_INT,DCMI_D13/PSSI_D13,LTDC_CLK,EVENTOUT/EVENTOUT,, +PortG,PG8,,,,TIM8_ETR,,I2S6_WS/SPI6_NSS,,USART6_DE/USART6_RTS,SPDIFRX_IN3,,,,FMC_SDCLK,,LTDC_G7,EVENTOUT/EVENTOUT,, +PortG,PG9,,,,,,I2S1_SDI/SPI1_MISO,,USART6_RX,SPDIFRX_IN4,OCTOSPIM_P1_IO6,SAI2_FS_B,SDMMC2_D0,FMC_NCE/FMC_NE2,DCMI_VSYNC/PSSI_RDY,,EVENTOUT/EVENTOUT,, +PortH,PH0-OSC_IN,,,,,,,,,,,,,,,,EVENTOUT/EVENTOUT,, +PortH,PH1-OSC_OUT,,,,,,,,,,,,,,,,EVENTOUT/EVENTOUT,, +PortH,PH10,,,TIM5_CH1,,I2C4_SMBA,,,,,,,,FMC_D18,DCMI_D1/PSSI_D1,LTDC_R4,EVENTOUT/EVENTOUT,, +PortH,PH11,,,TIM5_CH2,,I2C4_SCL,,,,,,,,FMC_D19,DCMI_D2/PSSI_D2,LTDC_R5,EVENTOUT/EVENTOUT,, +PortH,PH12,,,TIM5_CH3,,I2C4_SDA,,,,,,,,FMC_D20,DCMI_D3/PSSI_D3,LTDC_R6,EVENTOUT/EVENTOUT,, +PortH,PH13,,,,TIM8_CH1N,,,,,UART4_TX,FDCAN1_TX,,,FMC_D21,,LTDC_G2,EVENTOUT/EVENTOUT,, +PortH,PH14,,,,TIM8_CH2N,,,,,UART4_RX,FDCAN1_RX,,,FMC_D22,DCMI_D4/PSSI_D4,LTDC_G3,EVENTOUT/EVENTOUT,, +PortH,PH15,,,,TIM8_CH3N,,,,,,,,,FMC_D23,DCMI_D11/PSSI_D11,LTDC_G4,EVENTOUT/EVENTOUT,, +PortH,PH2,,LPTIM1_IN2,,,,,,,,OCTOSPIM_P1_IO4,SAI2_SCK_B,,FMC_SDCKE0,,LTDC_R0,EVENTOUT/EVENTOUT,, +PortH,PH3,,,,,,,,,,OCTOSPIM_P1_IO5,SAI2_MCLK_B,,FMC_SDNE0,,LTDC_R1,EVENTOUT/EVENTOUT,, +PortH,PH4,,,,,I2C2_SCL,,,,,LTDC_G5,USB_OTG_HS_ULPI_NXT,,,PSSI_D14,LTDC_G4,EVENTOUT/EVENTOUT,, +PortH,PH5,,,,,I2C2_SDA,SPI5_NSS,,,,,,,FMC_SDNWE,,,EVENTOUT/EVENTOUT,, +PortH,PH6,,,TIM12_CH1,,I2C2_SMBA,SPI5_SCK,,,,,,,FMC_SDNE1,DCMI_D8/PSSI_D8,,EVENTOUT/EVENTOUT,, +PortH,PH7,,,,,I2C3_SCL,SPI5_MISO,,,,,,,FMC_SDCKE1,DCMI_D9/PSSI_D9,,EVENTOUT/EVENTOUT,, +PortH,PH8,,,TIM5_ETR,,I2C3_SDA,,,,,,,,FMC_D16,DCMI_HSYNC/PSSI_DE,LTDC_R2,EVENTOUT/EVENTOUT,, +PortH,PH9,,,TIM12_CH2,,I2C3_SMBA,,,,,,,,FMC_D17,DCMI_D0/PSSI_D0,LTDC_R3,EVENTOUT/EVENTOUT,, +PortI,PI0,,,TIM5_CH4,,,I2S2_WS/SPI2_NSS,,,,,,,FMC_D24,DCMI_D13/PSSI_D13,LTDC_G5,EVENTOUT/EVENTOUT,, +PortI,PI1,,,,TIM8_BKIN2,,I2S2_CK/SPI2_SCK,,,,,,TIM8_BKIN2_COMP1/TIM8_BKIN2_COMP2,FMC_D25,DCMI_D8/PSSI_D8,LTDC_G6,EVENTOUT/EVENTOUT,, +PortI,PI10,,,,OCTOSPIM_P2_IO1,,,,,,,,,FMC_D31,PSSI_D14,LTDC_HSYNC,EVENTOUT/EVENTOUT,, +PortI,PI11,,,,OCTOSPIM_P2_IO2,,,,,,LTDC_G6,USB_OTG_HS_ULPI_DIR,,,PSSI_D15,,EVENTOUT/EVENTOUT,, +PortI,PI12,,,,OCTOSPIM_P2_IO3,,,,,,,,,,,LTDC_HSYNC,EVENTOUT/EVENTOUT,, +PortI,PI13,,,,OCTOSPIM_P2_CLK,,,,,,,,,,,LTDC_VSYNC,EVENTOUT/EVENTOUT,, +PortI,PI14,,,,OCTOSPIM_P2_NCLK,,,,,,,,,,,LTDC_CLK,EVENTOUT/EVENTOUT,, +PortI,PI15,,,,,,,,,,LTDC_G2,,,,,LTDC_R0,EVENTOUT/EVENTOUT,, +PortI,PI2,,,,TIM8_CH4,,I2S2_SDI/SPI2_MISO,,,,,,,FMC_D26,DCMI_D9/PSSI_D9,LTDC_G7,EVENTOUT/EVENTOUT,, +PortI,PI3,,,,TIM8_ETR,,I2S2_SDO/SPI2_MOSI,,,,,,,FMC_D27,DCMI_D10/PSSI_D10,,EVENTOUT/EVENTOUT,, +PortI,PI4,,,,TIM8_BKIN,,,,,,,SAI2_MCLK_A,TIM8_BKIN_COMP1/TIM8_BKIN_COMP2,FMC_NBL2,DCMI_D5/PSSI_D5,LTDC_B4,EVENTOUT/EVENTOUT,, +PortI,PI5,,,,TIM8_CH1,,,,,,,SAI2_SCK_A,,FMC_NBL3,DCMI_VSYNC/PSSI_RDY,LTDC_B5,EVENTOUT/EVENTOUT,, +PortI,PI6,,,,TIM8_CH2,,,,,,,SAI2_SD_A,,FMC_D28,DCMI_D6/PSSI_D6,LTDC_B6,EVENTOUT/EVENTOUT,, +PortI,PI7,,,,TIM8_CH3,,,,,,,SAI2_FS_A,,FMC_D29,DCMI_D7/PSSI_D7,LTDC_B7,EVENTOUT/EVENTOUT,, +PortI,PI8,,,,,,,,,,,,,,,,EVENTOUT/EVENTOUT,, +PortI,PI9,,,,OCTOSPIM_P2_IO0,,,,,UART4_RX,FDCAN1_RX,,,FMC_D30,,LTDC_VSYNC,EVENTOUT/EVENTOUT,, +PortJ,PJ0,,,,,,,,,,LTDC_R7,,,,,LTDC_R1,EVENTOUT/EVENTOUT,, +PortJ,PJ1,,,,OCTOSPIM_P2_IO4,,,,,,,,,,,LTDC_R2,EVENTOUT/EVENTOUT,, +PortJ,PJ10,,TIM1_CH2N,,TIM8_CH2,,SPI5_MOSI,,,,,,,,,LTDC_G3,EVENTOUT/EVENTOUT,, +PortJ,PJ11,,TIM1_CH2,,TIM8_CH2N,,SPI5_MISO,,,,,,,,,LTDC_G4,EVENTOUT/EVENTOUT,, +PortJ,PJ12,DEBUG_TRGOUT,,,,,,,,,LTDC_G3,,,,,LTDC_B0,EVENTOUT/EVENTOUT,, +PortJ,PJ13,,,,,,,,,,LTDC_B4,,,,,LTDC_B1,EVENTOUT/EVENTOUT,, +PortJ,PJ14,,,,,,,,,,,,,,,LTDC_B2,EVENTOUT/EVENTOUT,, +PortJ,PJ15,,,,,,,,,,,,,,,LTDC_B3,EVENTOUT/EVENTOUT,, +PortJ,PJ2,,,,OCTOSPIM_P2_IO5,,,,,,,,,,,LTDC_R3,EVENTOUT/EVENTOUT,, +PortJ,PJ3,,,,,,,,,,,,UART9_DE/UART9_RTS,,,LTDC_R4,EVENTOUT/EVENTOUT,, +PortJ,PJ4,,,,,,,,,,,,UART9_CTS,,,LTDC_R5,EVENTOUT/EVENTOUT,, +PortJ,PJ5,,,,,,,,,,,,,,,LTDC_R6,EVENTOUT/EVENTOUT,, +PortJ,PJ6,,,,TIM8_CH2,,,,,,,,,,,LTDC_R7,EVENTOUT/EVENTOUT,, +PortJ,PJ7,DEBUG_TRGIN,,,TIM8_CH2N,,,,,,,,,,,LTDC_G0,EVENTOUT/EVENTOUT,, +PortJ,PJ8,,TIM1_CH3N,,TIM8_CH1,,,,,UART8_TX,,,,,,LTDC_G1,EVENTOUT/EVENTOUT,, +PortJ,PJ9,,TIM1_CH3,,TIM8_CH1N,,,,,UART8_RX,,,,,,LTDC_G2,EVENTOUT/EVENTOUT,, +PortK,PK0,,TIM1_CH1N,,TIM8_CH3,,SPI5_SCK,,,,,,,,,LTDC_G5,EVENTOUT/EVENTOUT,, +PortK,PK1,,TIM1_CH1,,TIM8_CH3N,,SPI5_NSS,,,,,,,,,LTDC_G6,EVENTOUT/EVENTOUT,, +PortK,PK2,,TIM1_BKIN,,TIM8_BKIN,,,,,,,TIM8_BKIN_COMP1/TIM8_BKIN_COMP2,TIM1_BKIN_COMP1/TIM1_BKIN_COMP2,,,LTDC_G7,EVENTOUT/EVENTOUT,, +PortK,PK3,,,,OCTOSPIM_P2_IO6,,,,,,,,,,,LTDC_B4,EVENTOUT/EVENTOUT,, +PortK,PK4,,,,OCTOSPIM_P2_IO7,,,,,,,,,,,LTDC_B5,EVENTOUT/EVENTOUT,, +PortK,PK5,,,,OCTOSPIM_P2_NCS,,,,,,,,,,,LTDC_B6,EVENTOUT/EVENTOUT,, +PortK,PK6,,,,OCTOSPIM_P2_DQS,,,,,,,,,,,LTDC_B7,EVENTOUT/EVENTOUT,, +PortK,PK7,,,,,,,,,,,,,,,LTDC_DE,EVENTOUT/EVENTOUT,, diff --git a/ports/stm32/extint.c b/ports/stm32/extint.c index 695655f09..699bc6004 100644 --- a/ports/stm32/extint.c +++ b/ports/stm32/extint.c @@ -166,7 +166,11 @@ STATIC const uint8_t nvic_irq_channel[EXTI_NUM_VECTORS] = { #if defined(STM32H7) PVD_AVD_IRQn, RTC_Alarm_IRQn, + #if defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) + RTC_TAMP_STAMP_CSS_LSE_IRQn, + #else TAMP_STAMP_IRQn, + #endif RTC_WKUP_IRQn, #elif defined(STM32WB) PVD_PVM_IRQn, diff --git a/ports/stm32/flash.c b/ports/stm32/flash.c index d399ece86..b926679f9 100644 --- a/ports/stm32/flash.c +++ b/ports/stm32/flash.c @@ -253,7 +253,11 @@ int flash_erase(uint32_t flash_dest, uint32_t num_word32) { #endif EraseInitStruct.TypeErase = TYPEERASE_SECTORS; + #if defined(FLASH_CR_PSIZE) EraseInitStruct.VoltageRange = VOLTAGE_RANGE_3; // voltage range needs to be 2.7V to 3.6V + #else + EraseInitStruct.VoltageRange = 0; // unused parameter on STM32H7A3/B3 + #endif #if defined(STM32H7) EraseInitStruct.Banks = get_bank(flash_dest); #endif diff --git a/ports/stm32/machine_adc.c b/ports/stm32/machine_adc.c index f28bd5b39..a114a9ad1 100644 --- a/ports/stm32/machine_adc.c +++ b/ports/stm32/machine_adc.c @@ -130,6 +130,8 @@ void adc_config(ADC_TypeDef *adc, uint32_t bits) { adc->CFGR2 = 2 << ADC_CFGR2_CKMODE_Pos; // PCLK/4 (synchronous clock mode) #elif defined(STM32F4) || defined(STM32F7) || defined(STM32L4) ADCx_COMMON->CCR = 0; // ADCPR=PCLK/2 + #elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) + ADC12_COMMON->CCR = 3 << ADC_CCR_CKMODE_Pos; #elif defined(STM32H7) ADC12_COMMON->CCR = 3 << ADC_CCR_CKMODE_Pos; ADC3_COMMON->CCR = 3 << ADC_CCR_CKMODE_Pos; @@ -290,8 +292,9 @@ STATIC void adc_config_channel(ADC_TypeDef *adc, uint32_t channel, uint32_t samp *smpr = (*smpr & ~(7 << (channel * 3))) | sample_time << (channel * 3); // select sample time #elif defined(STM32H7) || defined(STM32L4) || defined(STM32WB) - - #if defined(STM32H7) + #if defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) + ADC_Common_TypeDef *adc_common = ADC12_COMMON; + #elif defined(STM32H7) adc->PCSEL |= 1 << channel; ADC_Common_TypeDef *adc_common = adc == ADC3 ? ADC3_COMMON : ADC12_COMMON; #elif defined(STM32L4) @@ -413,7 +416,7 @@ STATIC mp_obj_t machine_adc_make_new(const mp_obj_type_t *type, size_t n_args, s } else if (pin->adc_num & PIN_ADC2) { adc = ADC2; #endif - #if defined(ADC2) + #if defined(ADC3) } else if (pin->adc_num & PIN_ADC3) { adc = ADC3; #endif diff --git a/ports/stm32/main.c b/ports/stm32/main.c index e506cc571..5d1ff2dcf 100644 --- a/ports/stm32/main.c +++ b/ports/stm32/main.c @@ -378,6 +378,9 @@ void stm32_main(uint32_t reset_mode) { // enable the CCM RAM __HAL_RCC_CCMDATARAMEN_CLK_ENABLE(); #endif + #elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) + // Enable SRAM clock. + __HAL_RCC_SRDSRAM_CLK_ENABLE(); #elif defined(STM32H7) // Enable D2 SRAM1/2/3 clocks. __HAL_RCC_D2SRAM1_CLK_ENABLE(); diff --git a/ports/stm32/mpconfigboard_common.h b/ports/stm32/mpconfigboard_common.h index 0cf6adce3..bd00bae9c 100644 --- a/ports/stm32/mpconfigboard_common.h +++ b/ports/stm32/mpconfigboard_common.h @@ -314,6 +314,17 @@ #define MICROPY_HW_MAX_UART (8) #define MICROPY_HW_MAX_LPUART (0) +// Configuration for STM32H7A3/B3 series +#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || \ + defined(STM32H7B3xx) || defined(STM32H7B3xxQ) + +#define MP_HAL_UNIQUE_ID_ADDRESS (0x08fff800) +#define PYB_EXTI_NUM_VECTORS (24) +#define MICROPY_HW_MAX_I2C (4) +#define MICROPY_HW_MAX_TIMER (17) +#define MICROPY_HW_MAX_UART (10) +#define MICROPY_HW_MAX_LPUART (1) + // Configuration for STM32H7 series #elif defined(STM32H7) diff --git a/ports/stm32/powerctrl.c b/ports/stm32/powerctrl.c index 9d9cc7f51..406325581 100644 --- a/ports/stm32/powerctrl.c +++ b/ports/stm32/powerctrl.c @@ -36,14 +36,22 @@ #define RCC_SR_SFTRSTF RCC_RSR_SFTRSTF #elif defined(STM32H747xx) #define RCC_SR_SFTRSTF RCC_RSR_SFT2RSTF +#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) +#define RCC_SR_SFTRSTF RCC_RSR_SFTRSTF #endif #define RCC_SR_RMVF RCC_RSR_RMVF // This macro returns the actual voltage scaling level factoring in the power overdrive bit. // If the current voltage scale is VOLTAGE_SCALE1 and PWER_ODEN bit is set return VOLTAGE_SCALE0 // otherwise the current voltage scaling (level VOS1 to VOS3) set in PWER_CSR is returned instead. +#if defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || \ + defined(STM32H7B3xx) || defined(STM32H7B3xxQ) +// TODO +#define POWERCTRL_GET_VOLTAGE_SCALING() PWR_REGULATOR_VOLTAGE_SCALE0 +#else #define POWERCTRL_GET_VOLTAGE_SCALING() \ (((PWR->CSR1 & PWR_CSR1_ACTVOS) && (SYSCFG->PWRCR & SYSCFG_PWRCR_ODEN)) ? \ PWR_REGULATOR_VOLTAGE_SCALE0 : (PWR->CSR1 & PWR_CSR1_ACTVOS)) +#endif #else #define RCC_SR CSR #define RCC_SR_SFTRSTF RCC_CSR_SFTRSTF @@ -148,6 +156,15 @@ STATIC const sysclk_scaling_table_entry_t volt_scale_table[] = { { 180, PWR_REGULATOR_VOLTAGE_SCALE2 }, // Above 180MHz uses default PWR_REGULATOR_VOLTAGE_SCALE1 }; +#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || \ + defined(STM32H7B3xx) || defined(STM32H7B3xxQ) +STATIC const sysclk_scaling_table_entry_t volt_scale_table[] = { + // See table 15 "FLASH recommended number of wait states and programming delay" of RM0455. + {88, PWR_REGULATOR_VOLTAGE_SCALE3}, + {160, PWR_REGULATOR_VOLTAGE_SCALE2}, + {225, PWR_REGULATOR_VOLTAGE_SCALE1}, + {280, PWR_REGULATOR_VOLTAGE_SCALE0}, +}; #elif defined(STM32H7) STATIC const sysclk_scaling_table_entry_t volt_scale_table[] = { // See table 55 "Kernel clock distribution overview" of RM0433. @@ -836,6 +853,9 @@ void powerctrl_enter_standby_mode(void) { #if defined(STM32F0) || defined(STM32L0) #define CR_BITS (RTC_CR_ALRAIE | RTC_CR_WUTIE | RTC_CR_TSIE) #define ISR_BITS (RTC_ISR_ALRAF | RTC_ISR_WUTF | RTC_ISR_TSF) + #elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) + #define CR_BITS (RTC_CR_ALRAIE | RTC_CR_ALRBIE | RTC_CR_WUTIE | RTC_CR_TSIE) + #define SR_BITS (RTC_SR_ALRAF | RTC_SR_ALRBF | RTC_SR_WUTF | RTC_SR_TSF) #else #define CR_BITS (RTC_CR_ALRAIE | RTC_CR_ALRBIE | RTC_CR_WUTIE | RTC_CR_TSIE) #define ISR_BITS (RTC_ISR_ALRAF | RTC_ISR_ALRBF | RTC_ISR_WUTF | RTC_ISR_TSF) @@ -852,7 +872,11 @@ void powerctrl_enter_standby_mode(void) { RTC->CR &= ~CR_BITS; // clear RTC wake-up flags + #if defined(SR_BITS) + RTC->SR &= ~SR_BITS; + #else RTC->ISR &= ~ISR_BITS; + #endif #if defined(STM32F7) // Save EWUP state diff --git a/ports/stm32/rtc.c b/ports/stm32/rtc.c index ab8b49e18..a5553b8a0 100644 --- a/ports/stm32/rtc.c +++ b/ports/stm32/rtc.c @@ -339,9 +339,15 @@ STATIC HAL_StatusTypeDef PYB_RTC_Init(RTC_HandleTypeDef *hrtc) { hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16); // Exit Initialization mode + #if defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) + hrtc->Instance->ICSR &= (uint32_t) ~RTC_ICSR_INIT; + #else hrtc->Instance->ISR &= (uint32_t) ~RTC_ISR_INIT; + #endif - #if defined(STM32L0) || defined(STM32L4) || defined(STM32H7) || defined(STM32WB) + #if defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) + // do nothing + #elif defined(STM32L0) || defined(STM32L4) || defined(STM32H7) || defined(STM32WB) hrtc->Instance->OR &= (uint32_t) ~RTC_OR_ALARMOUTTYPE; hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType); #elif defined(STM32F7) @@ -693,8 +699,13 @@ mp_obj_t pyb_rtc_wakeup(size_t n_args, const mp_obj_t *args) { RTC->CR &= ~RTC_CR_WUTE; // wait until WUTWF is set + #if defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) + while (!(RTC->ICSR & RTC_ICSR_WUTWF)) { + } + #else while (!(RTC->ISR & RTC_ISR_WUTWF)) { } + #endif if (enable) { // program WUT @@ -721,7 +732,11 @@ mp_obj_t pyb_rtc_wakeup(size_t n_args, const mp_obj_t *args) { #endif // clear interrupt flags + #if defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) + RTC->SR &= ~RTC_SR_WUTF; + #else RTC->ISR &= ~RTC_ISR_WUTF; + #endif #if defined(STM32L4) || defined(STM32WB) EXTI->PR1 = 1 << EXTI_RTC_WAKEUP; #elif defined(STM32H7) diff --git a/ports/stm32/stm32_it.c b/ports/stm32/stm32_it.c index 4dde201a2..ed97c4fe0 100644 --- a/ports/stm32/stm32_it.c +++ b/ports/stm32/stm32_it.c @@ -527,7 +527,11 @@ void TAMP_STAMP_IRQHandler(void) { void RTC_WKUP_IRQHandler(void) { IRQ_ENTER(RTC_WKUP_IRQn); + #if defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) + RTC->SR &= ~RTC_SR_WUTF; // clear wakeup interrupt flag + #else RTC->ISR &= ~RTC_ISR_WUTF; // clear wakeup interrupt flag + #endif Handle_EXTI_Irq(EXTI_RTC_WAKEUP); // clear EXTI flag and execute optional callback IRQ_EXIT(RTC_WKUP_IRQn); } diff --git a/ports/stm32/system_stm32.c b/ports/stm32/system_stm32.c index 4e89204bf..8142fd0a5 100644 --- a/ports/stm32/system_stm32.c +++ b/ports/stm32/system_stm32.c @@ -180,7 +180,9 @@ void SystemClock_Config(void) { #if defined(STM32F4) || defined(STM32F7) || defined(STM32H7) /* Enable Power Control clock */ - #if defined(STM32H7) + #if defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) + MODIFY_REG(PWR->CR3, PWR_SUPPLY_CONFIG_MASK, PWR_CR3_SMPSEN); + #elif defined(STM32H7) MODIFY_REG(PWR->CR3, PWR_CR3_SCUEN, 0); #else __PWR_CLK_ENABLE(); @@ -197,7 +199,7 @@ void SystemClock_Config(void) { #if defined(STM32H7) // Wait for PWR_FLAG_VOSRDY - while ((PWR->D3CR & (PWR_D3CR_VOSRDY)) != PWR_D3CR_VOSRDY) { + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) { } #endif diff --git a/ports/stm32/timer.c b/ports/stm32/timer.c index a34d2984d..c23e7e02d 100644 --- a/ports/stm32/timer.c +++ b/ports/stm32/timer.c @@ -239,6 +239,9 @@ uint32_t timer_get_source_freq(uint32_t tim_id) { #if defined(STM32F0) source = HAL_RCC_GetPCLK1Freq(); clk_div = RCC->CFGR & RCC_CFGR_PPRE; + #elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) + source = HAL_RCC_GetPCLK2Freq(); + clk_div = RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2; #elif defined(STM32H7) source = HAL_RCC_GetPCLK2Freq(); clk_div = RCC->D2CFGR & RCC_D2CFGR_D2PPRE2; @@ -251,6 +254,8 @@ uint32_t timer_get_source_freq(uint32_t tim_id) { source = HAL_RCC_GetPCLK1Freq(); #if defined(STM32F0) clk_div = RCC->CFGR & RCC_CFGR_PPRE; + #elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) + clk_div = RCC->CDCFGR1 & RCC_CDCFGR2_CDPPRE1; #elif defined(STM32H7) clk_div = RCC->D2CFGR & RCC_D2CFGR_D2PPRE1; #else diff --git a/ports/stm32/uart.c b/ports/stm32/uart.c index d2953b264..627c33397 100644 --- a/ports/stm32/uart.c +++ b/ports/stm32/uart.c @@ -717,6 +717,33 @@ uint32_t uart_get_source_freq(pyb_uart_obj_t *self) { uart_clk = LSE_VALUE; break; } + #elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) + uint32_t csel; + if (self->uart_id == 1 || self->uart_id == 6 || self->uart_id == 9 || self->uart_id == 10) { + csel = RCC->CDCCIP2R >> 3; + } else { + csel = RCC->CDCCIP2R; + } + switch (csel & 3) { + case 0: + if (self->uart_id == 1 || self->uart_id == 6 || self->uart_id == 9 || self->uart_id == 10) { + uart_clk = HAL_RCC_GetPCLK2Freq(); + } else { + uart_clk = HAL_RCC_GetPCLK1Freq(); + } + break; + case 3: + uart_clk = HSI_VALUE; + break; + case 4: + uart_clk = CSI_VALUE; + break; + case 5: + uart_clk = LSE_VALUE; + break; + default: + break; + } #elif defined(STM32H7) uint32_t csel; if (self->uart_id == 1 || self->uart_id == 6) { diff --git a/ports/stm32/usbd_conf.c b/ports/stm32/usbd_conf.c index d24881d20..50e10ba17 100644 --- a/ports/stm32/usbd_conf.c +++ b/ports/stm32/usbd_conf.c @@ -59,6 +59,7 @@ PCD_HandleTypeDef pcd_hs_handle; * @retval None */ void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) { + #if MICROPY_HW_USB_FS if (hpcd->Instance == USB_OTG_FS) { #if defined(STM32H7) const uint32_t otg_alt = GPIO_AF10_OTG1_FS; @@ -125,12 +126,18 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) { NVIC_SetPriority(OTG_FS_IRQn, IRQ_PRI_OTG_FS); HAL_NVIC_EnableIRQ(OTG_FS_IRQn); #endif + + return; } + #endif + #if MICROPY_HW_USB_HS - else if (hpcd->Instance == USB_OTG_HS) { + if (hpcd->Instance == USB_OTG_HS) { #if MICROPY_HW_USB_HS_IN_FS - #if defined(STM32H7) + #if defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) + const uint32_t otg_alt = GPIO_AF10_OTG1_FS; + #elif defined(STM32H7) const uint32_t otg_alt = GPIO_AF12_OTG2_FS; #else const uint32_t otg_alt = GPIO_AF12_OTG_HS_FS; @@ -204,13 +211,17 @@ void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) { __HAL_RCC_USB_CLK_DISABLE(); #else + #if MICROPY_HW_USB_FS if (hpcd->Instance == USB_OTG_FS) { /* Disable USB FS Clocks */ __USB_OTG_FS_CLK_DISABLE(); __SYSCFG_CLK_DISABLE(); + return; } + #endif + #if MICROPY_HW_USB_HS - else if (hpcd->Instance == USB_OTG_HS) { + if (hpcd->Instance == USB_OTG_HS) { /* Disable USB FS Clocks */ __USB_OTG_HS_CLK_DISABLE(); __SYSCFG_CLK_DISABLE(); |