diff options
114 files changed, 1330 insertions, 5488 deletions
diff --git a/ports/renesas-ra/Makefile b/ports/renesas-ra/Makefile index 8dd172b50..bcfae8555 100644 --- a/ports/renesas-ra/Makefile +++ b/ports/renesas-ra/Makefile @@ -342,11 +342,6 @@ SRC_O += \ SRC_O += \ shared/runtime/gchelper_thumb2.o -HAL_SRC_C += $(addprefix $(HAL_DIR)/ra/board/$(BOARD_LOW)/,\ - board_init.c \ - board_leds.c \ - ) - HAL_SRC_C += $(addprefix $(HAL_DIR)/ra/fsp/src/bsp/mcu/all/,\ bsp_clocks.c \ bsp_common.c \ diff --git a/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/bsp/bsp_cfg.h index 9940d7ed3..e341e9994 100644 --- a/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/bsp/bsp_cfg.h +++ b/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -1,6 +1,10 @@ /* generated configuration header file - do not edit */ #ifndef BSP_CFG_H_ #define BSP_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #include "bsp_clock_cfg.h" #include "bsp_mcu_family_cfg.h" #include "board_cfg.h" @@ -14,7 +18,13 @@ #define BSP_CFG_RTOS (0) #endif #endif +#ifndef BSP_CFG_RTC_USED +#define BSP_CFG_RTC_USED (1) +#endif #undef RA_NOT_DEFINED +#if defined(_RA_BOOT_IMAGE) +#define BSP_CFG_BOOT_IMAGE (1) +#endif #define BSP_CFG_MCU_VCC_MV (3300) #define BSP_CFG_STACK_MAIN_BYTES (0x1000) #define BSP_CFG_HEAP_BYTES (0x4980) @@ -25,15 +35,14 @@ #define BSP_CFG_PFS_PROTECT ((1)) #define BSP_CFG_C_RUNTIME_INIT ((1)) +#define BSP_CFG_EARLY_INIT ((0)) -#define BSP_CFG_SOFT_RESET_SUPPORTED ((0)) +#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) #endif -#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) -#endif + #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) #endif @@ -46,4 +55,8 @@ #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 #endif + +#ifdef __cplusplus +} +#endif #endif /* BSP_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h index f52adbafa..d810dabb2 100644 --- a/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h +++ b/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -2,6 +2,7 @@ #ifndef BSP_MCU_DEVICE_PN_CFG_H_ #define BSP_MCU_DEVICE_PN_CFG_H_ #define BSP_MCU_R7FA4M1AB3CFP +#define BSP_MCU_FEATURE_SET ('A') #define BSP_ROM_SIZE_BYTES (262144) #define BSP_RAM_SIZE_BYTES (32768) #define BSP_DATA_FLASH_SIZE_BYTES (8192) diff --git a/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h index 4766823b3..a9b4de20c 100644 --- a/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ b/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -1,6 +1,10 @@ /* generated configuration header file - do not edit */ #ifndef BSP_MCU_FAMILY_CFG_H_ #define BSP_MCU_FAMILY_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #include "bsp_mcu_device_pn_cfg.h" #include "bsp_mcu_device_cfg.h" #include "../../../ra/fsp/src/bsp/mcu/ra4m1/bsp_mcu_info.h" @@ -22,7 +26,6 @@ #endif #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) #define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) -#define BSP_MCU_VBATT_SUPPORT (1) #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) @@ -50,7 +53,9 @@ #define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) #define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) #define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) - +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ #define BSP_PRV_IELS_ENUM(vector) (ELC_##vector) @@ -71,4 +76,8 @@ #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) #endif + +#ifdef __cplusplus +} +#endif #endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_adc_cfg.h b/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_adc_cfg.h index 9c59889ca..be8a42720 100644 --- a/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_adc_cfg.h +++ b/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_adc_cfg.h @@ -1,5 +1,13 @@ /* generated configuration header file - do not edit */ #ifndef R_ADC_CFG_H_ #define R_ADC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #define ADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif #endif /* R_ADC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_agt_cfg.h b/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_agt_cfg.h deleted file mode 100644 index d3ab55923..000000000 --- a/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_agt_cfg.h +++ /dev/null @@ -1,7 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_AGT_CFG_H_ -#define R_AGT_CFG_H_ -#define AGT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#define AGT_CFG_OUTPUT_SUPPORT_ENABLE (0) -#define AGT_CFG_INPUT_SUPPORT_ENABLE (0) -#endif /* R_AGT_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_dtc_cfg.h b/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_dtc_cfg.h deleted file mode 100644 index 21405f967..000000000 --- a/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_dtc_cfg.h +++ /dev/null @@ -1,6 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_DTC_CFG_H_ -#define R_DTC_CFG_H_ -#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#define DTC_CFG_VECTOR_TABLE_SECTION_NAME ".fsp_dtc_vector_table" -#endif /* R_DTC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_flash_lp_cfg.h b/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_flash_lp_cfg.h index 26879f9f4..7f285cace 100644 --- a/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_flash_lp_cfg.h +++ b/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_flash_lp_cfg.h @@ -1,7 +1,15 @@ /* generated configuration header file - do not edit */ #ifndef R_FLASH_LP_CFG_H_ #define R_FLASH_LP_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #define FLASH_LP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) #define FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (1) #define FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (0) + +#ifdef __cplusplus +} +#endif #endif /* R_FLASH_LP_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_icu_cfg.h b/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_icu_cfg.h deleted file mode 100644 index 5e77b6980..000000000 --- a/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_icu_cfg.h +++ /dev/null @@ -1,5 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_ICU_CFG_H_ -#define R_ICU_CFG_H_ -#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#endif /* R_ICU_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_ioport_cfg.h b/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_ioport_cfg.h index 6b4353d23..d2688bf5b 100644 --- a/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_ioport_cfg.h +++ b/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -1,5 +1,13 @@ /* generated configuration header file - do not edit */ #ifndef R_IOPORT_CFG_H_ #define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif #endif /* R_IOPORT_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_lpm_cfg.h b/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_lpm_cfg.h index 5f4d5c4a7..6712eee6a 100644 --- a/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_lpm_cfg.h +++ b/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_lpm_cfg.h @@ -1,5 +1,14 @@ /* generated configuration header file - do not edit */ #ifndef R_LPM_CFG_H_ #define R_LPM_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #define LPM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define LPM_CFG_STANDBY_LIMIT (0) + +#ifdef __cplusplus +} +#endif #endif /* R_LPM_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_rtc_cfg.h b/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_rtc_cfg.h deleted file mode 100644 index 484b7ed04..000000000 --- a/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_rtc_cfg.h +++ /dev/null @@ -1,5 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_RTC_CFG_H_ -#define R_RTC_CFG_H_ -#define RTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#endif /* R_RTC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_sci_uart_cfg.h b/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_sci_uart_cfg.h deleted file mode 100644 index c70c0be34..000000000 --- a/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_sci_uart_cfg.h +++ /dev/null @@ -1,8 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_SCI_UART_CFG_H_ -#define R_SCI_UART_CFG_H_ -#define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#define SCI_UART_CFG_FIFO_SUPPORT (0) -#define SCI_UART_CFG_DTC_SUPPORTED (0) -#define SCI_UART_CFG_FLOW_CONTROL_SUPPORT (0) -#endif /* R_SCI_UART_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_spi_cfg.h b/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_spi_cfg.h deleted file mode 100644 index 861fe1219..000000000 --- a/ports/renesas-ra/boards/EK_RA4M1/ra_cfg/fsp_cfg/r_spi_cfg.h +++ /dev/null @@ -1,7 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_SPI_CFG_H_ -#define R_SPI_CFG_H_ -#define SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#define SPI_DTC_SUPPORT_ENABLE (1) -#define SPI_TRANSMIT_FROM_RXI_ISR (0) -#endif /* R_SPI_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4M1/ra_gen/bsp_clock_cfg.h b/ports/renesas-ra/boards/EK_RA4M1/ra_gen/bsp_clock_cfg.h index cf28c33d7..5f407b90f 100644 --- a/ports/renesas-ra/boards/EK_RA4M1/ra_gen/bsp_clock_cfg.h +++ b/ports/renesas-ra/boards/EK_RA4M1/ra_gen/bsp_clock_cfg.h @@ -7,7 +7,7 @@ #define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ #define BSP_CFG_HOCO_FREQUENCY (0) /* HOCO 24MHz */ #define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */ -#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_8_0 /* PLL Mul x8 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(8U, 0U) /* PLL Mul x8 */ #define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ #define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */ diff --git a/ports/renesas-ra/boards/EK_RA4M1/ra_gen/common_data.c b/ports/renesas-ra/boards/EK_RA4M1/ra_gen/common_data.c index 34aad762f..fb539ac4a 100644 --- a/ports/renesas-ra/boards/EK_RA4M1/ra_gen/common_data.c +++ b/ports/renesas-ra/boards/EK_RA4M1/ra_gen/common_data.c @@ -3,5 +3,3 @@ ioport_instance_ctrl_t g_ioport_ctrl; const ioport_instance_t g_ioport = { .p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg, }; -void g_common_init(void) { -} diff --git a/ports/renesas-ra/boards/EK_RA4M1/ra_gen/common_data.h b/ports/renesas-ra/boards/EK_RA4M1/ra_gen/common_data.h index e2eb70836..3a764eda7 100644 --- a/ports/renesas-ra/boards/EK_RA4M1/ra_gen/common_data.h +++ b/ports/renesas-ra/boards/EK_RA4M1/ra_gen/common_data.h @@ -3,14 +3,16 @@ #define COMMON_DATA_H_ #include <stdint.h> #include "bsp_api.h" +#include "r_icu.h" +#include "r_external_irq_api.h" #include "r_ioport.h" #include "bsp_pin_cfg.h" FSP_HEADER + /* IOPORT Instance */ extern const ioport_instance_t g_ioport; /* IOPORT control structure. */ extern ioport_instance_ctrl_t g_ioport_ctrl; -void g_common_init(void); FSP_FOOTER #endif /* COMMON_DATA_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4M1/ra_gen/hal_data.c b/ports/renesas-ra/boards/EK_RA4M1/ra_gen/hal_data.c index cfaa1abd0..19c94dde2 100644 --- a/ports/renesas-ra/boards/EK_RA4M1/ra_gen/hal_data.c +++ b/ports/renesas-ra/boards/EK_RA4M1/ra_gen/hal_data.c @@ -1,52 +1,15 @@ -/* generated HAL source file - do not edit */ #include "hal_data.h" -/* Macros to tie dynamic ELC links to ADC_TRIGGER_SYNC_ELC option in adc_trigger_t. */ -#define ADC_TRIGGER_ADC0 ADC_TRIGGER_SYNC_ELC -#define ADC_TRIGGER_ADC0_B ADC_TRIGGER_SYNC_ELC -#define ADC_TRIGGER_ADC1 ADC_TRIGGER_SYNC_ELC -#define ADC_TRIGGER_ADC1_B ADC_TRIGGER_SYNC_ELC -adc_instance_ctrl_t g_adc0_ctrl; -const adc_extended_cfg_t g_adc0_cfg_extend = -{ .add_average_count = ADC_ADD_OFF, - .clearing = ADC_CLEAR_AFTER_READ_ON, - .trigger_group_b = ADC_TRIGGER_SYNC_ELC, - .double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED, - .adc_vref_control = ADC_VREF_CONTROL_VREFH, }; -const adc_cfg_t g_adc0_cfg = -{ .unit = 0, .mode = ADC_MODE_SINGLE_SCAN, .resolution = ADC_RESOLUTION_14_BIT, .alignment = - (adc_alignment_t)ADC_ALIGNMENT_RIGHT, - .trigger = ADC_TRIGGER_SOFTWARE, .p_callback = NULL, .p_context = NULL, .p_extend = &g_adc0_cfg_extend, - #if defined(VECTOR_NUMBER_ADC0_SCAN_END) - .scan_end_irq = VECTOR_NUMBER_ADC0_SCAN_END, - #else - .scan_end_irq = FSP_INVALID_VECTOR, - #endif - .scan_end_ipl = (BSP_IRQ_DISABLED), - #if defined(VECTOR_NUMBER_ADC0_SCAN_END_B) - .scan_end_b_irq = VECTOR_NUMBER_ADC0_SCAN_END_B, - #else - .scan_end_b_irq = FSP_INVALID_VECTOR, - #endif - .scan_end_b_ipl = (BSP_IRQ_DISABLED), }; -const adc_channel_cfg_t g_adc0_channel_cfg = -{ .scan_mask = 0, - .scan_mask_group_b = 0, - .priority_group_a = ADC_GROUP_A_PRIORITY_OFF, - .add_mask = 0, - .sample_hold_mask = 0, - .sample_hold_states = 24, }; -/* Instance structure to use this module. */ -const adc_instance_t g_adc0 = -{ .p_ctrl = &g_adc0_ctrl, .p_cfg = &g_adc0_cfg, .p_channel_cfg = &g_adc0_channel_cfg, .p_api = &g_adc_on_adc }; lpm_instance_ctrl_t g_lpm0_ctrl; const lpm_cfg_t g_lpm0_cfg = -{ .low_power_mode = LPM_MODE_SLEEP, +{ .low_power_mode = LPM_MODE_SLEEP, .standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM + | (lpm_standby_wake_source_t)0, + #if BSP_FEATURE_LPM_HAS_SNOOZE .snooze_cancel_sources = LPM_SNOOZE_CANCEL_SOURCE_NONE, - .standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM | (lpm_standby_wake_source_t)0, .snooze_request_source = LPM_SNOOZE_REQUEST_RXD0_FALLING, .snooze_end_sources = (lpm_snooze_end_t)0, .dtc_state_in_snooze = LPM_SNOOZE_DTC_DISABLE, + #endif #if BSP_FEATURE_LPM_HAS_SBYCR_OPE .output_port_enable = 0, #endif @@ -56,171 +19,23 @@ const lpm_cfg_t g_lpm0_cfg = .deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0, .deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0, #endif - .p_extend = NULL, }; - -const lpm_instance_t g_lpm0 = -{ .p_api = &g_lpm_on_lpm, .p_ctrl = &g_lpm0_ctrl, .p_cfg = &g_lpm0_cfg }; -dtc_instance_ctrl_t g_transfer1_ctrl; - -transfer_info_t g_transfer1_info = -{ .dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, - .repeat_area = TRANSFER_REPEAT_AREA_DESTINATION, - .irq = TRANSFER_IRQ_END, - .chain_mode = TRANSFER_CHAIN_MODE_DISABLED, - .src_addr_mode = TRANSFER_ADDR_MODE_FIXED, - .size = TRANSFER_SIZE_2_BYTE, - .mode = TRANSFER_MODE_NORMAL, - .p_dest = (void *)NULL, - .p_src = (void const *)NULL, - .num_blocks = 0, - .length = 0, }; -const dtc_extended_cfg_t g_transfer1_cfg_extend = -{ .activation_source = VECTOR_NUMBER_SPI0_RXI, }; -const transfer_cfg_t g_transfer1_cfg = -{ .p_info = &g_transfer1_info, .p_extend = &g_transfer1_cfg_extend, }; - -/* Instance structure to use this module. */ -const transfer_instance_t g_transfer1 = -{ .p_ctrl = &g_transfer1_ctrl, .p_cfg = &g_transfer1_cfg, .p_api = &g_transfer_on_dtc }; -dtc_instance_ctrl_t g_transfer0_ctrl; - -transfer_info_t g_transfer0_info = -{ .dest_addr_mode = TRANSFER_ADDR_MODE_FIXED, - .repeat_area = TRANSFER_REPEAT_AREA_SOURCE, - .irq = TRANSFER_IRQ_END, - .chain_mode = TRANSFER_CHAIN_MODE_DISABLED, - .src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, - .size = TRANSFER_SIZE_2_BYTE, - .mode = TRANSFER_MODE_NORMAL, - .p_dest = (void *)NULL, - .p_src = (void const *)NULL, - .num_blocks = 0, - .length = 0, }; -const dtc_extended_cfg_t g_transfer0_cfg_extend = -{ .activation_source = VECTOR_NUMBER_SPI0_TXI, }; -const transfer_cfg_t g_transfer0_cfg = -{ .p_info = &g_transfer0_info, .p_extend = &g_transfer0_cfg_extend, }; - -/* Instance structure to use this module. */ -const transfer_instance_t g_transfer0 = -{ .p_ctrl = &g_transfer0_ctrl, .p_cfg = &g_transfer0_cfg, .p_api = &g_transfer_on_dtc }; -spi_instance_ctrl_t g_spi0_ctrl; - -/** SPI extended configuration for SPI HAL driver */ -const spi_extended_cfg_t g_spi0_ext_cfg = -{ .spi_clksyn = SPI_SSL_MODE_CLK_SYN, - .spi_comm = SPI_COMMUNICATION_FULL_DUPLEX, - .ssl_polarity = SPI_SSLP_LOW, - .ssl_select = SPI_SSL_SELECT_SSL0, - .mosi_idle = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE, - .parity = SPI_PARITY_MODE_DISABLE, - .byte_swap = SPI_BYTE_SWAP_DISABLE, - .spck_div = - { - /* Actual calculated bitrate: 12000000. */ .spbr = 1, - .brdv = 0 - }, - .spck_delay = SPI_DELAY_COUNT_1, - .ssl_negation_delay = SPI_DELAY_COUNT_1, - .next_access_delay = SPI_DELAY_COUNT_1 }; - -/** SPI configuration for SPI HAL driver */ -const spi_cfg_t g_spi0_cfg = -{ .channel = 0, - - #if defined(VECTOR_NUMBER_SPI0_RXI) - .rxi_irq = VECTOR_NUMBER_SPI0_RXI, - #else - .rxi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SPI0_TXI) - .txi_irq = VECTOR_NUMBER_SPI0_TXI, - #else - .txi_irq = FSP_INVALID_VECTOR, + #if BSP_FEATURE_LPM_HAS_PDRAMSCR + .ram_retention_cfg.ram_retention = (uint8_t)(0), + .ram_retention_cfg.tcm_retention = false, #endif - #if defined(VECTOR_NUMBER_SPI0_TEI) - .tei_irq = VECTOR_NUMBER_SPI0_TEI, - #else - .tei_irq = FSP_INVALID_VECTOR, + #if BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP + .ram_retention_cfg.standby_ram_retention = false, #endif - #if defined(VECTOR_NUMBER_SPI0_ERI) - .eri_irq = VECTOR_NUMBER_SPI0_ERI, - #else - .eri_irq = FSP_INVALID_VECTOR, + #if BSP_FEATURE_LPM_HAS_LDO_CONTROL + .ldo_standby_cfg.pll1_ldo = false, + .ldo_standby_cfg.pll2_ldo = false, + .ldo_standby_cfg.hoco_ldo = false, #endif + .p_extend = NULL, }; - .rxi_ipl = (12), - .txi_ipl = (12), - .tei_ipl = (12), - .eri_ipl = (12), - - .operating_mode = SPI_MODE_MASTER, - - .clk_phase = SPI_CLK_PHASE_EDGE_ODD, - .clk_polarity = SPI_CLK_POLARITY_LOW, - - .mode_fault = SPI_MODE_FAULT_ERROR_DISABLE, - .bit_order = SPI_BIT_ORDER_MSB_FIRST, - .p_transfer_tx = g_spi0_P_TRANSFER_TX, - .p_transfer_rx = g_spi0_P_TRANSFER_RX, - .p_callback = spi_callback, - - .p_context = NULL, - .p_extend = (void *)&g_spi0_ext_cfg, }; +const lpm_instance_t g_lpm0 = +{ .p_api = &g_lpm_on_lpm, .p_ctrl = &g_lpm0_ctrl, .p_cfg = &g_lpm0_cfg }; -/* Instance structure to use this module. */ -const spi_instance_t g_spi0 = -{ .p_ctrl = &g_spi0_ctrl, .p_cfg = &g_spi0_cfg, .p_api = &g_spi_on_spi }; -icu_instance_ctrl_t g_external_irq0_ctrl; -const external_irq_cfg_t g_external_irq0_cfg = -{ .channel = 0, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ0) - .irq = VECTOR_NUMBER_ICU_IRQ0, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq0 = -{ .p_ctrl = &g_external_irq0_ctrl, .p_cfg = &g_external_irq0_cfg, .p_api = &g_external_irq_on_icu }; -agt_instance_ctrl_t g_timer0_ctrl; -const agt_extended_cfg_t g_timer0_extend = -{ .count_source = AGT_CLOCK_PCLKB, - .agto = AGT_PIN_CFG_DISABLED, - .agtoa = AGT_PIN_CFG_DISABLED, - .agtob = AGT_PIN_CFG_DISABLED, - .measurement_mode = AGT_MEASURE_DISABLED, - .agtio_filter = AGT_AGTIO_FILTER_NONE, - .enable_pin = AGT_ENABLE_PIN_NOT_USED, - .trigger_edge = AGT_TRIGGER_EDGE_RISING, }; -const timer_cfg_t g_timer0_cfg = -{ .mode = TIMER_MODE_PERIODIC, -/* Actual period: 0.002730666666666667 seconds. Actual duty: 50%. */ .period_counts = 0x10000, - .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 0, .p_callback = callback_agt, - /** If NULL then do not add & */ - #if defined(NULL) - .p_context = NULL, - #else - .p_context = &NULL, - #endif - .p_extend = &g_timer0_extend, - .cycle_end_ipl = (5), - #if defined(VECTOR_NUMBER_AGT0_INT) - .cycle_end_irq = VECTOR_NUMBER_AGT0_INT, - #else - .cycle_end_irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const timer_instance_t g_timer0 = -{ .p_ctrl = &g_timer0_ctrl, .p_cfg = &g_timer0_cfg, .p_api = &g_timer_on_agt }; flash_lp_instance_ctrl_t g_flash0_ctrl; const flash_cfg_t g_flash0_cfg = { .data_flash_bgo = false, .p_callback = NULL, .p_context = NULL, .ipl = (BSP_IRQ_DISABLED), @@ -233,239 +48,3 @@ const flash_cfg_t g_flash0_cfg = /* Instance structure to use this module. */ const flash_instance_t g_flash0 = { .p_ctrl = &g_flash0_ctrl, .p_cfg = &g_flash0_cfg, .p_api = &g_flash_on_flash_lp }; -rtc_instance_ctrl_t g_rtc0_ctrl; -const rtc_error_adjustment_cfg_t g_rtc0_err_cfg = -{ .adjustment_mode = RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC, - .adjustment_period = RTC_ERROR_ADJUSTMENT_PERIOD_10_SECOND, - .adjustment_type = RTC_ERROR_ADJUSTMENT_NONE, - .adjustment_value = 0, }; -const rtc_cfg_t g_rtc0_cfg = -{ .clock_source = RTC_CLOCK_SOURCE_LOCO, .freq_compare_value_loco = 255, .p_err_cfg = &g_rtc0_err_cfg, .p_callback = - NULL, - .p_context = NULL, .alarm_ipl = (14), .periodic_ipl = (14), .carry_ipl = (14), - #if defined(VECTOR_NUMBER_RTC_ALARM) - .alarm_irq = VECTOR_NUMBER_RTC_ALARM, - #else - .alarm_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_RTC_PERIOD) - .periodic_irq = VECTOR_NUMBER_RTC_PERIOD, - #else - .periodic_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_RTC_CARRY) - .carry_irq = VECTOR_NUMBER_RTC_CARRY, - #else - .carry_irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const rtc_instance_t g_rtc0 = -{ .p_ctrl = &g_rtc0_ctrl, .p_cfg = &g_rtc0_cfg, .p_api = &g_rtc_on_rtc }; -sci_uart_instance_ctrl_t g_uart2_ctrl; - -baud_setting_t g_uart2_baud_setting = -{ -/* Baud rate calculated with 0.160% error. */ .abcse = 0, - .abcs = 0, .bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t)256, .brme = false -}; - -/** UART extended configuration for UARTonSCI HAL driver */ -const sci_uart_extended_cfg_t g_uart2_cfg_extend = -{ .clock = SCI_UART_CLOCK_INT, - .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, - .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, - .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, - .p_baud_setting = &g_uart2_baud_setting, - .uart_mode = UART_MODE_RS232, - .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, - #if 0 - .flow_control_pin = BSP_IO_PORT_00_PIN_00, - #else - .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), - #endif -}; - -/** UART interface configuration */ -const uart_cfg_t g_uart2_cfg = -{ .channel = 2, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = - user_uart_callback, - .p_context = NULL, .p_extend = &g_uart2_cfg_extend, -#define RA_NOT_DEFINED (1) - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_tx = NULL, - #else - .p_transfer_tx = &RA_NOT_DEFINED, - #endif - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_rx = NULL, - #else - .p_transfer_rx = &RA_NOT_DEFINED, - #endif -#undef RA_NOT_DEFINED - .rxi_ipl = (12), - .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), - #if defined(VECTOR_NUMBER_SCI2_RXI) - .rxi_irq = VECTOR_NUMBER_SCI2_RXI, - #else - .rxi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI2_TXI) - .txi_irq = VECTOR_NUMBER_SCI2_TXI, - #else - .txi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI2_TEI) - .tei_irq = VECTOR_NUMBER_SCI2_TEI, - #else - .tei_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI2_ERI) - .eri_irq = VECTOR_NUMBER_SCI2_ERI, - #else - .eri_irq = FSP_INVALID_VECTOR, - #endif -}; - -/* Instance structure to use this module. */ -const uart_instance_t g_uart2 = -{ .p_ctrl = &g_uart2_ctrl, .p_cfg = &g_uart2_cfg, .p_api = &g_uart_on_sci }; -sci_uart_instance_ctrl_t g_uart1_ctrl; - -baud_setting_t g_uart1_baud_setting = -{ -/* Baud rate calculated with 0.160% error. */ .abcse = 0, - .abcs = 0, .bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t)256, .brme = false -}; - -/** UART extended configuration for UARTonSCI HAL driver */ -const sci_uart_extended_cfg_t g_uart1_cfg_extend = -{ .clock = SCI_UART_CLOCK_INT, - .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, - .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, - .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, - .p_baud_setting = &g_uart1_baud_setting, - .uart_mode = UART_MODE_RS232, - .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, - #if 0 - .flow_control_pin = BSP_IO_PORT_00_PIN_00, - #else - .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), - #endif -}; - -/** UART interface configuration */ -const uart_cfg_t g_uart1_cfg = -{ .channel = 1, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = - user_uart_callback, - .p_context = NULL, .p_extend = &g_uart1_cfg_extend, -#define RA_NOT_DEFINED (1) - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_tx = NULL, - #else - .p_transfer_tx = &RA_NOT_DEFINED, - #endif - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_rx = NULL, - #else - .p_transfer_rx = &RA_NOT_DEFINED, - #endif -#undef RA_NOT_DEFINED - .rxi_ipl = (12), - .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), - #if defined(VECTOR_NUMBER_SCI1_RXI) - .rxi_irq = VECTOR_NUMBER_SCI1_RXI, - #else - .rxi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI1_TXI) - .txi_irq = VECTOR_NUMBER_SCI1_TXI, - #else - .txi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI1_TEI) - .tei_irq = VECTOR_NUMBER_SCI1_TEI, - #else - .tei_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI1_ERI) - .eri_irq = VECTOR_NUMBER_SCI1_ERI, - #else - .eri_irq = FSP_INVALID_VECTOR, - #endif -}; - -/* Instance structure to use this module. */ -const uart_instance_t g_uart1 = -{ .p_ctrl = &g_uart1_ctrl, .p_cfg = &g_uart1_cfg, .p_api = &g_uart_on_sci }; -sci_uart_instance_ctrl_t g_uart0_ctrl; - -baud_setting_t g_uart0_baud_setting = -{ -/* Baud rate calculated with 0.160% error. */ .abcse = 0, - .abcs = 0, .bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t)256, .brme = false -}; - -/** UART extended configuration for UARTonSCI HAL driver */ -const sci_uart_extended_cfg_t g_uart0_cfg_extend = -{ .clock = SCI_UART_CLOCK_INT, - .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, - .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, - .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, - .p_baud_setting = &g_uart0_baud_setting, - .uart_mode = UART_MODE_RS232, - .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, - #if 0 - .flow_control_pin = BSP_IO_PORT_00_PIN_00, - #else - .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), - #endif -}; - -/** UART interface configuration */ -const uart_cfg_t g_uart0_cfg = -{ .channel = 0, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = - user_uart_callback, - .p_context = NULL, .p_extend = &g_uart0_cfg_extend, -#define RA_NOT_DEFINED (1) - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_tx = NULL, - #else - .p_transfer_tx = &RA_NOT_DEFINED, - #endif - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_rx = NULL, - #else - .p_transfer_rx = &RA_NOT_DEFINED, - #endif -#undef RA_NOT_DEFINED - .rxi_ipl = (12), - .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), - #if defined(VECTOR_NUMBER_SCI0_RXI) - .rxi_irq = VECTOR_NUMBER_SCI0_RXI, - #else - .rxi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI0_TXI) - .txi_irq = VECTOR_NUMBER_SCI0_TXI, - #else - .txi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI0_TEI) - .tei_irq = VECTOR_NUMBER_SCI0_TEI, - #else - .tei_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI0_ERI) - .eri_irq = VECTOR_NUMBER_SCI0_ERI, - #else - .eri_irq = FSP_INVALID_VECTOR, - #endif -}; - -/* Instance structure to use this module. */ -const uart_instance_t g_uart0 = -{ .p_ctrl = &g_uart0_ctrl, .p_cfg = &g_uart0_cfg, .p_api = &g_uart_on_sci }; -void g_hal_init(void) { - g_common_init(); -} diff --git a/ports/renesas-ra/boards/EK_RA4M1/ra_gen/hal_data.h b/ports/renesas-ra/boards/EK_RA4M1/ra_gen/hal_data.h index 4120a4803..7b1e505f6 100644 --- a/ports/renesas-ra/boards/EK_RA4M1/ra_gen/hal_data.h +++ b/ports/renesas-ra/boards/EK_RA4M1/ra_gen/hal_data.h @@ -2,99 +2,20 @@ #ifndef HAL_DATA_H_ #define HAL_DATA_H_ #include <stdint.h> -#include "bsp_api.h" #include "common_data.h" -#include "r_adc.h" -#include "r_adc_api.h" #include "r_lpm.h" #include "r_lpm_api.h" -#include "r_dtc.h" -#include "r_transfer_api.h" -#include "r_spi.h" -#include "r_icu.h" -#include "r_external_irq_api.h" -#include "r_agt.h" -#include "r_timer_api.h" #include "r_flash_lp.h" #include "r_flash_api.h" -#include "r_rtc.h" -#include "r_rtc_api.h" -#include "r_sci_uart.h" -#include "r_uart_api.h" FSP_HEADER -/** ADC on ADC Instance. */ -extern const adc_instance_t g_adc0; -/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */ -extern adc_instance_ctrl_t g_adc0_ctrl; -extern const adc_cfg_t g_adc0_cfg; -extern const adc_channel_cfg_t g_adc0_channel_cfg; - -#ifndef NULL -void NULL(adc_callback_args_t *p_args); -#endif /** lpm Instance */ extern const lpm_instance_t g_lpm0; /** Access the LPM instance using these structures when calling API functions directly (::p_api is not used). */ extern lpm_instance_ctrl_t g_lpm0_ctrl; extern const lpm_cfg_t g_lpm0_cfg; -/* Transfer on DTC Instance. */ -extern const transfer_instance_t g_transfer1; - -/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ -extern dtc_instance_ctrl_t g_transfer1_ctrl; -extern const transfer_cfg_t g_transfer1_cfg; -/* Transfer on DTC Instance. */ -extern const transfer_instance_t g_transfer0; - -/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ -extern dtc_instance_ctrl_t g_transfer0_ctrl; -extern const transfer_cfg_t g_transfer0_cfg; -/** SPI on SPI Instance. */ -extern const spi_instance_t g_spi0; - -/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */ -extern spi_instance_ctrl_t g_spi0_ctrl; -extern const spi_cfg_t g_spi0_cfg; - -/** Callback used by SPI Instance. */ -#ifndef spi_callback -void spi_callback(spi_callback_args_t *p_args); -#endif - -#define RA_NOT_DEFINED (1) -#if (RA_NOT_DEFINED == g_transfer0) - #define g_spi0_P_TRANSFER_TX (NULL) -#else -#define g_spi0_P_TRANSFER_TX (&g_transfer0) -#endif -#if (RA_NOT_DEFINED == g_transfer1) - #define g_spi0_P_TRANSFER_RX (NULL) -#else -#define g_spi0_P_TRANSFER_RX (&g_transfer1) -#endif -#undef RA_NOT_DEFINED -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq0; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq0_ctrl; -extern const external_irq_cfg_t g_external_irq0_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** AGT Timer Instance */ -extern const timer_instance_t g_timer0; - -/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ -extern agt_instance_ctrl_t g_timer0_ctrl; -extern const timer_cfg_t g_timer0_cfg; -#ifndef callback_agt -void callback_agt(timer_callback_args_t *p_args); -#endif /* Flash on Flash LP Instance. */ extern const flash_instance_t g_flash0; @@ -105,50 +26,8 @@ extern const flash_cfg_t g_flash0_cfg; #ifndef NULL void NULL(flash_callback_args_t *p_args); #endif -/* RTC Instance. */ -extern const rtc_instance_t g_rtc0; - -/** Access the RTC instance using these structures when calling API functions directly (::p_api is not used). */ -extern rtc_instance_ctrl_t g_rtc0_ctrl; -extern const rtc_cfg_t g_rtc0_cfg; - -#ifndef NULL -void NULL(rtc_callback_args_t *p_args); -#endif -/** UART on SCI Instance. */ -extern const uart_instance_t g_uart2; - -/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ -extern sci_uart_instance_ctrl_t g_uart2_ctrl; -extern const uart_cfg_t g_uart2_cfg; -extern const sci_uart_extended_cfg_t g_uart2_cfg_extend; - -#ifndef user_uart_callback -void user_uart_callback(uart_callback_args_t *p_args); -#endif -/** UART on SCI Instance. */ -extern const uart_instance_t g_uart1; - -/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ -extern sci_uart_instance_ctrl_t g_uart1_ctrl; -extern const uart_cfg_t g_uart1_cfg; -extern const sci_uart_extended_cfg_t g_uart1_cfg_extend; - -#ifndef user_uart_callback -void user_uart_callback(uart_callback_args_t *p_args); -#endif -/** UART on SCI Instance. */ -extern const uart_instance_t g_uart0; -/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ -extern sci_uart_instance_ctrl_t g_uart0_ctrl; -extern const uart_cfg_t g_uart0_cfg; -extern const sci_uart_extended_cfg_t g_uart0_cfg_extend; - -#ifndef user_uart_callback -void user_uart_callback(uart_callback_args_t *p_args); -#endif void hal_entry(void); -void g_hal_init(void); + FSP_FOOTER #endif /* HAL_DATA_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4M1/ra_gen/pin_data.c b/ports/renesas-ra/boards/EK_RA4M1/ra_gen/pin_data.c index bc928d63f..93eb2ae0d 100644 --- a/ports/renesas-ra/boards/EK_RA4M1/ra_gen/pin_data.c +++ b/ports/renesas-ra/boards/EK_RA4M1/ra_gen/pin_data.c @@ -1,105 +1,91 @@ /* generated pin source file - do not edit */ #include "bsp_api.h" #include "r_ioport_api.h" -const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { - { - .pin = BSP_IO_PORT_00_PIN_00, - .pin_cfg = ((uint32_t)IOPORT_CFG_ANALOG_ENABLE), - }, - { - .pin = BSP_IO_PORT_01_PIN_00, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), - }, - { - .pin = BSP_IO_PORT_01_PIN_01, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), - }, - { - .pin = BSP_IO_PORT_01_PIN_02, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), - }, - { - .pin = BSP_IO_PORT_01_PIN_03, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), - }, - { - .pin = BSP_IO_PORT_01_PIN_05, - .pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT), - }, - { - .pin = BSP_IO_PORT_01_PIN_06, - .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW), - }, - { - .pin = BSP_IO_PORT_01_PIN_08, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), - }, - { - .pin = BSP_IO_PORT_01_PIN_09, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), - }, - { - .pin = BSP_IO_PORT_01_PIN_10, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), - }, - { - .pin = BSP_IO_PORT_01_PIN_15, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_CTSU), - }, - { - .pin = BSP_IO_PORT_02_PIN_05, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_CTSU), - }, - { - .pin = BSP_IO_PORT_03_PIN_00, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), - }, - { - .pin = BSP_IO_PORT_03_PIN_01, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), - }, - { - .pin = BSP_IO_PORT_03_PIN_02, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), - }, - { - .pin = BSP_IO_PORT_04_PIN_00, - .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW), - }, - { - .pin = BSP_IO_PORT_04_PIN_01, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9), - }, - { - .pin = BSP_IO_PORT_04_PIN_02, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9), - }, - { - .pin = BSP_IO_PORT_04_PIN_03, - .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW), - }, - { - .pin = BSP_IO_PORT_04_PIN_07, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_USB_FS), - }, - { - .pin = BSP_IO_PORT_04_PIN_10, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), - }, - { - .pin = BSP_IO_PORT_04_PIN_11, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), - }, - { - .pin = BSP_IO_PORT_09_PIN_14, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_USB_FS), - }, - { - .pin = BSP_IO_PORT_09_PIN_15, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_USB_FS), - }, -}; -const ioport_cfg_t g_bsp_pin_cfg = { - .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), - .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = +{ + { .pin = BSP_IO_PORT_00_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_ANALOG_ENABLE) }, + { .pin = BSP_IO_PORT_01_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SPI) }, + { .pin = BSP_IO_PORT_01_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SPI) }, + { .pin = BSP_IO_PORT_01_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SPI) }, + { .pin = BSP_IO_PORT_01_PIN_03, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SPI) }, + { .pin = BSP_IO_PORT_01_PIN_05, .pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE + | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT) }, + { .pin = BSP_IO_PORT_01_PIN_06, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT + | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) }, + { .pin = BSP_IO_PORT_01_PIN_08, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_DEBUG) }, + { .pin = BSP_IO_PORT_01_PIN_09, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_DEBUG) }, + { .pin = BSP_IO_PORT_01_PIN_10, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_DEBUG) }, + { .pin = BSP_IO_PORT_01_PIN_15, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_CTSU) }, + { .pin = BSP_IO_PORT_02_PIN_05, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_CTSU) }, + { .pin = BSP_IO_PORT_03_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_DEBUG) }, + { .pin = BSP_IO_PORT_03_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) }, + { .pin = BSP_IO_PORT_03_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) }, + { .pin = BSP_IO_PORT_04_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT + | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) }, + { .pin = BSP_IO_PORT_04_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, + { .pin = BSP_IO_PORT_04_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, + { .pin = BSP_IO_PORT_04_PIN_03, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT + | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) }, + { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_USB_FS) }, + { .pin = BSP_IO_PORT_04_PIN_10, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) }, + { .pin = BSP_IO_PORT_04_PIN_11, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) }, + { .pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_USB_FS) }, + { .pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_USB_FS) }, }; + +const ioport_cfg_t g_bsp_pin_cfg = +{ .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], }; + +#if BSP_TZ_SECURE_BUILD + +void R_BSP_PinCfgSecurityInit(void); + +/* Initialize SAR registers for secure pins. */ +void R_BSP_PinCfgSecurityInit(void) { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #else + uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #endif + memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0])); + + + for (uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++) + { + uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin; + uint32_t port = port_pin >> 8U; + uint32_t pin = port_pin & 0xFFU; + pmsar[port] &= (uint16_t) ~(1U << pin); + } + + for (uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + R_PMISC->PMSAR[i].PMSAR = (uint16_t)pmsar[i]; + #else + R_PMISC->PMSAR[i].PMSAR = pmsar[i]; + #endif + } + +} +#endif diff --git a/ports/renesas-ra/boards/EK_RA4M1/ra_gen/vector_data.c b/ports/renesas-ra/boards/EK_RA4M1/ra_gen/vector_data.c index a5f0092a5..d2aafa6e7 100644 --- a/ports/renesas-ra/boards/EK_RA4M1/ra_gen/vector_data.c +++ b/ports/renesas-ra/boards/EK_RA4M1/ra_gen/vector_data.c @@ -4,7 +4,7 @@ #if VECTOR_DATA_IRQ_COUNT > 0 BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = { - [0] = sci_uart_rxi_isr, /* SCI0 RXI (Receive data full) */ + [0] = sci_uart_rxi_isr, /* SCI0 RXI (Receive data full) */ [1] = sci_uart_txi_isr, /* SCI0 TXI (Transmit data empty) */ [2] = sci_uart_tei_isr, /* SCI0 TEI (Transmit end) */ [3] = sci_uart_eri_isr, /* SCI0 ERI (Receive error) */ @@ -14,17 +14,17 @@ BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BS [7] = sci_uart_eri_isr, /* SCI1 ERI (Receive error) */ [8] = sci_uart_rxi_isr, /* SCI2 RXI (Received data full) */ [9] = sci_uart_txi_isr, /* SCI2 TXI (Transmit data empty) */ - [10] = sci_uart_tei_isr, /* SCI2 TEI (Transmit end) */ - [11] = sci_uart_eri_isr, /* SCI2 ERI (Receive error) */ - [12] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */ - [13] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */ - [14] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */ - [15] = agt_int_isr, /* AGT0 INT (AGT interrupt) */ - [16] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */ - [17] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */ - [18] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */ - [19] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */ - [20] = spi_eri_isr, /* SPI0 ERI (Error) */ + [10] = sci_uart_tei_isr, /* SCI2 TEI (Transmit end) */ + [11] = sci_uart_eri_isr, /* SCI2 ERI (Receive error) */ + [12] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */ + [13] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */ + [14] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */ + [15] = agt_int_isr, /* AGT0 INT (AGT interrupt) */ + [16] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */ + [17] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */ + [18] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */ + [19] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */ + [20] = spi_eri_isr, /* SPI0 ERI (Error) */ }; const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = { @@ -38,16 +38,16 @@ const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENT [7] = BSP_PRV_IELS_ENUM(EVENT_SCI1_ERI), /* SCI1 ERI (Receive error) */ [8] = BSP_PRV_IELS_ENUM(EVENT_SCI2_RXI), /* SCI2 RXI (Received data full) */ [9] = BSP_PRV_IELS_ENUM(EVENT_SCI2_TXI), /* SCI2 TXI (Transmit data empty) */ - [10] = BSP_PRV_IELS_ENUM(EVENT_SCI2_TEI), /* SCI2 TEI (Transmit end) */ - [11] = BSP_PRV_IELS_ENUM(EVENT_SCI2_ERI), /* SCI2 ERI (Receive error) */ - [12] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */ - [13] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */ - [14] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */ - [15] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */ - [16] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ0), /* ICU IRQ0 (External pin interrupt 0) */ - [17] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */ - [18] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */ - [19] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */ - [20] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */ + [10] = BSP_PRV_IELS_ENUM(EVENT_SCI2_TEI), /* SCI2 TEI (Transmit end) */ + [11] = BSP_PRV_IELS_ENUM(EVENT_SCI2_ERI), /* SCI2 ERI (Receive error) */ + [12] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */ + [13] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */ + [14] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */ + [15] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */ + [16] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ0), /* ICU IRQ0 (External pin interrupt 0) */ + [17] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */ + [18] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */ + [19] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */ + [20] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */ }; #endif diff --git a/ports/renesas-ra/boards/EK_RA4M1/ra_gen/vector_data.h b/ports/renesas-ra/boards/EK_RA4M1/ra_gen/vector_data.h index 1e23b674c..068f001b8 100644 --- a/ports/renesas-ra/boards/EK_RA4M1/ra_gen/vector_data.h +++ b/ports/renesas-ra/boards/EK_RA4M1/ra_gen/vector_data.h @@ -1,6 +1,9 @@ /* generated vector header file - do not edit */ #ifndef VECTOR_DATA_H #define VECTOR_DATA_H +#ifdef __cplusplus +extern "C" { +#endif /* Number of interrupts allocated */ #ifndef VECTOR_DATA_IRQ_COUNT #define VECTOR_DATA_IRQ_COUNT (21) @@ -21,59 +24,48 @@ void spi_eri_isr(void); /* Vector table allocations */ #define VECTOR_NUMBER_SCI0_RXI ((IRQn_Type)0) /* SCI0 RXI (Receive data full) */ +#define SCI0_RXI_IRQn ((IRQn_Type)0) /* SCI0 RXI (Receive data full) */ #define VECTOR_NUMBER_SCI0_TXI ((IRQn_Type)1) /* SCI0 TXI (Transmit data empty) */ +#define SCI0_TXI_IRQn ((IRQn_Type)1) /* SCI0 TXI (Transmit data empty) */ #define VECTOR_NUMBER_SCI0_TEI ((IRQn_Type)2) /* SCI0 TEI (Transmit end) */ +#define SCI0_TEI_IRQn ((IRQn_Type)2) /* SCI0 TEI (Transmit end) */ #define VECTOR_NUMBER_SCI0_ERI ((IRQn_Type)3) /* SCI0 ERI (Receive error) */ +#define SCI0_ERI_IRQn ((IRQn_Type)3) /* SCI0 ERI (Receive error) */ #define VECTOR_NUMBER_SCI1_RXI ((IRQn_Type)4) /* SCI1 RXI (Received data full) */ +#define SCI1_RXI_IRQn ((IRQn_Type)4) /* SCI1 RXI (Received data full) */ #define VECTOR_NUMBER_SCI1_TXI ((IRQn_Type)5) /* SCI1 TXI (Transmit data empty) */ +#define SCI1_TXI_IRQn ((IRQn_Type)5) /* SCI1 TXI (Transmit data empty) */ #define VECTOR_NUMBER_SCI1_TEI ((IRQn_Type)6) /* SCI1 TEI (Transmit end) */ +#define SCI1_TEI_IRQn ((IRQn_Type)6) /* SCI1 TEI (Transmit end) */ #define VECTOR_NUMBER_SCI1_ERI ((IRQn_Type)7) /* SCI1 ERI (Receive error) */ +#define SCI1_ERI_IRQn ((IRQn_Type)7) /* SCI1 ERI (Receive error) */ #define VECTOR_NUMBER_SCI2_RXI ((IRQn_Type)8) /* SCI2 RXI (Received data full) */ +#define SCI2_RXI_IRQn ((IRQn_Type)8) /* SCI2 RXI (Received data full) */ #define VECTOR_NUMBER_SCI2_TXI ((IRQn_Type)9) /* SCI2 TXI (Transmit data empty) */ +#define SCI2_TXI_IRQn ((IRQn_Type)9) /* SCI2 TXI (Transmit data empty) */ #define VECTOR_NUMBER_SCI2_TEI ((IRQn_Type)10) /* SCI2 TEI (Transmit end) */ +#define SCI2_TEI_IRQn ((IRQn_Type)10) /* SCI2 TEI (Transmit end) */ #define VECTOR_NUMBER_SCI2_ERI ((IRQn_Type)11) /* SCI2 ERI (Receive error) */ +#define SCI2_ERI_IRQn ((IRQn_Type)11) /* SCI2 ERI (Receive error) */ #define VECTOR_NUMBER_RTC_ALARM ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */ +#define RTC_ALARM_IRQn ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */ #define VECTOR_NUMBER_RTC_PERIOD ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */ +#define RTC_PERIOD_IRQn ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */ #define VECTOR_NUMBER_RTC_CARRY ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */ +#define RTC_CARRY_IRQn ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */ #define VECTOR_NUMBER_AGT0_INT ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */ +#define AGT0_INT_IRQn ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */ #define VECTOR_NUMBER_ICU_IRQ0 ((IRQn_Type)16) /* ICU IRQ0 (External pin interrupt 0) */ +#define ICU_IRQ0_IRQn ((IRQn_Type)16) /* ICU IRQ0 (External pin interrupt 0) */ #define VECTOR_NUMBER_SPI0_RXI ((IRQn_Type)17) /* SPI0 RXI (Receive buffer full) */ +#define SPI0_RXI_IRQn ((IRQn_Type)17) /* SPI0 RXI (Receive buffer full) */ #define VECTOR_NUMBER_SPI0_TXI ((IRQn_Type)18) /* SPI0 TXI (Transmit buffer empty) */ +#define SPI0_TXI_IRQn ((IRQn_Type)18) /* SPI0 TXI (Transmit buffer empty) */ #define VECTOR_NUMBER_SPI0_TEI ((IRQn_Type)19) /* SPI0 TEI (Transmission complete event) */ +#define SPI0_TEI_IRQn ((IRQn_Type)19) /* SPI0 TEI (Transmission complete event) */ #define VECTOR_NUMBER_SPI0_ERI ((IRQn_Type)20) /* SPI0 ERI (Error) */ -typedef enum IRQn -{ - Reset_IRQn = -15, - NonMaskableInt_IRQn = -14, - HardFault_IRQn = -13, - MemoryManagement_IRQn = -12, - BusFault_IRQn = -11, - UsageFault_IRQn = -10, - SecureFault_IRQn = -9, - SVCall_IRQn = -5, - DebugMonitor_IRQn = -4, - PendSV_IRQn = -2, - SysTick_IRQn = -1, - SCI0_RXI_IRQn = 0, /* SCI0 RXI (Receive data full) */ - SCI0_TXI_IRQn = 1, /* SCI0 TXI (Transmit data empty) */ - SCI0_TEI_IRQn = 2, /* SCI0 TEI (Transmit end) */ - SCI0_ERI_IRQn = 3, /* SCI0 ERI (Receive error) */ - SCI1_RXI_IRQn = 4, /* SCI1 RXI (Received data full) */ - SCI1_TXI_IRQn = 5, /* SCI1 TXI (Transmit data empty) */ - SCI1_TEI_IRQn = 6, /* SCI1 TEI (Transmit end) */ - SCI1_ERI_IRQn = 7, /* SCI1 ERI (Receive error) */ - SCI2_RXI_IRQn = 8, /* SCI2 RXI (Received data full) */ - SCI2_TXI_IRQn = 9, /* SCI2 TXI (Transmit data empty) */ - SCI2_TEI_IRQn = 10, /* SCI2 TEI (Transmit end) */ - SCI2_ERI_IRQn = 11, /* SCI2 ERI (Receive error) */ - RTC_ALARM_IRQn = 12, /* RTC ALARM (Alarm interrupt) */ - RTC_PERIOD_IRQn = 13, /* RTC PERIOD (Periodic interrupt) */ - RTC_CARRY_IRQn = 14, /* RTC CARRY (Carry interrupt) */ - AGT0_INT_IRQn = 15, /* AGT0 INT (AGT interrupt) */ - ICU_IRQ0_IRQn = 16, /* ICU IRQ0 (External pin interrupt 0) */ - SPI0_RXI_IRQn = 17, /* SPI0 RXI (Receive buffer full) */ - SPI0_TXI_IRQn = 18, /* SPI0 TXI (Transmit buffer empty) */ - SPI0_TEI_IRQn = 19, /* SPI0 TEI (Transmission complete event) */ - SPI0_ERI_IRQn = 20, /* SPI0 ERI (Error) */ -} IRQn_Type; +#define SPI0_ERI_IRQn ((IRQn_Type)20) /* SPI0 ERI (Error) */ +#ifdef __cplusplus +} +#endif #endif /* VECTOR_DATA_H */ diff --git a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/bsp/bsp_cfg.h index 9ebcbf977..d6d8e7df3 100644 --- a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/bsp/bsp_cfg.h +++ b/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -1,6 +1,10 @@ /* generated configuration header file - do not edit */ #ifndef BSP_CFG_H_ #define BSP_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #include "bsp_clock_cfg.h" #include "bsp_mcu_family_cfg.h" #include "board_cfg.h" @@ -14,7 +18,13 @@ #define BSP_CFG_RTOS (0) #endif #endif +#ifndef BSP_CFG_RTC_USED +#define BSP_CFG_RTC_USED (1) +#endif #undef RA_NOT_DEFINED +#if defined(_RA_BOOT_IMAGE) +#define BSP_CFG_BOOT_IMAGE (1) +#endif #define BSP_CFG_MCU_VCC_MV (3300) #define BSP_CFG_STACK_MAIN_BYTES (0x4000) #define BSP_CFG_HEAP_BYTES (0xf000) @@ -25,15 +35,14 @@ #define BSP_CFG_PFS_PROTECT ((1)) #define BSP_CFG_C_RUNTIME_INIT ((1)) +#define BSP_CFG_EARLY_INIT ((0)) -#define BSP_CFG_SOFT_RESET_SUPPORTED ((0)) +#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (0) #endif -#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) -#endif + #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) #endif @@ -46,4 +55,8 @@ #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 #endif + +#ifdef __cplusplus +} +#endif #endif /* BSP_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h index 70984c8ef..3795df650 100644 --- a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h +++ b/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -2,6 +2,7 @@ #ifndef BSP_MCU_DEVICE_PN_CFG_H_ #define BSP_MCU_DEVICE_PN_CFG_H_ #define BSP_MCU_R7FA4W1AD2CNG +#define BSP_MCU_FEATURE_SET ('A') #define BSP_ROM_SIZE_BYTES (524288) #define BSP_RAM_SIZE_BYTES (98304) #define BSP_DATA_FLASH_SIZE_BYTES (8192) diff --git a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h index fd26bb64e..7ea92f74b 100644 --- a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ b/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -1,6 +1,10 @@ /* generated configuration header file - do not edit */ #ifndef BSP_MCU_FAMILY_CFG_H_ #define BSP_MCU_FAMILY_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #include "bsp_mcu_device_pn_cfg.h" #include "bsp_mcu_device_cfg.h" #include "../../../ra/fsp/src/bsp/mcu/ra4w1/bsp_mcu_info.h" @@ -22,7 +26,6 @@ #endif #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) #define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) -#define BSP_MCU_VBATT_SUPPORT (1) #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) @@ -50,7 +53,9 @@ #define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) #define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) #define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) - +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ #define BSP_PRV_IELS_ENUM(vector) (ELC_##vector) @@ -71,4 +76,8 @@ #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) #endif + +#ifdef __cplusplus +} +#endif #endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_adc_cfg.h b/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_adc_cfg.h index 9c59889ca..be8a42720 100644 --- a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_adc_cfg.h +++ b/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_adc_cfg.h @@ -1,5 +1,13 @@ /* generated configuration header file - do not edit */ #ifndef R_ADC_CFG_H_ #define R_ADC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #define ADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif #endif /* R_ADC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_agt_cfg.h b/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_agt_cfg.h deleted file mode 100644 index d3ab55923..000000000 --- a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_agt_cfg.h +++ /dev/null @@ -1,7 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_AGT_CFG_H_ -#define R_AGT_CFG_H_ -#define AGT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#define AGT_CFG_OUTPUT_SUPPORT_ENABLE (0) -#define AGT_CFG_INPUT_SUPPORT_ENABLE (0) -#endif /* R_AGT_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_dtc_cfg.h b/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_dtc_cfg.h deleted file mode 100644 index 21405f967..000000000 --- a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_dtc_cfg.h +++ /dev/null @@ -1,6 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_DTC_CFG_H_ -#define R_DTC_CFG_H_ -#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#define DTC_CFG_VECTOR_TABLE_SECTION_NAME ".fsp_dtc_vector_table" -#endif /* R_DTC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_flash_lp_cfg.h b/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_flash_lp_cfg.h index 26879f9f4..7f285cace 100644 --- a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_flash_lp_cfg.h +++ b/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_flash_lp_cfg.h @@ -1,7 +1,15 @@ /* generated configuration header file - do not edit */ #ifndef R_FLASH_LP_CFG_H_ #define R_FLASH_LP_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #define FLASH_LP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) #define FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (1) #define FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (0) + +#ifdef __cplusplus +} +#endif #endif /* R_FLASH_LP_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_icu_cfg.h b/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_icu_cfg.h deleted file mode 100644 index 5e77b6980..000000000 --- a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_icu_cfg.h +++ /dev/null @@ -1,5 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_ICU_CFG_H_ -#define R_ICU_CFG_H_ -#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#endif /* R_ICU_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_iic_master_cfg.h b/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_iic_master_cfg.h deleted file mode 100644 index 595ea938d..000000000 --- a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_iic_master_cfg.h +++ /dev/null @@ -1,7 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_IIC_MASTER_CFG_H_ -#define R_IIC_MASTER_CFG_H_ -#define IIC_MASTER_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#define IIC_MASTER_CFG_DTC_ENABLE (0) -#define IIC_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE (0) -#endif /* R_IIC_MASTER_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_ioport_cfg.h b/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_ioport_cfg.h index 6b4353d23..d2688bf5b 100644 --- a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_ioport_cfg.h +++ b/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -1,5 +1,13 @@ /* generated configuration header file - do not edit */ #ifndef R_IOPORT_CFG_H_ #define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif #endif /* R_IOPORT_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_lpm_cfg.h b/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_lpm_cfg.h index 5f4d5c4a7..6712eee6a 100644 --- a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_lpm_cfg.h +++ b/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_lpm_cfg.h @@ -1,5 +1,14 @@ /* generated configuration header file - do not edit */ #ifndef R_LPM_CFG_H_ #define R_LPM_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #define LPM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define LPM_CFG_STANDBY_LIMIT (0) + +#ifdef __cplusplus +} +#endif #endif /* R_LPM_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_rtc_cfg.h b/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_rtc_cfg.h deleted file mode 100644 index 484b7ed04..000000000 --- a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_rtc_cfg.h +++ /dev/null @@ -1,5 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_RTC_CFG_H_ -#define R_RTC_CFG_H_ -#define RTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#endif /* R_RTC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_sci_uart_cfg.h b/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_sci_uart_cfg.h deleted file mode 100644 index c70c0be34..000000000 --- a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_sci_uart_cfg.h +++ /dev/null @@ -1,8 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_SCI_UART_CFG_H_ -#define R_SCI_UART_CFG_H_ -#define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#define SCI_UART_CFG_FIFO_SUPPORT (0) -#define SCI_UART_CFG_DTC_SUPPORTED (0) -#define SCI_UART_CFG_FLOW_CONTROL_SUPPORT (0) -#endif /* R_SCI_UART_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_spi_cfg.h b/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_spi_cfg.h deleted file mode 100644 index 861fe1219..000000000 --- a/ports/renesas-ra/boards/EK_RA4W1/ra_cfg/fsp_cfg/r_spi_cfg.h +++ /dev/null @@ -1,7 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_SPI_CFG_H_ -#define R_SPI_CFG_H_ -#define SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#define SPI_DTC_SUPPORT_ENABLE (1) -#define SPI_TRANSMIT_FROM_RXI_ISR (0) -#endif /* R_SPI_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4W1/ra_gen/bsp_clock_cfg.h b/ports/renesas-ra/boards/EK_RA4W1/ra_gen/bsp_clock_cfg.h index 9432ad009..4669c98c4 100644 --- a/ports/renesas-ra/boards/EK_RA4W1/ra_gen/bsp_clock_cfg.h +++ b/ports/renesas-ra/boards/EK_RA4W1/ra_gen/bsp_clock_cfg.h @@ -7,15 +7,13 @@ #define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ #define BSP_CFG_HOCO_FREQUENCY (4) /* HOCO 48MHz */ #define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */ -#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL_12_0) /* PLL Mul x12 */ +#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(12U, 0U)) /* PLL Mul x12 */ #define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* Clock Src: HOCO */ #define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */ #define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */ #define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */ #define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */ -#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ -#define BSP_CFG_BCLK_OUTPUT (2) /* BCK/2 */ #define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */ #define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ #define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ diff --git a/ports/renesas-ra/boards/EK_RA4W1/ra_gen/common_data.c b/ports/renesas-ra/boards/EK_RA4W1/ra_gen/common_data.c index 34aad762f..fb539ac4a 100644 --- a/ports/renesas-ra/boards/EK_RA4W1/ra_gen/common_data.c +++ b/ports/renesas-ra/boards/EK_RA4W1/ra_gen/common_data.c @@ -3,5 +3,3 @@ ioport_instance_ctrl_t g_ioport_ctrl; const ioport_instance_t g_ioport = { .p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg, }; -void g_common_init(void) { -} diff --git a/ports/renesas-ra/boards/EK_RA4W1/ra_gen/common_data.h b/ports/renesas-ra/boards/EK_RA4W1/ra_gen/common_data.h index e2eb70836..5c61c7636 100644 --- a/ports/renesas-ra/boards/EK_RA4W1/ra_gen/common_data.h +++ b/ports/renesas-ra/boards/EK_RA4W1/ra_gen/common_data.h @@ -5,12 +5,15 @@ #include "bsp_api.h" #include "r_ioport.h" #include "bsp_pin_cfg.h" +#include "r_icu.h" +#include "r_external_irq_api.h" FSP_HEADER + /* IOPORT Instance */ extern const ioport_instance_t g_ioport; /* IOPORT control structure. */ extern ioport_instance_ctrl_t g_ioport_ctrl; -void g_common_init(void); + FSP_FOOTER #endif /* COMMON_DATA_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4W1/ra_gen/hal_data.c b/ports/renesas-ra/boards/EK_RA4W1/ra_gen/hal_data.c index 8e7ee1bd4..af7f3ebd4 100644 --- a/ports/renesas-ra/boards/EK_RA4W1/ra_gen/hal_data.c +++ b/ports/renesas-ra/boards/EK_RA4W1/ra_gen/hal_data.c @@ -1,98 +1,15 @@ -/* generated HAL source file - do not edit */ #include "hal_data.h" -/* Macros to tie dynamic ELC links to ADC_TRIGGER_SYNC_ELC option in adc_trigger_t. */ -#define ADC_TRIGGER_ADC0 ADC_TRIGGER_SYNC_ELC -#define ADC_TRIGGER_ADC0_B ADC_TRIGGER_SYNC_ELC -#define ADC_TRIGGER_ADC1 ADC_TRIGGER_SYNC_ELC -#define ADC_TRIGGER_ADC1_B ADC_TRIGGER_SYNC_ELC -adc_instance_ctrl_t g_adc0_ctrl; -const adc_extended_cfg_t g_adc0_cfg_extend = -{ .add_average_count = ADC_ADD_OFF, - .clearing = ADC_CLEAR_AFTER_READ_ON, - .trigger_group_b = ADC_TRIGGER_SYNC_ELC, - .double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED, - .adc_vref_control = ADC_VREF_CONTROL_VREFH, }; -const adc_cfg_t g_adc0_cfg = -{ .unit = 0, .mode = ADC_MODE_SINGLE_SCAN, .resolution = ADC_RESOLUTION_14_BIT, .alignment = - (adc_alignment_t)ADC_ALIGNMENT_RIGHT, - .trigger = ADC_TRIGGER_SOFTWARE, .p_callback = NULL, .p_context = NULL, .p_extend = &g_adc0_cfg_extend, - #if defined(VECTOR_NUMBER_ADC0_SCAN_END) - .scan_end_irq = VECTOR_NUMBER_ADC0_SCAN_END, - #else - .scan_end_irq = FSP_INVALID_VECTOR, - #endif - .scan_end_ipl = (BSP_IRQ_DISABLED), - #if defined(VECTOR_NUMBER_ADC0_SCAN_END_B) - .scan_end_b_irq = VECTOR_NUMBER_ADC0_SCAN_END_B, - #else - .scan_end_b_irq = FSP_INVALID_VECTOR, - #endif - .scan_end_b_ipl = (BSP_IRQ_DISABLED), }; -const adc_channel_cfg_t g_adc0_channel_cfg = -{ .scan_mask = 0, - .scan_mask_group_b = 0, - .priority_group_a = ADC_GROUP_A_PRIORITY_OFF, - .add_mask = 0, - .sample_hold_mask = 0, - .sample_hold_states = 24, }; -/* Instance structure to use this module. */ -const adc_instance_t g_adc0 = -{ .p_ctrl = &g_adc0_ctrl, .p_cfg = &g_adc0_cfg, .p_channel_cfg = &g_adc0_channel_cfg, .p_api = &g_adc_on_adc }; -iic_master_instance_ctrl_t g_i2c_master0_ctrl; -const iic_master_extended_cfg_t g_i2c_master0_extend = -{ .timeout_mode = IIC_MASTER_TIMEOUT_MODE_SHORT, -/* Actual calculated bitrate: 99272. Actual calculated duty cycle: 49%. */ .clock_settings.brl_value = 27, - .clock_settings.brh_value = 26, .clock_settings.cks_value = 2, }; -const i2c_master_cfg_t g_i2c_master0_cfg = -{ .channel = 0, .rate = I2C_MASTER_RATE_STANDARD, .slave = 0x00, .addr_mode = I2C_MASTER_ADDR_MODE_7BIT, -#define RA_NOT_DEFINED (1) - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_tx = NULL, - #else - .p_transfer_tx = &RA_NOT_DEFINED, - #endif - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_rx = NULL, - #else - .p_transfer_rx = &RA_NOT_DEFINED, - #endif -#undef RA_NOT_DEFINED - .p_callback = callback_iic, - .p_context = NULL, - #if defined(VECTOR_NUMBER_IIC0_RXI) - .rxi_irq = VECTOR_NUMBER_IIC0_RXI, - #else - .rxi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_IIC0_TXI) - .txi_irq = VECTOR_NUMBER_IIC0_TXI, - #else - .txi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_IIC0_TEI) - .tei_irq = VECTOR_NUMBER_IIC0_TEI, - #else - .tei_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_IIC0_ERI) - .eri_irq = VECTOR_NUMBER_IIC0_ERI, - #else - .eri_irq = FSP_INVALID_VECTOR, - #endif - .ipl = (12), - .p_extend = &g_i2c_master0_extend, }; -/* Instance structure to use this module. */ -const i2c_master_instance_t g_i2c_master0 = -{ .p_ctrl = &g_i2c_master0_ctrl, .p_cfg = &g_i2c_master0_cfg, .p_api = &g_i2c_master_on_iic }; lpm_instance_ctrl_t g_lpm0_ctrl; const lpm_cfg_t g_lpm0_cfg = -{ .low_power_mode = LPM_MODE_SLEEP, +{ .low_power_mode = LPM_MODE_SLEEP, .standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM + | (lpm_standby_wake_source_t)0, + #if BSP_FEATURE_LPM_HAS_SNOOZE .snooze_cancel_sources = LPM_SNOOZE_CANCEL_SOURCE_NONE, - .standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM | (lpm_standby_wake_source_t)0, .snooze_request_source = LPM_SNOOZE_REQUEST_RXD0_FALLING, .snooze_end_sources = (lpm_snooze_end_t)0, .dtc_state_in_snooze = LPM_SNOOZE_DTC_DISABLE, + #endif #if BSP_FEATURE_LPM_HAS_SBYCR_OPE .output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN, #endif @@ -102,278 +19,24 @@ const lpm_cfg_t g_lpm0_cfg = .deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0, .deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0, #endif - .p_extend = NULL, }; - -const lpm_instance_t g_lpm0 = -{ .p_api = &g_lpm_on_lpm, .p_ctrl = &g_lpm0_ctrl, .p_cfg = &g_lpm0_cfg }; -dtc_instance_ctrl_t g_transfer1_ctrl; - -transfer_info_t g_transfer1_info = -{ .dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, - .repeat_area = TRANSFER_REPEAT_AREA_DESTINATION, - .irq = TRANSFER_IRQ_END, - .chain_mode = TRANSFER_CHAIN_MODE_DISABLED, - .src_addr_mode = TRANSFER_ADDR_MODE_FIXED, - .size = TRANSFER_SIZE_2_BYTE, - .mode = TRANSFER_MODE_NORMAL, - .p_dest = (void *)NULL, - .p_src = (void const *)NULL, - .num_blocks = 0, - .length = 0, }; -const dtc_extended_cfg_t g_transfer1_cfg_extend = -{ .activation_source = VECTOR_NUMBER_SPI0_RXI, }; -const transfer_cfg_t g_transfer1_cfg = -{ .p_info = &g_transfer1_info, .p_extend = &g_transfer1_cfg_extend, }; - -/* Instance structure to use this module. */ -const transfer_instance_t g_transfer1 = -{ .p_ctrl = &g_transfer1_ctrl, .p_cfg = &g_transfer1_cfg, .p_api = &g_transfer_on_dtc }; -dtc_instance_ctrl_t g_transfer0_ctrl; - -transfer_info_t g_transfer0_info = -{ .dest_addr_mode = TRANSFER_ADDR_MODE_FIXED, - .repeat_area = TRANSFER_REPEAT_AREA_SOURCE, - .irq = TRANSFER_IRQ_END, - .chain_mode = TRANSFER_CHAIN_MODE_DISABLED, - .src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, - .size = TRANSFER_SIZE_2_BYTE, - .mode = TRANSFER_MODE_NORMAL, - .p_dest = (void *)NULL, - .p_src = (void const *)NULL, - .num_blocks = 0, - .length = 0, }; -const dtc_extended_cfg_t g_transfer0_cfg_extend = -{ .activation_source = VECTOR_NUMBER_SPI0_TXI, }; -const transfer_cfg_t g_transfer0_cfg = -{ .p_info = &g_transfer0_info, .p_extend = &g_transfer0_cfg_extend, }; - -/* Instance structure to use this module. */ -const transfer_instance_t g_transfer0 = -{ .p_ctrl = &g_transfer0_ctrl, .p_cfg = &g_transfer0_cfg, .p_api = &g_transfer_on_dtc }; -spi_instance_ctrl_t g_spi0_ctrl; - -/** SPI extended configuration for SPI HAL driver */ -const spi_extended_cfg_t g_spi0_ext_cfg = -{ .spi_clksyn = SPI_SSL_MODE_CLK_SYN, - .spi_comm = SPI_COMMUNICATION_FULL_DUPLEX, - .ssl_polarity = SPI_SSLP_LOW, - .ssl_select = SPI_SSL_SELECT_SSL0, - .mosi_idle = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE, - .parity = SPI_PARITY_MODE_DISABLE, - .byte_swap = SPI_BYTE_SWAP_DISABLE, - .spck_div = - { - /* Actual calculated bitrate: 12000000. */ .spbr = 1, - .brdv = 0 - }, - .spck_delay = SPI_DELAY_COUNT_1, - .ssl_negation_delay = SPI_DELAY_COUNT_1, - .next_access_delay = SPI_DELAY_COUNT_1 }; - -/** SPI configuration for SPI HAL driver */ -const spi_cfg_t g_spi0_cfg = -{ .channel = 0, - - #if defined(VECTOR_NUMBER_SPI0_RXI) - .rxi_irq = VECTOR_NUMBER_SPI0_RXI, - #else - .rxi_irq = FSP_INVALID_VECTOR, + #if BSP_FEATURE_LPM_HAS_PDRAMSCR + .ram_retention_cfg.ram_retention = (uint8_t)(0), + .ram_retention_cfg.tcm_retention = false, #endif - #if defined(VECTOR_NUMBER_SPI0_TXI) - .txi_irq = VECTOR_NUMBER_SPI0_TXI, - #else - .txi_irq = FSP_INVALID_VECTOR, + #if BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP + .ram_retention_cfg.standby_ram_retention = false, #endif - #if defined(VECTOR_NUMBER_SPI0_TEI) - .tei_irq = VECTOR_NUMBER_SPI0_TEI, - #else - .tei_irq = FSP_INVALID_VECTOR, + #if BSP_FEATURE_LPM_HAS_LDO_CONTROL + .ldo_standby_cfg.pll1_ldo = false, + .ldo_standby_cfg.pll2_ldo = false, + .ldo_standby_cfg.hoco_ldo = false, #endif - #if defined(VECTOR_NUMBER_SPI0_ERI) - .eri_irq = VECTOR_NUMBER_SPI0_ERI, - #else - .eri_irq = FSP_INVALID_VECTOR, - #endif - - .rxi_ipl = (12), - .txi_ipl = (12), - .tei_ipl = (12), - .eri_ipl = (12), - - .operating_mode = SPI_MODE_MASTER, - - .clk_phase = SPI_CLK_PHASE_EDGE_ODD, - .clk_polarity = SPI_CLK_POLARITY_LOW, + .p_extend = NULL, }; - .mode_fault = SPI_MODE_FAULT_ERROR_DISABLE, - .bit_order = SPI_BIT_ORDER_MSB_FIRST, - .p_transfer_tx = g_spi0_P_TRANSFER_TX, - .p_transfer_rx = g_spi0_P_TRANSFER_RX, - .p_callback = spi_callback, +const lpm_instance_t g_lpm0 = +{ .p_api = &g_lpm_on_lpm, .p_ctrl = &g_lpm0_ctrl, .p_cfg = &g_lpm0_cfg }; - .p_context = NULL, - .p_extend = (void *)&g_spi0_ext_cfg, }; -/* Instance structure to use this module. */ -const spi_instance_t g_spi0 = -{ .p_ctrl = &g_spi0_ctrl, .p_cfg = &g_spi0_cfg, .p_api = &g_spi_on_spi }; -icu_instance_ctrl_t g_external_irq4_ctrl; -const external_irq_cfg_t g_external_irq4_cfg = -{ .channel = 4, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ4) - .irq = VECTOR_NUMBER_ICU_IRQ4, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq4 = -{ .p_ctrl = &g_external_irq4_ctrl, .p_cfg = &g_external_irq4_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq3_ctrl; -const external_irq_cfg_t g_external_irq3_cfg = -{ .channel = 3, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ3) - .irq = VECTOR_NUMBER_ICU_IRQ3, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq3 = -{ .p_ctrl = &g_external_irq3_ctrl, .p_cfg = &g_external_irq3_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq2_ctrl; -const external_irq_cfg_t g_external_irq2_cfg = -{ .channel = 2, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ2) - .irq = VECTOR_NUMBER_ICU_IRQ2, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq2 = -{ .p_ctrl = &g_external_irq2_ctrl, .p_cfg = &g_external_irq2_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq1_ctrl; -const external_irq_cfg_t g_external_irq1_cfg = -{ .channel = 1, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ1) - .irq = VECTOR_NUMBER_ICU_IRQ1, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq1 = -{ .p_ctrl = &g_external_irq1_ctrl, .p_cfg = &g_external_irq1_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq0_ctrl; -const external_irq_cfg_t g_external_irq0_cfg = -{ .channel = 0, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ0) - .irq = VECTOR_NUMBER_ICU_IRQ0, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq0 = -{ .p_ctrl = &g_external_irq0_ctrl, .p_cfg = &g_external_irq0_cfg, .p_api = &g_external_irq_on_icu }; -agt_instance_ctrl_t g_timer1_ctrl; -const agt_extended_cfg_t g_timer1_extend = -{ .count_source = AGT_CLOCK_PCLKB, - .agto = AGT_PIN_CFG_DISABLED, - .agtoa = AGT_PIN_CFG_DISABLED, - .agtob = AGT_PIN_CFG_DISABLED, - .measurement_mode = AGT_MEASURE_DISABLED, - .agtio_filter = AGT_AGTIO_FILTER_NONE, - .enable_pin = AGT_ENABLE_PIN_NOT_USED, - .trigger_edge = AGT_TRIGGER_EDGE_RISING, }; -const timer_cfg_t g_timer1_cfg = -{ .mode = TIMER_MODE_PERIODIC, -/* Actual period: 0.002730666666666667 seconds. Actual duty: 50%. */ .period_counts = 0x10000, - .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 1, .p_callback = callback_agt, - /** If NULL then do not add & */ - #if defined(NULL) - .p_context = NULL, - #else - .p_context = &NULL, - #endif - .p_extend = &g_timer1_extend, - .cycle_end_ipl = (5), - #if defined(VECTOR_NUMBER_AGT1_INT) - .cycle_end_irq = VECTOR_NUMBER_AGT1_INT, - #else - .cycle_end_irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const timer_instance_t g_timer1 = -{ .p_ctrl = &g_timer1_ctrl, .p_cfg = &g_timer1_cfg, .p_api = &g_timer_on_agt }; -agt_instance_ctrl_t g_timer0_ctrl; -const agt_extended_cfg_t g_timer0_extend = -{ .count_source = AGT_CLOCK_PCLKB, - .agto = AGT_PIN_CFG_DISABLED, - .agtoa = AGT_PIN_CFG_DISABLED, - .agtob = AGT_PIN_CFG_DISABLED, - .measurement_mode = AGT_MEASURE_DISABLED, - .agtio_filter = AGT_AGTIO_FILTER_NONE, - .enable_pin = AGT_ENABLE_PIN_NOT_USED, - .trigger_edge = AGT_TRIGGER_EDGE_RISING, }; -const timer_cfg_t g_timer0_cfg = -{ .mode = TIMER_MODE_PERIODIC, -/* Actual period: 0.002730666666666667 seconds. Actual duty: 50%. */ .period_counts = 0x10000, - .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 0, .p_callback = callback_agt, - /** If NULL then do not add & */ - #if defined(NULL) - .p_context = NULL, - #else - .p_context = &NULL, - #endif - .p_extend = &g_timer0_extend, - .cycle_end_ipl = (5), - #if defined(VECTOR_NUMBER_AGT0_INT) - .cycle_end_irq = VECTOR_NUMBER_AGT0_INT, - #else - .cycle_end_irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const timer_instance_t g_timer0 = -{ .p_ctrl = &g_timer0_ctrl, .p_cfg = &g_timer0_cfg, .p_api = &g_timer_on_agt }; flash_lp_instance_ctrl_t g_flash0_ctrl; const flash_cfg_t g_flash0_cfg = { .data_flash_bgo = false, .p_callback = NULL, .p_context = NULL, .ipl = (BSP_IRQ_DISABLED), @@ -386,239 +49,3 @@ const flash_cfg_t g_flash0_cfg = /* Instance structure to use this module. */ const flash_instance_t g_flash0 = { .p_ctrl = &g_flash0_ctrl, .p_cfg = &g_flash0_cfg, .p_api = &g_flash_on_flash_lp }; -rtc_instance_ctrl_t g_rtc0_ctrl; -const rtc_error_adjustment_cfg_t g_rtc0_err_cfg = -{ .adjustment_mode = RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC, - .adjustment_period = RTC_ERROR_ADJUSTMENT_PERIOD_10_SECOND, - .adjustment_type = RTC_ERROR_ADJUSTMENT_NONE, - .adjustment_value = 0, }; -const rtc_cfg_t g_rtc0_cfg = -{ .clock_source = RTC_CLOCK_SOURCE_LOCO, .freq_compare_value_loco = 255, .p_err_cfg = &g_rtc0_err_cfg, .p_callback = - NULL, - .p_context = NULL, .alarm_ipl = (14), .periodic_ipl = (14), .carry_ipl = (14), - #if defined(VECTOR_NUMBER_RTC_ALARM) - .alarm_irq = VECTOR_NUMBER_RTC_ALARM, - #else - .alarm_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_RTC_PERIOD) - .periodic_irq = VECTOR_NUMBER_RTC_PERIOD, - #else - .periodic_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_RTC_CARRY) - .carry_irq = VECTOR_NUMBER_RTC_CARRY, - #else - .carry_irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const rtc_instance_t g_rtc0 = -{ .p_ctrl = &g_rtc0_ctrl, .p_cfg = &g_rtc0_cfg, .p_api = &g_rtc_on_rtc }; -sci_uart_instance_ctrl_t g_uart9_ctrl; - -baud_setting_t g_uart9_baud_setting = -{ -/* Baud rate calculated with 0.160% error. */ .abcse = 0, - .abcs = 0, .bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t)256, .brme = false -}; - -/** UART extended configuration for UARTonSCI HAL driver */ -const sci_uart_extended_cfg_t g_uart9_cfg_extend = -{ .clock = SCI_UART_CLOCK_INT, - .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, - .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, - .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, - .p_baud_setting = &g_uart9_baud_setting, - .uart_mode = UART_MODE_RS232, - .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, - #if 0 - .flow_control_pin = BSP_IO_PORT_00_PIN_00, - #else - .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), - #endif -}; - -/** UART interface configuration */ -const uart_cfg_t g_uart9_cfg = -{ .channel = 9, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = - user_uart_callback, - .p_context = NULL, .p_extend = &g_uart9_cfg_extend, -#define RA_NOT_DEFINED (1) - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_tx = NULL, - #else - .p_transfer_tx = &RA_NOT_DEFINED, - #endif - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_rx = NULL, - #else - .p_transfer_rx = &RA_NOT_DEFINED, - #endif -#undef RA_NOT_DEFINED - .rxi_ipl = (12), - .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), - #if defined(VECTOR_NUMBER_SCI9_RXI) - .rxi_irq = VECTOR_NUMBER_SCI9_RXI, - #else - .rxi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI9_TXI) - .txi_irq = VECTOR_NUMBER_SCI9_TXI, - #else - .txi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI9_TEI) - .tei_irq = VECTOR_NUMBER_SCI9_TEI, - #else - .tei_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI9_ERI) - .eri_irq = VECTOR_NUMBER_SCI9_ERI, - #else - .eri_irq = FSP_INVALID_VECTOR, - #endif -}; - -/* Instance structure to use this module. */ -const uart_instance_t g_uart9 = -{ .p_ctrl = &g_uart9_ctrl, .p_cfg = &g_uart9_cfg, .p_api = &g_uart_on_sci }; -sci_uart_instance_ctrl_t g_uart4_ctrl; - -baud_setting_t g_uart4_baud_setting = -{ -/* Baud rate calculated with 0.160% error. */ .abcse = 0, - .abcs = 0, .bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t)256, .brme = false -}; - -/** UART extended configuration for UARTonSCI HAL driver */ -const sci_uart_extended_cfg_t g_uart4_cfg_extend = -{ .clock = SCI_UART_CLOCK_INT, - .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, - .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, - .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, - .p_baud_setting = &g_uart4_baud_setting, - .uart_mode = UART_MODE_RS232, - .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, - #if 0 - .flow_control_pin = BSP_IO_PORT_00_PIN_00, - #else - .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), - #endif -}; - -/** UART interface configuration */ -const uart_cfg_t g_uart4_cfg = -{ .channel = 4, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = - user_uart_callback, - .p_context = NULL, .p_extend = &g_uart4_cfg_extend, -#define RA_NOT_DEFINED (1) - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_tx = NULL, - #else - .p_transfer_tx = &RA_NOT_DEFINED, - #endif - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_rx = NULL, - #else - .p_transfer_rx = &RA_NOT_DEFINED, - #endif -#undef RA_NOT_DEFINED - .rxi_ipl = (12), - .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), - #if defined(VECTOR_NUMBER_SCI4_RXI) - .rxi_irq = VECTOR_NUMBER_SCI4_RXI, - #else - .rxi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI4_TXI) - .txi_irq = VECTOR_NUMBER_SCI4_TXI, - #else - .txi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI4_TEI) - .tei_irq = VECTOR_NUMBER_SCI4_TEI, - #else - .tei_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI4_ERI) - .eri_irq = VECTOR_NUMBER_SCI4_ERI, - #else - .eri_irq = FSP_INVALID_VECTOR, - #endif -}; - -/* Instance structure to use this module. */ -const uart_instance_t g_uart4 = -{ .p_ctrl = &g_uart4_ctrl, .p_cfg = &g_uart4_cfg, .p_api = &g_uart_on_sci }; -sci_uart_instance_ctrl_t g_uart1_ctrl; - -baud_setting_t g_uart1_baud_setting = -{ -/* Baud rate calculated with 0.160% error. */ .abcse = 0, - .abcs = 0, .bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t)256, .brme = false -}; - -/** UART extended configuration for UARTonSCI HAL driver */ -const sci_uart_extended_cfg_t g_uart1_cfg_extend = -{ .clock = SCI_UART_CLOCK_INT, - .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, - .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, - .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, - .p_baud_setting = &g_uart1_baud_setting, - .uart_mode = UART_MODE_RS232, - .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, - #if 0 - .flow_control_pin = BSP_IO_PORT_00_PIN_00, - #else - .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), - #endif -}; - -/** UART interface configuration */ -const uart_cfg_t g_uart1_cfg = -{ .channel = 1, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = - user_uart_callback, - .p_context = NULL, .p_extend = &g_uart1_cfg_extend, -#define RA_NOT_DEFINED (1) - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_tx = NULL, - #else - .p_transfer_tx = &RA_NOT_DEFINED, - #endif - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_rx = NULL, - #else - .p_transfer_rx = &RA_NOT_DEFINED, - #endif -#undef RA_NOT_DEFINED - .rxi_ipl = (12), - .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), - #if defined(VECTOR_NUMBER_SCI1_RXI) - .rxi_irq = VECTOR_NUMBER_SCI1_RXI, - #else - .rxi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI1_TXI) - .txi_irq = VECTOR_NUMBER_SCI1_TXI, - #else - .txi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI1_TEI) - .tei_irq = VECTOR_NUMBER_SCI1_TEI, - #else - .tei_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI1_ERI) - .eri_irq = VECTOR_NUMBER_SCI1_ERI, - #else - .eri_irq = FSP_INVALID_VECTOR, - #endif -}; - -/* Instance structure to use this module. */ -const uart_instance_t g_uart1 = -{ .p_ctrl = &g_uart1_ctrl, .p_cfg = &g_uart1_cfg, .p_api = &g_uart_on_sci }; -void g_hal_init(void) { - g_common_init(); -} diff --git a/ports/renesas-ra/boards/EK_RA4W1/ra_gen/hal_data.h b/ports/renesas-ra/boards/EK_RA4W1/ra_gen/hal_data.h index cf3f00771..7b1e505f6 100644 --- a/ports/renesas-ra/boards/EK_RA4W1/ra_gen/hal_data.h +++ b/ports/renesas-ra/boards/EK_RA4W1/ra_gen/hal_data.h @@ -2,161 +2,20 @@ #ifndef HAL_DATA_H_ #define HAL_DATA_H_ #include <stdint.h> -#include "bsp_api.h" #include "common_data.h" -#include "r_adc.h" -#include "r_adc_api.h" -#include "r_iic_master.h" -#include "r_i2c_master_api.h" #include "r_lpm.h" #include "r_lpm_api.h" -#include "r_dtc.h" -#include "r_transfer_api.h" -#include "r_spi.h" -#include "r_icu.h" -#include "r_external_irq_api.h" -#include "r_agt.h" -#include "r_timer_api.h" #include "r_flash_lp.h" #include "r_flash_api.h" -#include "r_rtc.h" -#include "r_rtc_api.h" -#include "r_sci_uart.h" -#include "r_uart_api.h" FSP_HEADER -/** ADC on ADC Instance. */ -extern const adc_instance_t g_adc0; -/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */ -extern adc_instance_ctrl_t g_adc0_ctrl; -extern const adc_cfg_t g_adc0_cfg; -extern const adc_channel_cfg_t g_adc0_channel_cfg; - -#ifndef NULL -void NULL(adc_callback_args_t *p_args); -#endif -/* I2C Master on IIC Instance. */ -extern const i2c_master_instance_t g_i2c_master0; - -/** Access the I2C Master instance using these structures when calling API functions directly (::p_api is not used). */ -extern iic_master_instance_ctrl_t g_i2c_master0_ctrl; -extern const i2c_master_cfg_t g_i2c_master0_cfg; - -#ifndef callback_iic -void callback_iic(i2c_master_callback_args_t *p_args); -#endif /** lpm Instance */ extern const lpm_instance_t g_lpm0; /** Access the LPM instance using these structures when calling API functions directly (::p_api is not used). */ extern lpm_instance_ctrl_t g_lpm0_ctrl; extern const lpm_cfg_t g_lpm0_cfg; -/* Transfer on DTC Instance. */ -extern const transfer_instance_t g_transfer1; - -/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ -extern dtc_instance_ctrl_t g_transfer1_ctrl; -extern const transfer_cfg_t g_transfer1_cfg; -/* Transfer on DTC Instance. */ -extern const transfer_instance_t g_transfer0; - -/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ -extern dtc_instance_ctrl_t g_transfer0_ctrl; -extern const transfer_cfg_t g_transfer0_cfg; -/** SPI on SPI Instance. */ -extern const spi_instance_t g_spi0; - -/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */ -extern spi_instance_ctrl_t g_spi0_ctrl; -extern const spi_cfg_t g_spi0_cfg; - -/** Callback used by SPI Instance. */ -#ifndef spi_callback -void spi_callback(spi_callback_args_t *p_args); -#endif - -#define RA_NOT_DEFINED (1) -#if (RA_NOT_DEFINED == g_transfer0) - #define g_spi0_P_TRANSFER_TX (NULL) -#else -#define g_spi0_P_TRANSFER_TX (&g_transfer0) -#endif -#if (RA_NOT_DEFINED == g_transfer1) - #define g_spi0_P_TRANSFER_RX (NULL) -#else -#define g_spi0_P_TRANSFER_RX (&g_transfer1) -#endif -#undef RA_NOT_DEFINED -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq4; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq4_ctrl; -extern const external_irq_cfg_t g_external_irq4_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq3; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq3_ctrl; -extern const external_irq_cfg_t g_external_irq3_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq2; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq2_ctrl; -extern const external_irq_cfg_t g_external_irq2_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq1; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq1_ctrl; -extern const external_irq_cfg_t g_external_irq1_cfg; -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq0; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq0_ctrl; -extern const external_irq_cfg_t g_external_irq0_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** AGT Timer Instance */ -extern const timer_instance_t g_timer1; - -/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ -extern agt_instance_ctrl_t g_timer1_ctrl; -extern const timer_cfg_t g_timer1_cfg; - -#ifndef callback_agt -void callback_agt(timer_callback_args_t *p_args); -#endif -/** AGT Timer Instance */ -extern const timer_instance_t g_timer0; - -/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ -extern agt_instance_ctrl_t g_timer0_ctrl; -extern const timer_cfg_t g_timer0_cfg; - -#ifndef callback_agt -void callback_agt(timer_callback_args_t *p_args); -#endif /* Flash on Flash LP Instance. */ extern const flash_instance_t g_flash0; @@ -167,50 +26,8 @@ extern const flash_cfg_t g_flash0_cfg; #ifndef NULL void NULL(flash_callback_args_t *p_args); #endif -/* RTC Instance. */ -extern const rtc_instance_t g_rtc0; - -/** Access the RTC instance using these structures when calling API functions directly (::p_api is not used). */ -extern rtc_instance_ctrl_t g_rtc0_ctrl; -extern const rtc_cfg_t g_rtc0_cfg; -#ifndef NULL -void NULL(rtc_callback_args_t *p_args); -#endif -/** UART on SCI Instance. */ -extern const uart_instance_t g_uart9; - -/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ -extern sci_uart_instance_ctrl_t g_uart9_ctrl; -extern const uart_cfg_t g_uart9_cfg; -extern const sci_uart_extended_cfg_t g_uart9_cfg_extend; - -#ifndef user_uart_callback -void user_uart_callback(uart_callback_args_t *p_args); -#endif -/** UART on SCI Instance. */ -extern const uart_instance_t g_uart4; - -/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ -extern sci_uart_instance_ctrl_t g_uart4_ctrl; -extern const uart_cfg_t g_uart4_cfg; -extern const sci_uart_extended_cfg_t g_uart4_cfg_extend; - -#ifndef user_uart_callback -void user_uart_callback(uart_callback_args_t *p_args); -#endif -/** UART on SCI Instance. */ -extern const uart_instance_t g_uart1; - -/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ -extern sci_uart_instance_ctrl_t g_uart1_ctrl; -extern const uart_cfg_t g_uart1_cfg; -extern const sci_uart_extended_cfg_t g_uart1_cfg_extend; - -#ifndef user_uart_callback -void user_uart_callback(uart_callback_args_t *p_args); -#endif void hal_entry(void); -void g_hal_init(void); + FSP_FOOTER #endif /* HAL_DATA_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA4W1/ra_gen/pin_data.c b/ports/renesas-ra/boards/EK_RA4W1/ra_gen/pin_data.c index 2a5a8764c..7e318319e 100644 --- a/ports/renesas-ra/boards/EK_RA4W1/ra_gen/pin_data.c +++ b/ports/renesas-ra/boards/EK_RA4W1/ra_gen/pin_data.c @@ -1,69 +1,74 @@ /* generated pin source file - do not edit */ #include "bsp_api.h" #include "r_ioport_api.h" -const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { - { - .pin = BSP_IO_PORT_01_PIN_00, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), - }, - { - .pin = BSP_IO_PORT_01_PIN_01, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), - }, - { - .pin = BSP_IO_PORT_01_PIN_02, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), - }, - { - .pin = BSP_IO_PORT_01_PIN_03, - .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_HIGH), - }, - { - .pin = BSP_IO_PORT_01_PIN_06, - .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_HIGH), - }, - { - .pin = BSP_IO_PORT_01_PIN_09, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9), - }, - { - .pin = BSP_IO_PORT_01_PIN_10, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9), - }, - { - .pin = BSP_IO_PORT_01_PIN_11, - .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_HIGH), - }, - { - .pin = BSP_IO_PORT_02_PIN_04, - .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_HIGH), - }, - { - .pin = BSP_IO_PORT_02_PIN_05, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), - }, - { - .pin = BSP_IO_PORT_02_PIN_06, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), - }, - { - .pin = BSP_IO_PORT_02_PIN_12, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9), - }, - { - .pin = BSP_IO_PORT_02_PIN_13, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9), - }, + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = +{ + { .pin = BSP_IO_PORT_01_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SPI) }, + { .pin = BSP_IO_PORT_01_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SPI) }, + { .pin = BSP_IO_PORT_01_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SPI) }, + { .pin = BSP_IO_PORT_01_PIN_03, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT + | (uint32_t)IOPORT_CFG_PORT_OUTPUT_HIGH) }, + { .pin = BSP_IO_PORT_01_PIN_06, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT + | (uint32_t)IOPORT_CFG_PORT_OUTPUT_HIGH) }, + { .pin = BSP_IO_PORT_01_PIN_09, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, + { .pin = BSP_IO_PORT_01_PIN_10, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, + { .pin = BSP_IO_PORT_01_PIN_11, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT + | (uint32_t)IOPORT_CFG_PORT_OUTPUT_HIGH) }, + { .pin = BSP_IO_PORT_02_PIN_04, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT + | (uint32_t)IOPORT_CFG_PORT_OUTPUT_HIGH) }, + { .pin = BSP_IO_PORT_02_PIN_05, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) }, + { .pin = BSP_IO_PORT_02_PIN_06, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) }, + { .pin = BSP_IO_PORT_02_PIN_12, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, + { .pin = BSP_IO_PORT_02_PIN_13, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, + { .pin = BSP_IO_PORT_04_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE + | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT) }, + { .pin = BSP_IO_PORT_04_PIN_04, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT + | (uint32_t)IOPORT_CFG_PORT_OUTPUT_HIGH) }, +}; + +const ioport_cfg_t g_bsp_pin_cfg = +{ .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], }; + +#if BSP_TZ_SECURE_BUILD + +void R_BSP_PinCfgSecurityInit(void); + +/* Initialize SAR registers for secure pins. */ +void R_BSP_PinCfgSecurityInit(void) { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #else + uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #endif + memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0])); + + + for (uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++) { - .pin = BSP_IO_PORT_04_PIN_02, - .pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT), - }, + uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin; + uint32_t port = port_pin >> 8U; + uint32_t pin = port_pin & 0xFFU; + pmsar[port] &= (uint16_t) ~(1U << pin); + } + + for (uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) { - .pin = BSP_IO_PORT_04_PIN_04, - .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_HIGH), - }, -}; -const ioport_cfg_t g_bsp_pin_cfg = { - .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), - .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], -}; + #if (2U == BSP_FEATURE_IOPORT_VERSION) + R_PMISC->PMSAR[i].PMSAR = (uint16_t)pmsar[i]; + #else + R_PMISC->PMSAR[i].PMSAR = pmsar[i]; + #endif + } + +} +#endif diff --git a/ports/renesas-ra/boards/EK_RA4W1/ra_gen/vector_data.c b/ports/renesas-ra/boards/EK_RA4W1/ra_gen/vector_data.c index 1867e7383..18986d0ae 100644 --- a/ports/renesas-ra/boards/EK_RA4W1/ra_gen/vector_data.c +++ b/ports/renesas-ra/boards/EK_RA4W1/ra_gen/vector_data.c @@ -14,26 +14,26 @@ BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BS [7] = sci_uart_eri_isr, /* SCI4 ERI (Receive error) */ [8] = sci_uart_rxi_isr, /* SCI9 RXI (Received data full) */ [9] = sci_uart_txi_isr, /* SCI9 TXI (Transmit data empty) */ - [10] = sci_uart_tei_isr, /* SCI9 TEI (Transmit end) */ - [11] = sci_uart_eri_isr, /* SCI9 ERI (Receive error) */ - [12] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */ - [13] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */ - [14] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */ - [15] = agt_int_isr, /* AGT0 INT (AGT interrupt) */ - [16] = agt_int_isr, /* AGT1 INT (AGT interrupt) */ - [17] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */ - [18] = r_icu_isr, /* ICU IRQ1 (External pin interrupt 1) */ - [19] = r_icu_isr, /* ICU IRQ2 (External pin interrupt 2) */ - [20] = r_icu_isr, /* ICU IRQ3 (External pin interrupt 3) */ - [21] = r_icu_isr, /* ICU IRQ4 (External pin interrupt 4) */ - [22] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */ - [23] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */ - [24] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */ - [25] = spi_eri_isr, /* SPI0 ERI (Error) */ - [26] = iic_master_rxi_isr, /* IIC0 RXI (Receive data full) */ - [27] = iic_master_txi_isr, /* IIC0 TXI (Transmit data empty) */ - [28] = iic_master_tei_isr, /* IIC0 TEI (Transmit end) */ - [29] = iic_master_eri_isr, /* IIC0 ERI (Transfer error) */ + [10] = sci_uart_tei_isr, /* SCI9 TEI (Transmit end) */ + [11] = sci_uart_eri_isr, /* SCI9 ERI (Receive error) */ + [12] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */ + [13] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */ + [14] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */ + [15] = agt_int_isr, /* AGT0 INT (AGT interrupt) */ + [16] = agt_int_isr, /* AGT1 INT (AGT interrupt) */ + [17] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */ + [18] = r_icu_isr, /* ICU IRQ1 (External pin interrupt 1) */ + [19] = r_icu_isr, /* ICU IRQ2 (External pin interrupt 2) */ + [20] = r_icu_isr, /* ICU IRQ3 (External pin interrupt 3) */ + [21] = r_icu_isr, /* ICU IRQ4 (External pin interrupt 4) */ + [22] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */ + [23] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */ + [24] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */ + [25] = spi_eri_isr, /* SPI0 ERI (Error) */ + [26] = iic_master_rxi_isr, /* IIC0 RXI (Receive data full) */ + [27] = iic_master_txi_isr, /* IIC0 TXI (Transmit data empty) */ + [28] = iic_master_tei_isr, /* IIC0 TEI (Transmit end) */ + [29] = iic_master_eri_isr, /* IIC0 ERI (Transfer error) */ }; const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = { @@ -47,25 +47,25 @@ const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENT [7] = BSP_PRV_IELS_ENUM(EVENT_SCI4_ERI), /* SCI4 ERI (Receive error) */ [8] = BSP_PRV_IELS_ENUM(EVENT_SCI9_RXI), /* SCI9 RXI (Received data full) */ [9] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TXI), /* SCI9 TXI (Transmit data empty) */ - [10] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TEI), /* SCI9 TEI (Transmit end) */ - [11] = BSP_PRV_IELS_ENUM(EVENT_SCI9_ERI), /* SCI9 ERI (Receive error) */ - [12] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */ - [13] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */ - [14] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */ - [15] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */ - [16] = BSP_PRV_IELS_ENUM(EVENT_AGT1_INT), /* AGT1 INT (AGT interrupt) */ - [17] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ0), /* ICU IRQ0 (External pin interrupt 0) */ - [18] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ1), /* ICU IRQ1 (External pin interrupt 1) */ - [19] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ2), /* ICU IRQ2 (External pin interrupt 2) */ - [20] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ3), /* ICU IRQ3 (External pin interrupt 3) */ - [21] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ4), /* ICU IRQ4 (External pin interrupt 4) */ - [22] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */ - [23] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */ - [24] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */ - [25] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */ - [26] = BSP_PRV_IELS_ENUM(EVENT_IIC0_RXI), /* IIC0 RXI (Receive data full) */ - [27] = BSP_PRV_IELS_ENUM(EVENT_IIC0_TXI), /* IIC0 TXI (Transmit data empty) */ - [28] = BSP_PRV_IELS_ENUM(EVENT_IIC0_TEI), /* IIC0 TEI (Transmit end) */ - [29] = BSP_PRV_IELS_ENUM(EVENT_IIC0_ERI), /* IIC0 ERI (Transfer error) */ + [10] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TEI), /* SCI9 TEI (Transmit end) */ + [11] = BSP_PRV_IELS_ENUM(EVENT_SCI9_ERI), /* SCI9 ERI (Receive error) */ + [12] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */ + [13] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */ + [14] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */ + [15] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */ + [16] = BSP_PRV_IELS_ENUM(EVENT_AGT1_INT), /* AGT1 INT (AGT interrupt) */ + [17] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ0), /* ICU IRQ0 (External pin interrupt 0) */ + [18] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ1), /* ICU IRQ1 (External pin interrupt 1) */ + [19] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ2), /* ICU IRQ2 (External pin interrupt 2) */ + [20] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ3), /* ICU IRQ3 (External pin interrupt 3) */ + [21] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ4), /* ICU IRQ4 (External pin interrupt 4) */ + [22] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */ + [23] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */ + [24] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */ + [25] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */ + [26] = BSP_PRV_IELS_ENUM(EVENT_IIC0_RXI), /* IIC0 RXI (Receive data full) */ + [27] = BSP_PRV_IELS_ENUM(EVENT_IIC0_TXI), /* IIC0 TXI (Transmit data empty) */ + [28] = BSP_PRV_IELS_ENUM(EVENT_IIC0_TEI), /* IIC0 TEI (Transmit end) */ + [29] = BSP_PRV_IELS_ENUM(EVENT_IIC0_ERI), /* IIC0 ERI (Transfer error) */ }; #endif diff --git a/ports/renesas-ra/boards/EK_RA4W1/ra_gen/vector_data.h b/ports/renesas-ra/boards/EK_RA4W1/ra_gen/vector_data.h index c45ef8d95..a4adf6ab0 100644 --- a/ports/renesas-ra/boards/EK_RA4W1/ra_gen/vector_data.h +++ b/ports/renesas-ra/boards/EK_RA4W1/ra_gen/vector_data.h @@ -1,6 +1,9 @@ /* generated vector header file - do not edit */ #ifndef VECTOR_DATA_H #define VECTOR_DATA_H +#ifdef __cplusplus +extern "C" { +#endif /* Number of interrupts allocated */ #ifndef VECTOR_DATA_IRQ_COUNT #define VECTOR_DATA_IRQ_COUNT (30) @@ -25,77 +28,66 @@ void iic_master_eri_isr(void); /* Vector table allocations */ #define VECTOR_NUMBER_SCI1_RXI ((IRQn_Type)0) /* SCI1 RXI (Received data full) */ +#define SCI1_RXI_IRQn ((IRQn_Type)0) /* SCI1 RXI (Received data full) */ #define VECTOR_NUMBER_SCI1_TXI ((IRQn_Type)1) /* SCI1 TXI (Transmit data empty) */ +#define SCI1_TXI_IRQn ((IRQn_Type)1) /* SCI1 TXI (Transmit data empty) */ #define VECTOR_NUMBER_SCI1_TEI ((IRQn_Type)2) /* SCI1 TEI (Transmit end) */ +#define SCI1_TEI_IRQn ((IRQn_Type)2) /* SCI1 TEI (Transmit end) */ #define VECTOR_NUMBER_SCI1_ERI ((IRQn_Type)3) /* SCI1 ERI (Receive error) */ +#define SCI1_ERI_IRQn ((IRQn_Type)3) /* SCI1 ERI (Receive error) */ #define VECTOR_NUMBER_SCI4_RXI ((IRQn_Type)4) /* SCI4 RXI (Received data full) */ +#define SCI4_RXI_IRQn ((IRQn_Type)4) /* SCI4 RXI (Received data full) */ #define VECTOR_NUMBER_SCI4_TXI ((IRQn_Type)5) /* SCI4 TXI (Transmit data empty) */ +#define SCI4_TXI_IRQn ((IRQn_Type)5) /* SCI4 TXI (Transmit data empty) */ #define VECTOR_NUMBER_SCI4_TEI ((IRQn_Type)6) /* SCI4 TEI (Transmit end) */ +#define SCI4_TEI_IRQn ((IRQn_Type)6) /* SCI4 TEI (Transmit end) */ #define VECTOR_NUMBER_SCI4_ERI ((IRQn_Type)7) /* SCI4 ERI (Receive error) */ +#define SCI4_ERI_IRQn ((IRQn_Type)7) /* SCI4 ERI (Receive error) */ #define VECTOR_NUMBER_SCI9_RXI ((IRQn_Type)8) /* SCI9 RXI (Received data full) */ +#define SCI9_RXI_IRQn ((IRQn_Type)8) /* SCI9 RXI (Received data full) */ #define VECTOR_NUMBER_SCI9_TXI ((IRQn_Type)9) /* SCI9 TXI (Transmit data empty) */ +#define SCI9_TXI_IRQn ((IRQn_Type)9) /* SCI9 TXI (Transmit data empty) */ #define VECTOR_NUMBER_SCI9_TEI ((IRQn_Type)10) /* SCI9 TEI (Transmit end) */ +#define SCI9_TEI_IRQn ((IRQn_Type)10) /* SCI9 TEI (Transmit end) */ #define VECTOR_NUMBER_SCI9_ERI ((IRQn_Type)11) /* SCI9 ERI (Receive error) */ +#define SCI9_ERI_IRQn ((IRQn_Type)11) /* SCI9 ERI (Receive error) */ #define VECTOR_NUMBER_RTC_ALARM ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */ +#define RTC_ALARM_IRQn ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */ #define VECTOR_NUMBER_RTC_PERIOD ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */ +#define RTC_PERIOD_IRQn ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */ #define VECTOR_NUMBER_RTC_CARRY ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */ +#define RTC_CARRY_IRQn ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */ #define VECTOR_NUMBER_AGT0_INT ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */ +#define AGT0_INT_IRQn ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */ #define VECTOR_NUMBER_AGT1_INT ((IRQn_Type)16) /* AGT1 INT (AGT interrupt) */ +#define AGT1_INT_IRQn ((IRQn_Type)16) /* AGT1 INT (AGT interrupt) */ #define VECTOR_NUMBER_ICU_IRQ0 ((IRQn_Type)17) /* ICU IRQ0 (External pin interrupt 0) */ +#define ICU_IRQ0_IRQn ((IRQn_Type)17) /* ICU IRQ0 (External pin interrupt 0) */ #define VECTOR_NUMBER_ICU_IRQ1 ((IRQn_Type)18) /* ICU IRQ1 (External pin interrupt 1) */ +#define ICU_IRQ1_IRQn ((IRQn_Type)18) /* ICU IRQ1 (External pin interrupt 1) */ #define VECTOR_NUMBER_ICU_IRQ2 ((IRQn_Type)19) /* ICU IRQ2 (External pin interrupt 2) */ +#define ICU_IRQ2_IRQn ((IRQn_Type)19) /* ICU IRQ2 (External pin interrupt 2) */ #define VECTOR_NUMBER_ICU_IRQ3 ((IRQn_Type)20) /* ICU IRQ3 (External pin interrupt 3) */ +#define ICU_IRQ3_IRQn ((IRQn_Type)20) /* ICU IRQ3 (External pin interrupt 3) */ #define VECTOR_NUMBER_ICU_IRQ4 ((IRQn_Type)21) /* ICU IRQ4 (External pin interrupt 4) */ +#define ICU_IRQ4_IRQn ((IRQn_Type)21) /* ICU IRQ4 (External pin interrupt 4) */ #define VECTOR_NUMBER_SPI0_RXI ((IRQn_Type)22) /* SPI0 RXI (Receive buffer full) */ +#define SPI0_RXI_IRQn ((IRQn_Type)22) /* SPI0 RXI (Receive buffer full) */ #define VECTOR_NUMBER_SPI0_TXI ((IRQn_Type)23) /* SPI0 TXI (Transmit buffer empty) */ +#define SPI0_TXI_IRQn ((IRQn_Type)23) /* SPI0 TXI (Transmit buffer empty) */ #define VECTOR_NUMBER_SPI0_TEI ((IRQn_Type)24) /* SPI0 TEI (Transmission complete event) */ +#define SPI0_TEI_IRQn ((IRQn_Type)24) /* SPI0 TEI (Transmission complete event) */ #define VECTOR_NUMBER_SPI0_ERI ((IRQn_Type)25) /* SPI0 ERI (Error) */ +#define SPI0_ERI_IRQn ((IRQn_Type)25) /* SPI0 ERI (Error) */ #define VECTOR_NUMBER_IIC0_RXI ((IRQn_Type)26) /* IIC0 RXI (Receive data full) */ +#define IIC0_RXI_IRQn ((IRQn_Type)26) /* IIC0 RXI (Receive data full) */ #define VECTOR_NUMBER_IIC0_TXI ((IRQn_Type)27) /* IIC0 TXI (Transmit data empty) */ +#define IIC0_TXI_IRQn ((IRQn_Type)27) /* IIC0 TXI (Transmit data empty) */ #define VECTOR_NUMBER_IIC0_TEI ((IRQn_Type)28) /* IIC0 TEI (Transmit end) */ +#define IIC0_TEI_IRQn ((IRQn_Type)28) /* IIC0 TEI (Transmit end) */ #define VECTOR_NUMBER_IIC0_ERI ((IRQn_Type)29) /* IIC0 ERI (Transfer error) */ -typedef enum IRQn -{ - Reset_IRQn = -15, - NonMaskableInt_IRQn = -14, - HardFault_IRQn = -13, - MemoryManagement_IRQn = -12, - BusFault_IRQn = -11, - UsageFault_IRQn = -10, - SecureFault_IRQn = -9, - SVCall_IRQn = -5, - DebugMonitor_IRQn = -4, - PendSV_IRQn = -2, - SysTick_IRQn = -1, - SCI1_RXI_IRQn = 0, /* SCI1 RXI (Received data full) */ - SCI1_TXI_IRQn = 1, /* SCI1 TXI (Transmit data empty) */ - SCI1_TEI_IRQn = 2, /* SCI1 TEI (Transmit end) */ - SCI1_ERI_IRQn = 3, /* SCI1 ERI (Receive error) */ - SCI4_RXI_IRQn = 4, /* SCI4 RXI (Received data full) */ - SCI4_TXI_IRQn = 5, /* SCI4 TXI (Transmit data empty) */ - SCI4_TEI_IRQn = 6, /* SCI4 TEI (Transmit end) */ - SCI4_ERI_IRQn = 7, /* SCI4 ERI (Receive error) */ - SCI9_RXI_IRQn = 8, /* SCI9 RXI (Received data full) */ - SCI9_TXI_IRQn = 9, /* SCI9 TXI (Transmit data empty) */ - SCI9_TEI_IRQn = 10, /* SCI9 TEI (Transmit end) */ - SCI9_ERI_IRQn = 11, /* SCI9 ERI (Receive error) */ - RTC_ALARM_IRQn = 12, /* RTC ALARM (Alarm interrupt) */ - RTC_PERIOD_IRQn = 13, /* RTC PERIOD (Periodic interrupt) */ - RTC_CARRY_IRQn = 14, /* RTC CARRY (Carry interrupt) */ - AGT0_INT_IRQn = 15, /* AGT0 INT (AGT interrupt) */ - AGT1_INT_IRQn = 16, /* AGT1 INT (AGT interrupt) */ - ICU_IRQ0_IRQn = 17, /* ICU IRQ0 (External pin interrupt 0) */ - ICU_IRQ1_IRQn = 18, /* ICU IRQ1 (External pin interrupt 1) */ - ICU_IRQ2_IRQn = 19, /* ICU IRQ2 (External pin interrupt 2) */ - ICU_IRQ3_IRQn = 20, /* ICU IRQ3 (External pin interrupt 3) */ - ICU_IRQ4_IRQn = 21, /* ICU IRQ4 (External pin interrupt 4) */ - SPI0_RXI_IRQn = 22, /* SPI0 RXI (Receive buffer full) */ - SPI0_TXI_IRQn = 23, /* SPI0 TXI (Transmit buffer empty) */ - SPI0_TEI_IRQn = 24, /* SPI0 TEI (Transmission complete event) */ - SPI0_ERI_IRQn = 25, /* SPI0 ERI (Error) */ - IIC0_RXI_IRQn = 26, /* IIC0 RXI (Receive data full) */ - IIC0_TXI_IRQn = 27, /* IIC0 TXI (Transmit data empty) */ - IIC0_TEI_IRQn = 28, /* IIC0 TEI (Transmit end) */ - IIC0_ERI_IRQn = 29, /* IIC0 ERI (Transfer error) */ -} IRQn_Type; +#define IIC0_ERI_IRQn ((IRQn_Type)29) /* IIC0 ERI (Transfer error) */ +#ifdef __cplusplus +} +#endif #endif /* VECTOR_DATA_H */ diff --git a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/bsp/bsp_cfg.h index 54b41a45d..0dcada794 100644 --- a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/bsp/bsp_cfg.h +++ b/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -1,6 +1,10 @@ /* generated configuration header file - do not edit */ #ifndef BSP_CFG_H_ #define BSP_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #include "bsp_clock_cfg.h" #include "bsp_mcu_family_cfg.h" #include "board_cfg.h" @@ -14,7 +18,13 @@ #define BSP_CFG_RTOS (0) #endif #endif +#ifndef BSP_CFG_RTC_USED +#define BSP_CFG_RTC_USED (1) +#endif #undef RA_NOT_DEFINED +#if defined(_RA_BOOT_IMAGE) +#define BSP_CFG_BOOT_IMAGE (1) +#endif #define BSP_CFG_MCU_VCC_MV (3300) #define BSP_CFG_STACK_MAIN_BYTES (0x4000) #define BSP_CFG_HEAP_BYTES (0x2d000) @@ -25,15 +35,14 @@ #define BSP_CFG_PFS_PROTECT ((1)) #define BSP_CFG_C_RUNTIME_INIT ((1)) +#define BSP_CFG_EARLY_INIT ((0)) -#define BSP_CFG_SOFT_RESET_SUPPORTED ((0)) +#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) #endif -#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) -#endif + #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) #endif @@ -46,4 +55,8 @@ #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 #endif + +#ifdef __cplusplus +} +#endif #endif /* BSP_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h index 5fc7730d2..40bb3a3bf 100644 --- a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h +++ b/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -2,6 +2,7 @@ #ifndef BSP_MCU_DEVICE_PN_CFG_H_ #define BSP_MCU_DEVICE_PN_CFG_H_ #define BSP_MCU_R7FA6M1AD3CFP +#define BSP_MCU_FEATURE_SET ('A') #define BSP_ROM_SIZE_BYTES (524288) #define BSP_RAM_SIZE_BYTES (262144) #define BSP_DATA_FLASH_SIZE_BYTES (8192) diff --git a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h index 720eee2d7..c299ef170 100644 --- a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ b/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -1,6 +1,10 @@ /* generated configuration header file - do not edit */ #ifndef BSP_MCU_FAMILY_CFG_H_ #define BSP_MCU_FAMILY_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #include "bsp_mcu_device_pn_cfg.h" #include "bsp_mcu_device_cfg.h" #include "../../../ra/fsp/src/bsp/mcu/ra6m1/bsp_mcu_info.h" @@ -23,7 +27,6 @@ #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) -#define BSP_MCU_VBATT_SUPPORT (1) #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) @@ -50,7 +53,9 @@ #define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) #define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) #define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) - +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ #define BSP_PRV_IELS_ENUM(vector) (ELC_##vector) @@ -71,4 +76,8 @@ #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) #endif + +#ifdef __cplusplus +} +#endif #endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_adc_cfg.h b/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_adc_cfg.h index 9c59889ca..be8a42720 100644 --- a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_adc_cfg.h +++ b/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_adc_cfg.h @@ -1,5 +1,13 @@ /* generated configuration header file - do not edit */ #ifndef R_ADC_CFG_H_ #define R_ADC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #define ADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif #endif /* R_ADC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_agt_cfg.h b/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_agt_cfg.h deleted file mode 100644 index d3ab55923..000000000 --- a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_agt_cfg.h +++ /dev/null @@ -1,7 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_AGT_CFG_H_ -#define R_AGT_CFG_H_ -#define AGT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#define AGT_CFG_OUTPUT_SUPPORT_ENABLE (0) -#define AGT_CFG_INPUT_SUPPORT_ENABLE (0) -#endif /* R_AGT_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_dtc_cfg.h b/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_dtc_cfg.h deleted file mode 100644 index 21405f967..000000000 --- a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_dtc_cfg.h +++ /dev/null @@ -1,6 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_DTC_CFG_H_ -#define R_DTC_CFG_H_ -#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#define DTC_CFG_VECTOR_TABLE_SECTION_NAME ".fsp_dtc_vector_table" -#endif /* R_DTC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_flash_hp_cfg.h b/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_flash_hp_cfg.h index 48c9dec4e..9f7819b71 100644 --- a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_flash_hp_cfg.h +++ b/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_flash_hp_cfg.h @@ -1,7 +1,15 @@ /* generated configuration header file - do not edit */ #ifndef R_FLASH_HP_CFG_H_ #define R_FLASH_HP_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #define FLASH_HP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) #define FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (1) #define FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (0) + +#ifdef __cplusplus +} +#endif #endif /* R_FLASH_HP_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_icu_cfg.h b/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_icu_cfg.h deleted file mode 100644 index 5e77b6980..000000000 --- a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_icu_cfg.h +++ /dev/null @@ -1,5 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_ICU_CFG_H_ -#define R_ICU_CFG_H_ -#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#endif /* R_ICU_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_iic_master_cfg.h b/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_iic_master_cfg.h deleted file mode 100644 index 595ea938d..000000000 --- a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_iic_master_cfg.h +++ /dev/null @@ -1,7 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_IIC_MASTER_CFG_H_ -#define R_IIC_MASTER_CFG_H_ -#define IIC_MASTER_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#define IIC_MASTER_CFG_DTC_ENABLE (0) -#define IIC_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE (0) -#endif /* R_IIC_MASTER_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_ioport_cfg.h b/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_ioport_cfg.h index 6b4353d23..d2688bf5b 100644 --- a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_ioport_cfg.h +++ b/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -1,5 +1,13 @@ /* generated configuration header file - do not edit */ #ifndef R_IOPORT_CFG_H_ #define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif #endif /* R_IOPORT_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_lpm_cfg.h b/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_lpm_cfg.h index 5f4d5c4a7..6712eee6a 100644 --- a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_lpm_cfg.h +++ b/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_lpm_cfg.h @@ -1,5 +1,14 @@ /* generated configuration header file - do not edit */ #ifndef R_LPM_CFG_H_ #define R_LPM_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #define LPM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define LPM_CFG_STANDBY_LIMIT (0) + +#ifdef __cplusplus +} +#endif #endif /* R_LPM_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_rtc_cfg.h b/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_rtc_cfg.h deleted file mode 100644 index 484b7ed04..000000000 --- a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_rtc_cfg.h +++ /dev/null @@ -1,5 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_RTC_CFG_H_ -#define R_RTC_CFG_H_ -#define RTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#endif /* R_RTC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_sci_uart_cfg.h b/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_sci_uart_cfg.h deleted file mode 100644 index c70c0be34..000000000 --- a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_sci_uart_cfg.h +++ /dev/null @@ -1,8 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_SCI_UART_CFG_H_ -#define R_SCI_UART_CFG_H_ -#define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#define SCI_UART_CFG_FIFO_SUPPORT (0) -#define SCI_UART_CFG_DTC_SUPPORTED (0) -#define SCI_UART_CFG_FLOW_CONTROL_SUPPORT (0) -#endif /* R_SCI_UART_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_spi_cfg.h b/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_spi_cfg.h deleted file mode 100644 index 861fe1219..000000000 --- a/ports/renesas-ra/boards/EK_RA6M1/ra_cfg/fsp_cfg/r_spi_cfg.h +++ /dev/null @@ -1,7 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_SPI_CFG_H_ -#define R_SPI_CFG_H_ -#define SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#define SPI_DTC_SUPPORT_ENABLE (1) -#define SPI_TRANSMIT_FROM_RXI_ISR (0) -#endif /* R_SPI_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M1/ra_gen/bsp_clock_cfg.h b/ports/renesas-ra/boards/EK_RA6M1/ra_gen/bsp_clock_cfg.h index 013621000..c9775187a 100644 --- a/ports/renesas-ra/boards/EK_RA6M1/ra_gen/bsp_clock_cfg.h +++ b/ports/renesas-ra/boards/EK_RA6M1/ra_gen/bsp_clock_cfg.h @@ -7,7 +7,7 @@ #define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ #define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ #define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_1) /* PLL Div /1 */ -#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL Mul x20.0 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(20U, 0U) /* PLL Mul x20.0 */ #define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ #define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */ #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ @@ -15,7 +15,7 @@ #define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ #define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ #define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ -#define BSP_CFG_BCLK_OUTPUT (2) /* BCK/2 */ +#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */ #define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ #define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ #define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ diff --git a/ports/renesas-ra/boards/EK_RA6M1/ra_gen/common_data.c b/ports/renesas-ra/boards/EK_RA6M1/ra_gen/common_data.c index 34aad762f..ceee4985e 100644 --- a/ports/renesas-ra/boards/EK_RA6M1/ra_gen/common_data.c +++ b/ports/renesas-ra/boards/EK_RA6M1/ra_gen/common_data.c @@ -1,7 +1,4 @@ -/* generated common source file - do not edit */ #include "common_data.h" ioport_instance_ctrl_t g_ioport_ctrl; const ioport_instance_t g_ioport = { .p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg, }; -void g_common_init(void) { -} diff --git a/ports/renesas-ra/boards/EK_RA6M1/ra_gen/common_data.h b/ports/renesas-ra/boards/EK_RA6M1/ra_gen/common_data.h index e2eb70836..3a764eda7 100644 --- a/ports/renesas-ra/boards/EK_RA6M1/ra_gen/common_data.h +++ b/ports/renesas-ra/boards/EK_RA6M1/ra_gen/common_data.h @@ -3,14 +3,16 @@ #define COMMON_DATA_H_ #include <stdint.h> #include "bsp_api.h" +#include "r_icu.h" +#include "r_external_irq_api.h" #include "r_ioport.h" #include "bsp_pin_cfg.h" FSP_HEADER + /* IOPORT Instance */ extern const ioport_instance_t g_ioport; /* IOPORT control structure. */ extern ioport_instance_ctrl_t g_ioport_ctrl; -void g_common_init(void); FSP_FOOTER #endif /* COMMON_DATA_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M1/ra_gen/hal_data.c b/ports/renesas-ra/boards/EK_RA6M1/ra_gen/hal_data.c index 56f173511..bfc382ec1 100644 --- a/ports/renesas-ra/boards/EK_RA6M1/ra_gen/hal_data.c +++ b/ports/renesas-ra/boards/EK_RA6M1/ra_gen/hal_data.c @@ -1,131 +1,15 @@ -/* generated HAL source file - do not edit */ #include "hal_data.h" -/* Macros to tie dynamic ELC links to ADC_TRIGGER_SYNC_ELC option in adc_trigger_t. */ -#define ADC_TRIGGER_ADC0 ADC_TRIGGER_SYNC_ELC -#define ADC_TRIGGER_ADC0_B ADC_TRIGGER_SYNC_ELC -#define ADC_TRIGGER_ADC1 ADC_TRIGGER_SYNC_ELC -#define ADC_TRIGGER_ADC1_B ADC_TRIGGER_SYNC_ELC -adc_instance_ctrl_t g_adc1_ctrl; -const adc_extended_cfg_t g_adc1_cfg_extend = -{ .add_average_count = ADC_ADD_OFF, - .clearing = ADC_CLEAR_AFTER_READ_ON, - .trigger_group_b = ADC_TRIGGER_SYNC_ELC, - .double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED, - .adc_vref_control = ADC_VREF_CONTROL_VREFH, }; -const adc_cfg_t g_adc1_cfg = -{ .unit = 1, .mode = ADC_MODE_SINGLE_SCAN, .resolution = ADC_RESOLUTION_12_BIT, .alignment = - (adc_alignment_t)ADC_ALIGNMENT_RIGHT, - .trigger = ADC_TRIGGER_SOFTWARE, .p_callback = NULL, .p_context = NULL, .p_extend = &g_adc1_cfg_extend, - #if defined(VECTOR_NUMBER_ADC1_SCAN_END) - .scan_end_irq = VECTOR_NUMBER_ADC1_SCAN_END, - #else - .scan_end_irq = FSP_INVALID_VECTOR, - #endif - .scan_end_ipl = (BSP_IRQ_DISABLED), - #if defined(VECTOR_NUMBER_ADC1_SCAN_END_B) - .scan_end_b_irq = VECTOR_NUMBER_ADC1_SCAN_END_B, - #else - .scan_end_b_irq = FSP_INVALID_VECTOR, - #endif - .scan_end_b_ipl = (BSP_IRQ_DISABLED), }; -const adc_channel_cfg_t g_adc1_channel_cfg = -{ .scan_mask = 0, - .scan_mask_group_b = 0, - .priority_group_a = ADC_GROUP_A_PRIORITY_OFF, - .add_mask = 0, - .sample_hold_mask = 0, - .sample_hold_states = 24, }; -/* Instance structure to use this module. */ -const adc_instance_t g_adc1 = -{ .p_ctrl = &g_adc1_ctrl, .p_cfg = &g_adc1_cfg, .p_channel_cfg = &g_adc1_channel_cfg, .p_api = &g_adc_on_adc }; -iic_master_instance_ctrl_t g_i2c_master0_ctrl; -const iic_master_extended_cfg_t g_i2c_master0_extend = -{ .timeout_mode = IIC_MASTER_TIMEOUT_MODE_SHORT, -/* Actual calculated bitrate: 98945. Actual calculated duty cycle: 51%. */ .clock_settings.brl_value = 15, - .clock_settings.brh_value = 16, .clock_settings.cks_value = 4, }; -const i2c_master_cfg_t g_i2c_master0_cfg = -{ .channel = 0, .rate = I2C_MASTER_RATE_STANDARD, .slave = 0x00, .addr_mode = I2C_MASTER_ADDR_MODE_7BIT, -#define RA_NOT_DEFINED (1) - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_tx = NULL, - #else - .p_transfer_tx = &RA_NOT_DEFINED, - #endif - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_rx = NULL, - #else - .p_transfer_rx = &RA_NOT_DEFINED, - #endif -#undef RA_NOT_DEFINED - .p_callback = callback_iic, - .p_context = NULL, - #if defined(VECTOR_NUMBER_IIC0_RXI) - .rxi_irq = VECTOR_NUMBER_IIC0_RXI, - #else - .rxi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_IIC0_TXI) - .txi_irq = VECTOR_NUMBER_IIC0_TXI, - #else - .txi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_IIC0_TEI) - .tei_irq = VECTOR_NUMBER_IIC0_TEI, - #else - .tei_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_IIC0_ERI) - .eri_irq = VECTOR_NUMBER_IIC0_ERI, - #else - .eri_irq = FSP_INVALID_VECTOR, - #endif - .ipl = (12), - .p_extend = &g_i2c_master0_extend, }; -/* Instance structure to use this module. */ -const i2c_master_instance_t g_i2c_master0 = -{ .p_ctrl = &g_i2c_master0_ctrl, .p_cfg = &g_i2c_master0_cfg, .p_api = &g_i2c_master_on_iic }; -adc_instance_ctrl_t g_adc0_ctrl; -const adc_extended_cfg_t g_adc0_cfg_extend = -{ .add_average_count = ADC_ADD_OFF, - .clearing = ADC_CLEAR_AFTER_READ_ON, - .trigger_group_b = ADC_TRIGGER_SYNC_ELC, - .double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED, - .adc_vref_control = ADC_VREF_CONTROL_VREFH, }; -const adc_cfg_t g_adc0_cfg = -{ .unit = 0, .mode = ADC_MODE_SINGLE_SCAN, .resolution = ADC_RESOLUTION_12_BIT, .alignment = - (adc_alignment_t)ADC_ALIGNMENT_RIGHT, - .trigger = ADC_TRIGGER_SOFTWARE, .p_callback = NULL, .p_context = NULL, .p_extend = &g_adc0_cfg_extend, - #if defined(VECTOR_NUMBER_ADC0_SCAN_END) - .scan_end_irq = VECTOR_NUMBER_ADC0_SCAN_END, - #else - .scan_end_irq = FSP_INVALID_VECTOR, - #endif - .scan_end_ipl = (BSP_IRQ_DISABLED), - #if defined(VECTOR_NUMBER_ADC0_SCAN_END_B) - .scan_end_b_irq = VECTOR_NUMBER_ADC0_SCAN_END_B, - #else - .scan_end_b_irq = FSP_INVALID_VECTOR, - #endif - .scan_end_b_ipl = (BSP_IRQ_DISABLED), }; -const adc_channel_cfg_t g_adc0_channel_cfg = -{ .scan_mask = 0, - .scan_mask_group_b = 0, - .priority_group_a = ADC_GROUP_A_PRIORITY_OFF, - .add_mask = 0, - .sample_hold_mask = 0, - .sample_hold_states = 24, }; -/* Instance structure to use this module. */ -const adc_instance_t g_adc0 = -{ .p_ctrl = &g_adc0_ctrl, .p_cfg = &g_adc0_cfg, .p_channel_cfg = &g_adc0_channel_cfg, .p_api = &g_adc_on_adc }; lpm_instance_ctrl_t g_lpm0_ctrl; const lpm_cfg_t g_lpm0_cfg = -{ .low_power_mode = LPM_MODE_SLEEP, +{ .low_power_mode = LPM_MODE_SLEEP, .standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM + | (lpm_standby_wake_source_t)0, + #if BSP_FEATURE_LPM_HAS_SNOOZE .snooze_cancel_sources = LPM_SNOOZE_CANCEL_SOURCE_NONE, - .standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM | (lpm_standby_wake_source_t)0, .snooze_request_source = LPM_SNOOZE_REQUEST_RXD0_FALLING, .snooze_end_sources = (lpm_snooze_end_t)0, .dtc_state_in_snooze = LPM_SNOOZE_DTC_DISABLE, + #endif #if BSP_FEATURE_LPM_HAS_SBYCR_OPE .output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN, #endif @@ -135,449 +19,23 @@ const lpm_cfg_t g_lpm0_cfg = .deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0, .deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0, #endif - .p_extend = NULL, }; - -const lpm_instance_t g_lpm0 = -{ .p_api = &g_lpm_on_lpm, .p_ctrl = &g_lpm0_ctrl, .p_cfg = &g_lpm0_cfg }; -dtc_instance_ctrl_t g_transfer1_ctrl; - -transfer_info_t g_transfer1_info = -{ .dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, - .repeat_area = TRANSFER_REPEAT_AREA_DESTINATION, - .irq = TRANSFER_IRQ_END, - .chain_mode = TRANSFER_CHAIN_MODE_DISABLED, - .src_addr_mode = TRANSFER_ADDR_MODE_FIXED, - .size = TRANSFER_SIZE_2_BYTE, - .mode = TRANSFER_MODE_NORMAL, - .p_dest = (void *)NULL, - .p_src = (void const *)NULL, - .num_blocks = 0, - .length = 0, }; -const dtc_extended_cfg_t g_transfer1_cfg_extend = -{ .activation_source = VECTOR_NUMBER_SPI0_RXI, }; -const transfer_cfg_t g_transfer1_cfg = -{ .p_info = &g_transfer1_info, .p_extend = &g_transfer1_cfg_extend, }; - -/* Instance structure to use this module. */ -const transfer_instance_t g_transfer1 = -{ .p_ctrl = &g_transfer1_ctrl, .p_cfg = &g_transfer1_cfg, .p_api = &g_transfer_on_dtc }; -dtc_instance_ctrl_t g_transfer0_ctrl; - -transfer_info_t g_transfer0_info = -{ .dest_addr_mode = TRANSFER_ADDR_MODE_FIXED, - .repeat_area = TRANSFER_REPEAT_AREA_SOURCE, - .irq = TRANSFER_IRQ_END, - .chain_mode = TRANSFER_CHAIN_MODE_DISABLED, - .src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, - .size = TRANSFER_SIZE_2_BYTE, - .mode = TRANSFER_MODE_NORMAL, - .p_dest = (void *)NULL, - .p_src = (void const *)NULL, - .num_blocks = 0, - .length = 0, }; -const dtc_extended_cfg_t g_transfer0_cfg_extend = -{ .activation_source = VECTOR_NUMBER_SPI0_TXI, }; -const transfer_cfg_t g_transfer0_cfg = -{ .p_info = &g_transfer0_info, .p_extend = &g_transfer0_cfg_extend, }; - -/* Instance structure to use this module. */ -const transfer_instance_t g_transfer0 = -{ .p_ctrl = &g_transfer0_ctrl, .p_cfg = &g_transfer0_cfg, .p_api = &g_transfer_on_dtc }; -spi_instance_ctrl_t g_spi0_ctrl; - -/** SPI extended configuration for SPI HAL driver */ -const spi_extended_cfg_t g_spi0_ext_cfg = -{ .spi_clksyn = SPI_SSL_MODE_CLK_SYN, - .spi_comm = SPI_COMMUNICATION_FULL_DUPLEX, - .ssl_polarity = SPI_SSLP_LOW, - .ssl_select = SPI_SSL_SELECT_SSL0, - .mosi_idle = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE, - .parity = SPI_PARITY_MODE_DISABLE, - .byte_swap = SPI_BYTE_SWAP_DISABLE, - .spck_div = - { - /* Actual calculated bitrate: 15000000. */ .spbr = 3, - .brdv = 0 - }, - .spck_delay = SPI_DELAY_COUNT_1, - .ssl_negation_delay = SPI_DELAY_COUNT_1, - .next_access_delay = SPI_DELAY_COUNT_1 }; - -/** SPI configuration for SPI HAL driver */ -const spi_cfg_t g_spi0_cfg = -{ .channel = 0, - - #if defined(VECTOR_NUMBER_SPI0_RXI) - .rxi_irq = VECTOR_NUMBER_SPI0_RXI, - #else - .rxi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SPI0_TXI) - .txi_irq = VECTOR_NUMBER_SPI0_TXI, - #else - .txi_irq = FSP_INVALID_VECTOR, + #if BSP_FEATURE_LPM_HAS_PDRAMSCR + .ram_retention_cfg.ram_retention = (uint8_t)(0), + .ram_retention_cfg.tcm_retention = false, #endif - #if defined(VECTOR_NUMBER_SPI0_TEI) - .tei_irq = VECTOR_NUMBER_SPI0_TEI, - #else - .tei_irq = FSP_INVALID_VECTOR, + #if BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP + .ram_retention_cfg.standby_ram_retention = false, #endif - #if defined(VECTOR_NUMBER_SPI0_ERI) - .eri_irq = VECTOR_NUMBER_SPI0_ERI, - #else - .eri_irq = FSP_INVALID_VECTOR, + #if BSP_FEATURE_LPM_HAS_LDO_CONTROL + .ldo_standby_cfg.pll1_ldo = false, + .ldo_standby_cfg.pll2_ldo = false, + .ldo_standby_cfg.hoco_ldo = false, #endif + .p_extend = NULL, }; - .rxi_ipl = (12), - .txi_ipl = (12), - .tei_ipl = (12), - .eri_ipl = (12), - - .operating_mode = SPI_MODE_MASTER, - - .clk_phase = SPI_CLK_PHASE_EDGE_ODD, - .clk_polarity = SPI_CLK_POLARITY_LOW, - - .mode_fault = SPI_MODE_FAULT_ERROR_DISABLE, - .bit_order = SPI_BIT_ORDER_MSB_FIRST, - .p_transfer_tx = g_spi0_P_TRANSFER_TX, - .p_transfer_rx = g_spi0_P_TRANSFER_RX, - .p_callback = spi_callback, - - .p_context = NULL, - .p_extend = (void *)&g_spi0_ext_cfg, }; +const lpm_instance_t g_lpm0 = +{ .p_api = &g_lpm_on_lpm, .p_ctrl = &g_lpm0_ctrl, .p_cfg = &g_lpm0_cfg }; -/* Instance structure to use this module. */ -const spi_instance_t g_spi0 = -{ .p_ctrl = &g_spi0_ctrl, .p_cfg = &g_spi0_cfg, .p_api = &g_spi_on_spi }; -icu_instance_ctrl_t g_external_irq13_ctrl; -const external_irq_cfg_t g_external_irq13_cfg = -{ .channel = 13, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ13) - .irq = VECTOR_NUMBER_ICU_IRQ13, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq13 = -{ .p_ctrl = &g_external_irq13_ctrl, .p_cfg = &g_external_irq13_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq12_ctrl; -const external_irq_cfg_t g_external_irq12_cfg = -{ .channel = 12, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ12) - .irq = VECTOR_NUMBER_ICU_IRQ12, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq12 = -{ .p_ctrl = &g_external_irq12_ctrl, .p_cfg = &g_external_irq12_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq11_ctrl; -const external_irq_cfg_t g_external_irq11_cfg = -{ .channel = 11, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ11) - .irq = VECTOR_NUMBER_ICU_IRQ11, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq11 = -{ .p_ctrl = &g_external_irq11_ctrl, .p_cfg = &g_external_irq11_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq10_ctrl; -const external_irq_cfg_t g_external_irq10_cfg = -{ .channel = 10, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ10) - .irq = VECTOR_NUMBER_ICU_IRQ10, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq10 = -{ .p_ctrl = &g_external_irq10_ctrl, .p_cfg = &g_external_irq10_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq9_ctrl; -const external_irq_cfg_t g_external_irq9_cfg = -{ .channel = 9, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ9) - .irq = VECTOR_NUMBER_ICU_IRQ9, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq9 = -{ .p_ctrl = &g_external_irq9_ctrl, .p_cfg = &g_external_irq9_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq8_ctrl; -const external_irq_cfg_t g_external_irq8_cfg = -{ .channel = 8, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ8) - .irq = VECTOR_NUMBER_ICU_IRQ8, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq8 = -{ .p_ctrl = &g_external_irq8_ctrl, .p_cfg = &g_external_irq8_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq7_ctrl; -const external_irq_cfg_t g_external_irq7_cfg = -{ .channel = 7, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ7) - .irq = VECTOR_NUMBER_ICU_IRQ7, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq7 = -{ .p_ctrl = &g_external_irq7_ctrl, .p_cfg = &g_external_irq7_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq6_ctrl; -const external_irq_cfg_t g_external_irq6_cfg = -{ .channel = 6, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ6) - .irq = VECTOR_NUMBER_ICU_IRQ6, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq6 = -{ .p_ctrl = &g_external_irq6_ctrl, .p_cfg = &g_external_irq6_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq5_ctrl; -const external_irq_cfg_t g_external_irq5_cfg = -{ .channel = 5, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ5) - .irq = VECTOR_NUMBER_ICU_IRQ5, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq5 = -{ .p_ctrl = &g_external_irq5_ctrl, .p_cfg = &g_external_irq5_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq4_ctrl; -const external_irq_cfg_t g_external_irq4_cfg = -{ .channel = 4, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ4) - .irq = VECTOR_NUMBER_ICU_IRQ4, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq4 = -{ .p_ctrl = &g_external_irq4_ctrl, .p_cfg = &g_external_irq4_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq3_ctrl; -const external_irq_cfg_t g_external_irq3_cfg = -{ .channel = 3, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ3) - .irq = VECTOR_NUMBER_ICU_IRQ3, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq3 = -{ .p_ctrl = &g_external_irq3_ctrl, .p_cfg = &g_external_irq3_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq2_ctrl; -const external_irq_cfg_t g_external_irq2_cfg = -{ .channel = 2, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ2) - .irq = VECTOR_NUMBER_ICU_IRQ2, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq2 = -{ .p_ctrl = &g_external_irq2_ctrl, .p_cfg = &g_external_irq2_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq1_ctrl; -const external_irq_cfg_t g_external_irq1_cfg = -{ .channel = 1, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ1) - .irq = VECTOR_NUMBER_ICU_IRQ1, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq1 = -{ .p_ctrl = &g_external_irq1_ctrl, .p_cfg = &g_external_irq1_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq0_ctrl; -const external_irq_cfg_t g_external_irq0_cfg = -{ .channel = 0, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ0) - .irq = VECTOR_NUMBER_ICU_IRQ0, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq0 = -{ .p_ctrl = &g_external_irq0_ctrl, .p_cfg = &g_external_irq0_cfg, .p_api = &g_external_irq_on_icu }; -agt_instance_ctrl_t g_timer1_ctrl; -const agt_extended_cfg_t g_timer1_extend = -{ .count_source = AGT_CLOCK_PCLKB, - .agto = AGT_PIN_CFG_DISABLED, - .agtoa = AGT_PIN_CFG_DISABLED, - .agtob = AGT_PIN_CFG_DISABLED, - .measurement_mode = AGT_MEASURE_DISABLED, - .agtio_filter = AGT_AGTIO_FILTER_NONE, - .enable_pin = AGT_ENABLE_PIN_NOT_USED, - .trigger_edge = AGT_TRIGGER_EDGE_RISING, }; -const timer_cfg_t g_timer1_cfg = -{ .mode = TIMER_MODE_PERIODIC, -/* Actual period: 0.0010922666666666667 seconds. Actual duty: 50%. */ .period_counts = 0x10000, - .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 1, .p_callback = callback_agt, - /** If NULL then do not add & */ - #if defined(NULL) - .p_context = NULL, - #else - .p_context = &NULL, - #endif - .p_extend = &g_timer1_extend, - .cycle_end_ipl = (5), - #if defined(VECTOR_NUMBER_AGT1_INT) - .cycle_end_irq = VECTOR_NUMBER_AGT1_INT, - #else - .cycle_end_irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const timer_instance_t g_timer1 = -{ .p_ctrl = &g_timer1_ctrl, .p_cfg = &g_timer1_cfg, .p_api = &g_timer_on_agt }; -agt_instance_ctrl_t g_timer0_ctrl; -const agt_extended_cfg_t g_timer0_extend = -{ .count_source = AGT_CLOCK_PCLKB, - .agto = AGT_PIN_CFG_DISABLED, - .agtoa = AGT_PIN_CFG_DISABLED, - .agtob = AGT_PIN_CFG_DISABLED, - .measurement_mode = AGT_MEASURE_DISABLED, - .agtio_filter = AGT_AGTIO_FILTER_NONE, - .enable_pin = AGT_ENABLE_PIN_NOT_USED, - .trigger_edge = AGT_TRIGGER_EDGE_RISING, }; -const timer_cfg_t g_timer0_cfg = -{ .mode = TIMER_MODE_PERIODIC, -/* Actual period: 0.0010922666666666667 seconds. Actual duty: 50%. */ .period_counts = 0x10000, - .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 0, .p_callback = callback_agt, - /** If NULL then do not add & */ - #if defined(NULL) - .p_context = NULL, - #else - .p_context = &NULL, - #endif - .p_extend = &g_timer0_extend, - .cycle_end_ipl = (5), - #if defined(VECTOR_NUMBER_AGT0_INT) - .cycle_end_irq = VECTOR_NUMBER_AGT0_INT, - #else - .cycle_end_irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const timer_instance_t g_timer0 = -{ .p_ctrl = &g_timer0_ctrl, .p_cfg = &g_timer0_cfg, .p_api = &g_timer_on_agt }; flash_hp_instance_ctrl_t g_flash0_ctrl; const flash_cfg_t g_flash0_cfg = { .data_flash_bgo = false, .p_callback = NULL, .p_context = NULL, @@ -596,239 +54,3 @@ const flash_cfg_t g_flash0_cfg = /* Instance structure to use this module. */ const flash_instance_t g_flash0 = { .p_ctrl = &g_flash0_ctrl, .p_cfg = &g_flash0_cfg, .p_api = &g_flash_on_flash_hp }; -rtc_instance_ctrl_t g_rtc0_ctrl; -const rtc_error_adjustment_cfg_t g_rtc0_err_cfg = -{ .adjustment_mode = RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC, - .adjustment_period = RTC_ERROR_ADJUSTMENT_PERIOD_10_SECOND, - .adjustment_type = RTC_ERROR_ADJUSTMENT_NONE, - .adjustment_value = 0, }; -const rtc_cfg_t g_rtc0_cfg = -{ .clock_source = RTC_CLOCK_SOURCE_LOCO, .freq_compare_value_loco = 255, .p_err_cfg = &g_rtc0_err_cfg, .p_callback = - NULL, - .p_context = NULL, .alarm_ipl = (14), .periodic_ipl = (14), .carry_ipl = (14), - #if defined(VECTOR_NUMBER_RTC_ALARM) - .alarm_irq = VECTOR_NUMBER_RTC_ALARM, - #else - .alarm_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_RTC_PERIOD) - .periodic_irq = VECTOR_NUMBER_RTC_PERIOD, - #else - .periodic_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_RTC_CARRY) - .carry_irq = VECTOR_NUMBER_RTC_CARRY, - #else - .carry_irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const rtc_instance_t g_rtc0 = -{ .p_ctrl = &g_rtc0_ctrl, .p_cfg = &g_rtc0_cfg, .p_api = &g_rtc_on_rtc }; -sci_uart_instance_ctrl_t g_uart8_ctrl; - -baud_setting_t g_uart8_baud_setting = -{ -/* Baud rate calculated with 0.160% error. */ .abcse = 0, - .abcs = 0, .bgdm = 1, .cks = 0, .brr = 64, .mddr = (uint8_t)256, .brme = false -}; - -/** UART extended configuration for UARTonSCI HAL driver */ -const sci_uart_extended_cfg_t g_uart8_cfg_extend = -{ .clock = SCI_UART_CLOCK_INT, - .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, - .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, - .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, - .p_baud_setting = &g_uart8_baud_setting, - .uart_mode = UART_MODE_RS232, - .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, - #if 0 - .flow_control_pin = BSP_IO_PORT_00_PIN_00, - #else - .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), - #endif -}; - -/** UART interface configuration */ -const uart_cfg_t g_uart8_cfg = -{ .channel = 8, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = - user_uart_callback, - .p_context = NULL, .p_extend = &g_uart8_cfg_extend, -#define RA_NOT_DEFINED (1) - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_tx = NULL, - #else - .p_transfer_tx = &RA_NOT_DEFINED, - #endif - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_rx = NULL, - #else - .p_transfer_rx = &RA_NOT_DEFINED, - #endif -#undef RA_NOT_DEFINED - .rxi_ipl = (12), - .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), - #if defined(VECTOR_NUMBER_SCI8_RXI) - .rxi_irq = VECTOR_NUMBER_SCI8_RXI, - #else - .rxi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI8_TXI) - .txi_irq = VECTOR_NUMBER_SCI8_TXI, - #else - .txi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI8_TEI) - .tei_irq = VECTOR_NUMBER_SCI8_TEI, - #else - .tei_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI8_ERI) - .eri_irq = VECTOR_NUMBER_SCI8_ERI, - #else - .eri_irq = FSP_INVALID_VECTOR, - #endif -}; - -/* Instance structure to use this module. */ -const uart_instance_t g_uart8 = -{ .p_ctrl = &g_uart8_ctrl, .p_cfg = &g_uart8_cfg, .p_api = &g_uart_on_sci }; -sci_uart_instance_ctrl_t g_uart2_ctrl; - -baud_setting_t g_uart2_baud_setting = -{ -/* Baud rate calculated with 0.160% error. */ .abcse = 0, - .abcs = 0, .bgdm = 1, .cks = 0, .brr = 64, .mddr = (uint8_t)256, .brme = false -}; - -/** UART extended configuration for UARTonSCI HAL driver */ -const sci_uart_extended_cfg_t g_uart2_cfg_extend = -{ .clock = SCI_UART_CLOCK_INT, - .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, - .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, - .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, - .p_baud_setting = &g_uart2_baud_setting, - .uart_mode = UART_MODE_RS232, - .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, - #if 0 - .flow_control_pin = BSP_IO_PORT_00_PIN_00, - #else - .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), - #endif -}; - -/** UART interface configuration */ -const uart_cfg_t g_uart2_cfg = -{ .channel = 2, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = - user_uart_callback, - .p_context = NULL, .p_extend = &g_uart2_cfg_extend, -#define RA_NOT_DEFINED (1) - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_tx = NULL, - #else - .p_transfer_tx = &RA_NOT_DEFINED, - #endif - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_rx = NULL, - #else - .p_transfer_rx = &RA_NOT_DEFINED, - #endif -#undef RA_NOT_DEFINED - .rxi_ipl = (12), - .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), - #if defined(VECTOR_NUMBER_SCI2_RXI) - .rxi_irq = VECTOR_NUMBER_SCI2_RXI, - #else - .rxi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI2_TXI) - .txi_irq = VECTOR_NUMBER_SCI2_TXI, - #else - .txi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI2_TEI) - .tei_irq = VECTOR_NUMBER_SCI2_TEI, - #else - .tei_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI2_ERI) - .eri_irq = VECTOR_NUMBER_SCI2_ERI, - #else - .eri_irq = FSP_INVALID_VECTOR, - #endif -}; - -/* Instance structure to use this module. */ -const uart_instance_t g_uart2 = -{ .p_ctrl = &g_uart2_ctrl, .p_cfg = &g_uart2_cfg, .p_api = &g_uart_on_sci }; -sci_uart_instance_ctrl_t g_uart0_ctrl; - -baud_setting_t g_uart0_baud_setting = -{ -/* Baud rate calculated with 0.160% error. */ .abcse = 0, - .abcs = 0, .bgdm = 1, .cks = 0, .brr = 64, .mddr = (uint8_t)256, .brme = false -}; - -/** UART extended configuration for UARTonSCI HAL driver */ -const sci_uart_extended_cfg_t g_uart0_cfg_extend = -{ .clock = SCI_UART_CLOCK_INT, - .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, - .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, - .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, - .p_baud_setting = &g_uart0_baud_setting, - .uart_mode = UART_MODE_RS232, - .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, - #if 0 - .flow_control_pin = BSP_IO_PORT_00_PIN_00, - #else - .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), - #endif -}; - -/** UART interface configuration */ -const uart_cfg_t g_uart0_cfg = -{ .channel = 0, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = - user_uart_callback, - .p_context = NULL, .p_extend = &g_uart0_cfg_extend, -#define RA_NOT_DEFINED (1) - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_tx = NULL, - #else - .p_transfer_tx = &RA_NOT_DEFINED, - #endif - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_rx = NULL, - #else - .p_transfer_rx = &RA_NOT_DEFINED, - #endif -#undef RA_NOT_DEFINED - .rxi_ipl = (12), - .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), - #if defined(VECTOR_NUMBER_SCI0_RXI) - .rxi_irq = VECTOR_NUMBER_SCI0_RXI, - #else - .rxi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI0_TXI) - .txi_irq = VECTOR_NUMBER_SCI0_TXI, - #else - .txi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI0_TEI) - .tei_irq = VECTOR_NUMBER_SCI0_TEI, - #else - .tei_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI0_ERI) - .eri_irq = VECTOR_NUMBER_SCI0_ERI, - #else - .eri_irq = FSP_INVALID_VECTOR, - #endif -}; - -/* Instance structure to use this module. */ -const uart_instance_t g_uart0 = -{ .p_ctrl = &g_uart0_ctrl, .p_cfg = &g_uart0_cfg, .p_api = &g_uart_on_sci }; -void g_hal_init(void) { - g_common_init(); -} diff --git a/ports/renesas-ra/boards/EK_RA6M1/ra_gen/hal_data.h b/ports/renesas-ra/boards/EK_RA6M1/ra_gen/hal_data.h index d8773ab5e..c661dfb18 100644 --- a/ports/renesas-ra/boards/EK_RA6M1/ra_gen/hal_data.h +++ b/ports/renesas-ra/boards/EK_RA6M1/ra_gen/hal_data.h @@ -2,262 +2,20 @@ #ifndef HAL_DATA_H_ #define HAL_DATA_H_ #include <stdint.h> -#include "bsp_api.h" #include "common_data.h" -#include "r_adc.h" -#include "r_adc_api.h" -#include "r_iic_master.h" -#include "r_i2c_master_api.h" #include "r_lpm.h" #include "r_lpm_api.h" -#include "r_dtc.h" -#include "r_transfer_api.h" -#include "r_spi.h" -#include "r_icu.h" -#include "r_external_irq_api.h" -#include "r_agt.h" -#include "r_timer_api.h" #include "r_flash_hp.h" #include "r_flash_api.h" -#include "r_rtc.h" -#include "r_rtc_api.h" -#include "r_sci_uart.h" -#include "r_uart_api.h" FSP_HEADER -/** ADC on ADC Instance. */ -extern const adc_instance_t g_adc1; -/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */ -extern adc_instance_ctrl_t g_adc1_ctrl; -extern const adc_cfg_t g_adc1_cfg; -extern const adc_channel_cfg_t g_adc1_channel_cfg; - -#ifndef NULL -void NULL(adc_callback_args_t *p_args); -#endif -/* I2C Master on IIC Instance. */ -extern const i2c_master_instance_t g_i2c_master0; - -/** Access the I2C Master instance using these structures when calling API functions directly (::p_api is not used). */ -extern iic_master_instance_ctrl_t g_i2c_master0_ctrl; -extern const i2c_master_cfg_t g_i2c_master0_cfg; - -#ifndef callback_iic -void callback_iic(i2c_master_callback_args_t *p_args); -#endif -/** ADC on ADC Instance. */ -extern const adc_instance_t g_adc0; - -/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */ -extern adc_instance_ctrl_t g_adc0_ctrl; -extern const adc_cfg_t g_adc0_cfg; -extern const adc_channel_cfg_t g_adc0_channel_cfg; - -#ifndef NULL -void NULL(adc_callback_args_t *p_args); -#endif /** lpm Instance */ extern const lpm_instance_t g_lpm0; /** Access the LPM instance using these structures when calling API functions directly (::p_api is not used). */ extern lpm_instance_ctrl_t g_lpm0_ctrl; extern const lpm_cfg_t g_lpm0_cfg; -/* Transfer on DTC Instance. */ -extern const transfer_instance_t g_transfer1; - -/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ -extern dtc_instance_ctrl_t g_transfer1_ctrl; -extern const transfer_cfg_t g_transfer1_cfg; -/* Transfer on DTC Instance. */ -extern const transfer_instance_t g_transfer0; - -/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ -extern dtc_instance_ctrl_t g_transfer0_ctrl; -extern const transfer_cfg_t g_transfer0_cfg; -/** SPI on SPI Instance. */ -extern const spi_instance_t g_spi0; - -/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */ -extern spi_instance_ctrl_t g_spi0_ctrl; -extern const spi_cfg_t g_spi0_cfg; - -/** Callback used by SPI Instance. */ -#ifndef spi_callback -void spi_callback(spi_callback_args_t *p_args); -#endif - -#define RA_NOT_DEFINED (1) -#if (RA_NOT_DEFINED == g_transfer0) - #define g_spi0_P_TRANSFER_TX (NULL) -#else -#define g_spi0_P_TRANSFER_TX (&g_transfer0) -#endif -#if (RA_NOT_DEFINED == g_transfer1) - #define g_spi0_P_TRANSFER_RX (NULL) -#else -#define g_spi0_P_TRANSFER_RX (&g_transfer1) -#endif -#undef RA_NOT_DEFINED -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq13; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq13_ctrl; -extern const external_irq_cfg_t g_external_irq13_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq12; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq12_ctrl; -extern const external_irq_cfg_t g_external_irq12_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq11; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq11_ctrl; -extern const external_irq_cfg_t g_external_irq11_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq10; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq10_ctrl; -extern const external_irq_cfg_t g_external_irq10_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq9; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq9_ctrl; -extern const external_irq_cfg_t g_external_irq9_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq8; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq8_ctrl; -extern const external_irq_cfg_t g_external_irq8_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq7; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq7_ctrl; -extern const external_irq_cfg_t g_external_irq7_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq6; -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq6_ctrl; -extern const external_irq_cfg_t g_external_irq6_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq5; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq5_ctrl; -extern const external_irq_cfg_t g_external_irq5_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq4; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq4_ctrl; -extern const external_irq_cfg_t g_external_irq4_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq3; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq3_ctrl; -extern const external_irq_cfg_t g_external_irq3_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq2; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq2_ctrl; -extern const external_irq_cfg_t g_external_irq2_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq1; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq1_ctrl; -extern const external_irq_cfg_t g_external_irq1_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq0; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq0_ctrl; -extern const external_irq_cfg_t g_external_irq0_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** AGT Timer Instance */ -extern const timer_instance_t g_timer1; - -/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ -extern agt_instance_ctrl_t g_timer1_ctrl; -extern const timer_cfg_t g_timer1_cfg; - -#ifndef callback_agt -void callback_agt(timer_callback_args_t *p_args); -#endif -/** AGT Timer Instance */ -extern const timer_instance_t g_timer0; - -/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ -extern agt_instance_ctrl_t g_timer0_ctrl; -extern const timer_cfg_t g_timer0_cfg; - -#ifndef callback_agt -void callback_agt(timer_callback_args_t *p_args); -#endif /* Flash on Flash HP Instance */ extern const flash_instance_t g_flash0; @@ -268,50 +26,8 @@ extern const flash_cfg_t g_flash0_cfg; #ifndef NULL void NULL(flash_callback_args_t *p_args); #endif -/* RTC Instance. */ -extern const rtc_instance_t g_rtc0; - -/** Access the RTC instance using these structures when calling API functions directly (::p_api is not used). */ -extern rtc_instance_ctrl_t g_rtc0_ctrl; -extern const rtc_cfg_t g_rtc0_cfg; - -#ifndef NULL -void NULL(rtc_callback_args_t *p_args); -#endif -/** UART on SCI Instance. */ -extern const uart_instance_t g_uart8; -/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ -extern sci_uart_instance_ctrl_t g_uart8_ctrl; -extern const uart_cfg_t g_uart8_cfg; -extern const sci_uart_extended_cfg_t g_uart8_cfg_extend; - -#ifndef user_uart_callback -void user_uart_callback(uart_callback_args_t *p_args); -#endif -/** UART on SCI Instance. */ -extern const uart_instance_t g_uart2; - -/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ -extern sci_uart_instance_ctrl_t g_uart2_ctrl; -extern const uart_cfg_t g_uart2_cfg; -extern const sci_uart_extended_cfg_t g_uart2_cfg_extend; - -#ifndef user_uart_callback -void user_uart_callback(uart_callback_args_t *p_args); -#endif -/** UART on SCI Instance. */ -extern const uart_instance_t g_uart0; - -/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ -extern sci_uart_instance_ctrl_t g_uart0_ctrl; -extern const uart_cfg_t g_uart0_cfg; -extern const sci_uart_extended_cfg_t g_uart0_cfg_extend; - -#ifndef user_uart_callback -void user_uart_callback(uart_callback_args_t *p_args); -#endif void hal_entry(void); -void g_hal_init(void); + FSP_FOOTER #endif /* HAL_DATA_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M1/ra_gen/pin_data.c b/ports/renesas-ra/boards/EK_RA6M1/ra_gen/pin_data.c index a2ddad010..164aeaa58 100644 --- a/ports/renesas-ra/boards/EK_RA6M1/ra_gen/pin_data.c +++ b/ports/renesas-ra/boards/EK_RA6M1/ra_gen/pin_data.c @@ -1,109 +1,92 @@ /* generated pin source file - do not edit */ #include "bsp_api.h" #include "r_ioport_api.h" -const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { - { - .pin = BSP_IO_PORT_00_PIN_04, - .pin_cfg = ((uint32_t)IOPORT_CFG_ANALOG_ENABLE), - }, - { - .pin = BSP_IO_PORT_01_PIN_00, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), - }, - { - .pin = BSP_IO_PORT_01_PIN_01, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), - }, - { - .pin = BSP_IO_PORT_01_PIN_02, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), - }, - { - .pin = BSP_IO_PORT_01_PIN_03, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), - }, - { - .pin = BSP_IO_PORT_01_PIN_04, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), - }, - { - .pin = BSP_IO_PORT_01_PIN_05, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), - }, - { - .pin = BSP_IO_PORT_01_PIN_06, - .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW), - }, - { - .pin = BSP_IO_PORT_01_PIN_07, - .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW), - }, - { - .pin = BSP_IO_PORT_01_PIN_08, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), - }, - { - .pin = BSP_IO_PORT_01_PIN_09, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), - }, - { - .pin = BSP_IO_PORT_01_PIN_10, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), - }, - { - .pin = BSP_IO_PORT_01_PIN_12, - .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW), - }, - { - .pin = BSP_IO_PORT_02_PIN_01, - .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT), - }, - { - .pin = BSP_IO_PORT_02_PIN_05, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_CTSU), - }, - { - .pin = BSP_IO_PORT_02_PIN_07, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_CTSU), - }, - { - .pin = BSP_IO_PORT_03_PIN_00, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), - }, - { - .pin = BSP_IO_PORT_03_PIN_01, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), - }, - { - .pin = BSP_IO_PORT_03_PIN_02, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), - }, - { - .pin = BSP_IO_PORT_04_PIN_00, - .pin_cfg = ((uint32_t)IOPORT_CFG_DRIVE_MID | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_IIC), - }, - { - .pin = BSP_IO_PORT_04_PIN_01, - .pin_cfg = ((uint32_t)IOPORT_CFG_DRIVE_MID | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_IIC), - }, - { - .pin = BSP_IO_PORT_04_PIN_07, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_USB_FS), - }, - { - .pin = BSP_IO_PORT_04_PIN_10, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), - }, - { - .pin = BSP_IO_PORT_04_PIN_11, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), - }, - { - .pin = BSP_IO_PORT_04_PIN_15, - .pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT), - }, -}; -const ioport_cfg_t g_bsp_pin_cfg = { - .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), - .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = +{ + { .pin = BSP_IO_PORT_00_PIN_04, .pin_cfg = ((uint32_t)IOPORT_CFG_ANALOG_ENABLE) }, + { .pin = BSP_IO_PORT_01_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SPI) }, + { .pin = BSP_IO_PORT_01_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SPI) }, + { .pin = BSP_IO_PORT_01_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SPI) }, + { .pin = BSP_IO_PORT_01_PIN_03, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SPI) }, + { .pin = BSP_IO_PORT_01_PIN_04, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) }, + { .pin = BSP_IO_PORT_01_PIN_05, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) }, + { .pin = BSP_IO_PORT_01_PIN_06, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT + | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) }, + { .pin = BSP_IO_PORT_01_PIN_07, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT + | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) }, + { .pin = BSP_IO_PORT_01_PIN_08, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_DEBUG) }, + { .pin = BSP_IO_PORT_01_PIN_09, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_DEBUG) }, + { .pin = BSP_IO_PORT_01_PIN_10, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_DEBUG) }, + { .pin = BSP_IO_PORT_01_PIN_12, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT + | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) }, + { .pin = BSP_IO_PORT_02_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT) }, + { .pin = BSP_IO_PORT_02_PIN_05, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_CTSU) }, + { .pin = BSP_IO_PORT_02_PIN_07, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_CTSU) }, + { .pin = BSP_IO_PORT_03_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_DEBUG) }, + { .pin = BSP_IO_PORT_03_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) }, + { .pin = BSP_IO_PORT_03_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) }, + { .pin = BSP_IO_PORT_04_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_DRIVE_MID + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_IIC) }, + { .pin = BSP_IO_PORT_04_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_DRIVE_MID + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_IIC) }, + { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_USB_FS) }, + { .pin = BSP_IO_PORT_04_PIN_10, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) }, + { .pin = BSP_IO_PORT_04_PIN_11, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) }, + { .pin = BSP_IO_PORT_04_PIN_15, .pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE + | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT) }, }; + +const ioport_cfg_t g_bsp_pin_cfg = +{ .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], }; + +#if BSP_TZ_SECURE_BUILD + +void R_BSP_PinCfgSecurityInit(void); + +/* Initialize SAR registers for secure pins. */ +void R_BSP_PinCfgSecurityInit(void) { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #else + uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #endif + memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0])); + + + for (uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++) + { + uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin; + uint32_t port = port_pin >> 8U; + uint32_t pin = port_pin & 0xFFU; + pmsar[port] &= (uint16_t) ~(1U << pin); + } + + for (uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + R_PMISC->PMSAR[i].PMSAR = (uint16_t)pmsar[i]; + #else + R_PMISC->PMSAR[i].PMSAR = pmsar[i]; + #endif + } + +} +#endif diff --git a/ports/renesas-ra/boards/EK_RA6M1/ra_gen/vector_data.c b/ports/renesas-ra/boards/EK_RA6M1/ra_gen/vector_data.c index cf17573a0..2004d5589 100644 --- a/ports/renesas-ra/boards/EK_RA6M1/ra_gen/vector_data.c +++ b/ports/renesas-ra/boards/EK_RA6M1/ra_gen/vector_data.c @@ -4,7 +4,7 @@ #if VECTOR_DATA_IRQ_COUNT > 0 BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = { - [0] = sci_uart_rxi_isr, /* SCI0 RXI (Receive data full) */ + [0] = sci_uart_rxi_isr, /* SCI0 RXI (Receive data full) */ [1] = sci_uart_txi_isr, /* SCI0 TXI (Transmit data empty) */ [2] = sci_uart_tei_isr, /* SCI0 TEI (Transmit end) */ [3] = sci_uart_eri_isr, /* SCI0 ERI (Receive error) */ @@ -14,35 +14,35 @@ BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BS [7] = sci_uart_eri_isr, /* SCI2 ERI (Receive error) */ [8] = sci_uart_rxi_isr, /* SCI8 RXI (Received data full) */ [9] = sci_uart_txi_isr, /* SCI8 TXI (Transmit data empty) */ - [10] = sci_uart_tei_isr, /* SCI8 TEI (Transmit end) */ - [11] = sci_uart_eri_isr, /* SCI8 ERI (Receive error) */ - [12] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */ - [13] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */ - [14] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */ - [15] = agt_int_isr, /* AGT0 INT (AGT interrupt) */ - [16] = agt_int_isr, /* AGT1 INT (AGT interrupt) */ - [17] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */ - [18] = r_icu_isr, /* ICU IRQ1 (External pin interrupt 1) */ - [19] = r_icu_isr, /* ICU IRQ2 (External pin interrupt 2) */ - [20] = r_icu_isr, /* ICU IRQ3 (External pin interrupt 3) */ - [21] = r_icu_isr, /* ICU IRQ4 (External pin interrupt 4) */ - [22] = r_icu_isr, /* ICU IRQ5 (External pin interrupt 5) */ - [23] = r_icu_isr, /* ICU IRQ6 (External pin interrupt 6) */ - [24] = r_icu_isr, /* ICU IRQ7 (External pin interrupt 7) */ - [25] = r_icu_isr, /* ICU IRQ8 (External pin interrupt 8) */ - [26] = r_icu_isr, /* ICU IRQ9 (External pin interrupt 9) */ - [27] = r_icu_isr, /* ICU IRQ10 (External pin interrupt 10) */ - [28] = r_icu_isr, /* ICU IRQ11 (External pin interrupt 11) */ - [29] = r_icu_isr, /* ICU IRQ12 (External pin interrupt 12) */ - [30] = r_icu_isr, /* ICU IRQ13 (External pin interrupt 13) */ - [31] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */ - [32] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */ - [33] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */ - [34] = spi_eri_isr, /* SPI0 ERI (Error) */ - [35] = iic_master_rxi_isr, /* IIC0 RXI (Receive data full) */ - [36] = iic_master_txi_isr, /* IIC0 TXI (Transmit data empty) */ - [37] = iic_master_tei_isr, /* IIC0 TEI (Transmit end) */ - [38] = iic_master_eri_isr, /* IIC0 ERI (Transfer error) */ + [10] = sci_uart_tei_isr, /* SCI8 TEI (Transmit end) */ + [11] = sci_uart_eri_isr, /* SCI8 ERI (Receive error) */ + [12] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */ + [13] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */ + [14] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */ + [15] = agt_int_isr, /* AGT0 INT (AGT interrupt) */ + [16] = agt_int_isr, /* AGT1 INT (AGT interrupt) */ + [17] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */ + [18] = r_icu_isr, /* ICU IRQ1 (External pin interrupt 1) */ + [19] = r_icu_isr, /* ICU IRQ2 (External pin interrupt 2) */ + [20] = r_icu_isr, /* ICU IRQ3 (External pin interrupt 3) */ + [21] = r_icu_isr, /* ICU IRQ4 (External pin interrupt 4) */ + [22] = r_icu_isr, /* ICU IRQ5 (External pin interrupt 5) */ + [23] = r_icu_isr, /* ICU IRQ6 (External pin interrupt 6) */ + [24] = r_icu_isr, /* ICU IRQ7 (External pin interrupt 7) */ + [25] = r_icu_isr, /* ICU IRQ8 (External pin interrupt 8) */ + [26] = r_icu_isr, /* ICU IRQ9 (External pin interrupt 9) */ + [27] = r_icu_isr, /* ICU IRQ10 (External pin interrupt 10) */ + [28] = r_icu_isr, /* ICU IRQ11 (External pin interrupt 11) */ + [29] = r_icu_isr, /* ICU IRQ12 (External pin interrupt 12) */ + [30] = r_icu_isr, /* ICU IRQ13 (External pin interrupt 13) */ + [31] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */ + [32] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */ + [33] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */ + [34] = spi_eri_isr, /* SPI0 ERI (Error) */ + [35] = iic_master_rxi_isr, /* IIC0 RXI (Receive data full) */ + [36] = iic_master_txi_isr, /* IIC0 TXI (Transmit data empty) */ + [37] = iic_master_tei_isr, /* IIC0 TEI (Transmit end) */ + [38] = iic_master_eri_isr, /* IIC0 ERI (Transfer error) */ }; const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = { @@ -56,34 +56,34 @@ const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENT [7] = BSP_PRV_IELS_ENUM(EVENT_SCI2_ERI), /* SCI2 ERI (Receive error) */ [8] = BSP_PRV_IELS_ENUM(EVENT_SCI8_RXI), /* SCI8 RXI (Received data full) */ [9] = BSP_PRV_IELS_ENUM(EVENT_SCI8_TXI), /* SCI8 TXI (Transmit data empty) */ - [10] = BSP_PRV_IELS_ENUM(EVENT_SCI8_TEI), /* SCI8 TEI (Transmit end) */ - [11] = BSP_PRV_IELS_ENUM(EVENT_SCI8_ERI), /* SCI8 ERI (Receive error) */ - [12] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */ - [13] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */ - [14] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */ - [15] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */ - [16] = BSP_PRV_IELS_ENUM(EVENT_AGT1_INT), /* AGT1 INT (AGT interrupt) */ - [17] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ0), /* ICU IRQ0 (External pin interrupt 0) */ - [18] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ1), /* ICU IRQ1 (External pin interrupt 1) */ - [19] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ2), /* ICU IRQ2 (External pin interrupt 2) */ - [20] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ3), /* ICU IRQ3 (External pin interrupt 3) */ - [21] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ4), /* ICU IRQ4 (External pin interrupt 4) */ - [22] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ5), /* ICU IRQ5 (External pin interrupt 5) */ - [23] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ6), /* ICU IRQ6 (External pin interrupt 6) */ - [24] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ7), /* ICU IRQ7 (External pin interrupt 7) */ - [25] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ8), /* ICU IRQ8 (External pin interrupt 8) */ - [26] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ9), /* ICU IRQ9 (External pin interrupt 9) */ - [27] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ10), /* ICU IRQ10 (External pin interrupt 10) */ - [28] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ11), /* ICU IRQ11 (External pin interrupt 11) */ - [29] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ12), /* ICU IRQ12 (External pin interrupt 12) */ - [30] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ13), /* ICU IRQ13 (External pin interrupt 13) */ - [31] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */ - [32] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */ - [33] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */ - [34] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */ - [35] = BSP_PRV_IELS_ENUM(EVENT_IIC0_RXI), /* IIC0 RXI (Receive data full) */ - [36] = BSP_PRV_IELS_ENUM(EVENT_IIC0_TXI), /* IIC0 TXI (Transmit data empty) */ - [37] = BSP_PRV_IELS_ENUM(EVENT_IIC0_TEI), /* IIC0 TEI (Transmit end) */ - [38] = BSP_PRV_IELS_ENUM(EVENT_IIC0_ERI), /* IIC0 ERI (Transfer error) */ + [10] = BSP_PRV_IELS_ENUM(EVENT_SCI8_TEI), /* SCI8 TEI (Transmit end) */ + [11] = BSP_PRV_IELS_ENUM(EVENT_SCI8_ERI), /* SCI8 ERI (Receive error) */ + [12] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */ + [13] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */ + [14] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */ + [15] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */ + [16] = BSP_PRV_IELS_ENUM(EVENT_AGT1_INT), /* AGT1 INT (AGT interrupt) */ + [17] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ0), /* ICU IRQ0 (External pin interrupt 0) */ + [18] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ1), /* ICU IRQ1 (External pin interrupt 1) */ + [19] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ2), /* ICU IRQ2 (External pin interrupt 2) */ + [20] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ3), /* ICU IRQ3 (External pin interrupt 3) */ + [21] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ4), /* ICU IRQ4 (External pin interrupt 4) */ + [22] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ5), /* ICU IRQ5 (External pin interrupt 5) */ + [23] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ6), /* ICU IRQ6 (External pin interrupt 6) */ + [24] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ7), /* ICU IRQ7 (External pin interrupt 7) */ + [25] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ8), /* ICU IRQ8 (External pin interrupt 8) */ + [26] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ9), /* ICU IRQ9 (External pin interrupt 9) */ + [27] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ10), /* ICU IRQ10 (External pin interrupt 10) */ + [28] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ11), /* ICU IRQ11 (External pin interrupt 11) */ + [29] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ12), /* ICU IRQ12 (External pin interrupt 12) */ + [30] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ13), /* ICU IRQ13 (External pin interrupt 13) */ + [31] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */ + [32] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */ + [33] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */ + [34] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */ + [35] = BSP_PRV_IELS_ENUM(EVENT_IIC0_RXI), /* IIC0 RXI (Receive data full) */ + [36] = BSP_PRV_IELS_ENUM(EVENT_IIC0_TXI), /* IIC0 TXI (Transmit data empty) */ + [37] = BSP_PRV_IELS_ENUM(EVENT_IIC0_TEI), /* IIC0 TEI (Transmit end) */ + [38] = BSP_PRV_IELS_ENUM(EVENT_IIC0_ERI), /* IIC0 ERI (Transfer error) */ }; #endif diff --git a/ports/renesas-ra/boards/EK_RA6M1/ra_gen/vector_data.h b/ports/renesas-ra/boards/EK_RA6M1/ra_gen/vector_data.h index b812cff2e..688c2c39f 100644 --- a/ports/renesas-ra/boards/EK_RA6M1/ra_gen/vector_data.h +++ b/ports/renesas-ra/boards/EK_RA6M1/ra_gen/vector_data.h @@ -1,6 +1,9 @@ /* generated vector header file - do not edit */ #ifndef VECTOR_DATA_H #define VECTOR_DATA_H +#ifdef __cplusplus +extern "C" { +#endif /* Number of interrupts allocated */ #ifndef VECTOR_DATA_IRQ_COUNT #define VECTOR_DATA_IRQ_COUNT (39) @@ -25,95 +28,84 @@ void iic_master_eri_isr(void); /* Vector table allocations */ #define VECTOR_NUMBER_SCI0_RXI ((IRQn_Type)0) /* SCI0 RXI (Receive data full) */ +#define SCI0_RXI_IRQn ((IRQn_Type)0) /* SCI0 RXI (Receive data full) */ #define VECTOR_NUMBER_SCI0_TXI ((IRQn_Type)1) /* SCI0 TXI (Transmit data empty) */ +#define SCI0_TXI_IRQn ((IRQn_Type)1) /* SCI0 TXI (Transmit data empty) */ #define VECTOR_NUMBER_SCI0_TEI ((IRQn_Type)2) /* SCI0 TEI (Transmit end) */ +#define SCI0_TEI_IRQn ((IRQn_Type)2) /* SCI0 TEI (Transmit end) */ #define VECTOR_NUMBER_SCI0_ERI ((IRQn_Type)3) /* SCI0 ERI (Receive error) */ +#define SCI0_ERI_IRQn ((IRQn_Type)3) /* SCI0 ERI (Receive error) */ #define VECTOR_NUMBER_SCI2_RXI ((IRQn_Type)4) /* SCI2 RXI (Received data full) */ +#define SCI2_RXI_IRQn ((IRQn_Type)4) /* SCI2 RXI (Received data full) */ #define VECTOR_NUMBER_SCI2_TXI ((IRQn_Type)5) /* SCI2 TXI (Transmit data empty) */ +#define SCI2_TXI_IRQn ((IRQn_Type)5) /* SCI2 TXI (Transmit data empty) */ #define VECTOR_NUMBER_SCI2_TEI ((IRQn_Type)6) /* SCI2 TEI (Transmit end) */ +#define SCI2_TEI_IRQn ((IRQn_Type)6) /* SCI2 TEI (Transmit end) */ #define VECTOR_NUMBER_SCI2_ERI ((IRQn_Type)7) /* SCI2 ERI (Receive error) */ +#define SCI2_ERI_IRQn ((IRQn_Type)7) /* SCI2 ERI (Receive error) */ #define VECTOR_NUMBER_SCI8_RXI ((IRQn_Type)8) /* SCI8 RXI (Received data full) */ +#define SCI8_RXI_IRQn ((IRQn_Type)8) /* SCI8 RXI (Received data full) */ #define VECTOR_NUMBER_SCI8_TXI ((IRQn_Type)9) /* SCI8 TXI (Transmit data empty) */ +#define SCI8_TXI_IRQn ((IRQn_Type)9) /* SCI8 TXI (Transmit data empty) */ #define VECTOR_NUMBER_SCI8_TEI ((IRQn_Type)10) /* SCI8 TEI (Transmit end) */ +#define SCI8_TEI_IRQn ((IRQn_Type)10) /* SCI8 TEI (Transmit end) */ #define VECTOR_NUMBER_SCI8_ERI ((IRQn_Type)11) /* SCI8 ERI (Receive error) */ +#define SCI8_ERI_IRQn ((IRQn_Type)11) /* SCI8 ERI (Receive error) */ #define VECTOR_NUMBER_RTC_ALARM ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */ +#define RTC_ALARM_IRQn ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */ #define VECTOR_NUMBER_RTC_PERIOD ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */ +#define RTC_PERIOD_IRQn ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */ #define VECTOR_NUMBER_RTC_CARRY ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */ +#define RTC_CARRY_IRQn ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */ #define VECTOR_NUMBER_AGT0_INT ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */ +#define AGT0_INT_IRQn ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */ #define VECTOR_NUMBER_AGT1_INT ((IRQn_Type)16) /* AGT1 INT (AGT interrupt) */ +#define AGT1_INT_IRQn ((IRQn_Type)16) /* AGT1 INT (AGT interrupt) */ #define VECTOR_NUMBER_ICU_IRQ0 ((IRQn_Type)17) /* ICU IRQ0 (External pin interrupt 0) */ +#define ICU_IRQ0_IRQn ((IRQn_Type)17) /* ICU IRQ0 (External pin interrupt 0) */ #define VECTOR_NUMBER_ICU_IRQ1 ((IRQn_Type)18) /* ICU IRQ1 (External pin interrupt 1) */ +#define ICU_IRQ1_IRQn ((IRQn_Type)18) /* ICU IRQ1 (External pin interrupt 1) */ #define VECTOR_NUMBER_ICU_IRQ2 ((IRQn_Type)19) /* ICU IRQ2 (External pin interrupt 2) */ +#define ICU_IRQ2_IRQn ((IRQn_Type)19) /* ICU IRQ2 (External pin interrupt 2) */ #define VECTOR_NUMBER_ICU_IRQ3 ((IRQn_Type)20) /* ICU IRQ3 (External pin interrupt 3) */ +#define ICU_IRQ3_IRQn ((IRQn_Type)20) /* ICU IRQ3 (External pin interrupt 3) */ #define VECTOR_NUMBER_ICU_IRQ4 ((IRQn_Type)21) /* ICU IRQ4 (External pin interrupt 4) */ +#define ICU_IRQ4_IRQn ((IRQn_Type)21) /* ICU IRQ4 (External pin interrupt 4) */ #define VECTOR_NUMBER_ICU_IRQ5 ((IRQn_Type)22) /* ICU IRQ5 (External pin interrupt 5) */ +#define ICU_IRQ5_IRQn ((IRQn_Type)22) /* ICU IRQ5 (External pin interrupt 5) */ #define VECTOR_NUMBER_ICU_IRQ6 ((IRQn_Type)23) /* ICU IRQ6 (External pin interrupt 6) */ +#define ICU_IRQ6_IRQn ((IRQn_Type)23) /* ICU IRQ6 (External pin interrupt 6) */ #define VECTOR_NUMBER_ICU_IRQ7 ((IRQn_Type)24) /* ICU IRQ7 (External pin interrupt 7) */ +#define ICU_IRQ7_IRQn ((IRQn_Type)24) /* ICU IRQ7 (External pin interrupt 7) */ #define VECTOR_NUMBER_ICU_IRQ8 ((IRQn_Type)25) /* ICU IRQ8 (External pin interrupt 8) */ +#define ICU_IRQ8_IRQn ((IRQn_Type)25) /* ICU IRQ8 (External pin interrupt 8) */ #define VECTOR_NUMBER_ICU_IRQ9 ((IRQn_Type)26) /* ICU IRQ9 (External pin interrupt 9) */ +#define ICU_IRQ9_IRQn ((IRQn_Type)26) /* ICU IRQ9 (External pin interrupt 9) */ #define VECTOR_NUMBER_ICU_IRQ10 ((IRQn_Type)27) /* ICU IRQ10 (External pin interrupt 10) */ +#define ICU_IRQ10_IRQn ((IRQn_Type)27) /* ICU IRQ10 (External pin interrupt 10) */ #define VECTOR_NUMBER_ICU_IRQ11 ((IRQn_Type)28) /* ICU IRQ11 (External pin interrupt 11) */ +#define ICU_IRQ11_IRQn ((IRQn_Type)28) /* ICU IRQ11 (External pin interrupt 11) */ #define VECTOR_NUMBER_ICU_IRQ12 ((IRQn_Type)29) /* ICU IRQ12 (External pin interrupt 12) */ +#define ICU_IRQ12_IRQn ((IRQn_Type)29) /* ICU IRQ12 (External pin interrupt 12) */ #define VECTOR_NUMBER_ICU_IRQ13 ((IRQn_Type)30) /* ICU IRQ13 (External pin interrupt 13) */ +#define ICU_IRQ13_IRQn ((IRQn_Type)30) /* ICU IRQ13 (External pin interrupt 13) */ #define VECTOR_NUMBER_SPI0_RXI ((IRQn_Type)31) /* SPI0 RXI (Receive buffer full) */ +#define SPI0_RXI_IRQn ((IRQn_Type)31) /* SPI0 RXI (Receive buffer full) */ #define VECTOR_NUMBER_SPI0_TXI ((IRQn_Type)32) /* SPI0 TXI (Transmit buffer empty) */ +#define SPI0_TXI_IRQn ((IRQn_Type)32) /* SPI0 TXI (Transmit buffer empty) */ #define VECTOR_NUMBER_SPI0_TEI ((IRQn_Type)33) /* SPI0 TEI (Transmission complete event) */ +#define SPI0_TEI_IRQn ((IRQn_Type)33) /* SPI0 TEI (Transmission complete event) */ #define VECTOR_NUMBER_SPI0_ERI ((IRQn_Type)34) /* SPI0 ERI (Error) */ +#define SPI0_ERI_IRQn ((IRQn_Type)34) /* SPI0 ERI (Error) */ #define VECTOR_NUMBER_IIC0_RXI ((IRQn_Type)35) /* IIC0 RXI (Receive data full) */ +#define IIC0_RXI_IRQn ((IRQn_Type)35) /* IIC0 RXI (Receive data full) */ #define VECTOR_NUMBER_IIC0_TXI ((IRQn_Type)36) /* IIC0 TXI (Transmit data empty) */ +#define IIC0_TXI_IRQn ((IRQn_Type)36) /* IIC0 TXI (Transmit data empty) */ #define VECTOR_NUMBER_IIC0_TEI ((IRQn_Type)37) /* IIC0 TEI (Transmit end) */ +#define IIC0_TEI_IRQn ((IRQn_Type)37) /* IIC0 TEI (Transmit end) */ #define VECTOR_NUMBER_IIC0_ERI ((IRQn_Type)38) /* IIC0 ERI (Transfer error) */ -typedef enum IRQn -{ - Reset_IRQn = -15, - NonMaskableInt_IRQn = -14, - HardFault_IRQn = -13, - MemoryManagement_IRQn = -12, - BusFault_IRQn = -11, - UsageFault_IRQn = -10, - SecureFault_IRQn = -9, - SVCall_IRQn = -5, - DebugMonitor_IRQn = -4, - PendSV_IRQn = -2, - SysTick_IRQn = -1, - SCI0_RXI_IRQn = 0, /* SCI0 RXI (Receive data full) */ - SCI0_TXI_IRQn = 1, /* SCI0 TXI (Transmit data empty) */ - SCI0_TEI_IRQn = 2, /* SCI0 TEI (Transmit end) */ - SCI0_ERI_IRQn = 3, /* SCI0 ERI (Receive error) */ - SCI2_RXI_IRQn = 4, /* SCI2 RXI (Received data full) */ - SCI2_TXI_IRQn = 5, /* SCI2 TXI (Transmit data empty) */ - SCI2_TEI_IRQn = 6, /* SCI2 TEI (Transmit end) */ - SCI2_ERI_IRQn = 7, /* SCI2 ERI (Receive error) */ - SCI8_RXI_IRQn = 8, /* SCI8 RXI (Received data full) */ - SCI8_TXI_IRQn = 9, /* SCI8 TXI (Transmit data empty) */ - SCI8_TEI_IRQn = 10, /* SCI8 TEI (Transmit end) */ - SCI8_ERI_IRQn = 11, /* SCI8 ERI (Receive error) */ - RTC_ALARM_IRQn = 12, /* RTC ALARM (Alarm interrupt) */ - RTC_PERIOD_IRQn = 13, /* RTC PERIOD (Periodic interrupt) */ - RTC_CARRY_IRQn = 14, /* RTC CARRY (Carry interrupt) */ - AGT0_INT_IRQn = 15, /* AGT0 INT (AGT interrupt) */ - AGT1_INT_IRQn = 16, /* AGT1 INT (AGT interrupt) */ - ICU_IRQ0_IRQn = 17, /* ICU IRQ0 (External pin interrupt 0) */ - ICU_IRQ1_IRQn = 18, /* ICU IRQ1 (External pin interrupt 1) */ - ICU_IRQ2_IRQn = 19, /* ICU IRQ2 (External pin interrupt 2) */ - ICU_IRQ3_IRQn = 20, /* ICU IRQ3 (External pin interrupt 3) */ - ICU_IRQ4_IRQn = 21, /* ICU IRQ4 (External pin interrupt 4) */ - ICU_IRQ5_IRQn = 22, /* ICU IRQ5 (External pin interrupt 5) */ - ICU_IRQ6_IRQn = 23, /* ICU IRQ6 (External pin interrupt 6) */ - ICU_IRQ7_IRQn = 24, /* ICU IRQ7 (External pin interrupt 7) */ - ICU_IRQ8_IRQn = 25, /* ICU IRQ8 (External pin interrupt 8) */ - ICU_IRQ9_IRQn = 26, /* ICU IRQ9 (External pin interrupt 9) */ - ICU_IRQ10_IRQn = 27, /* ICU IRQ10 (External pin interrupt 10) */ - ICU_IRQ11_IRQn = 28, /* ICU IRQ11 (External pin interrupt 11) */ - ICU_IRQ12_IRQn = 29, /* ICU IRQ12 (External pin interrupt 12) */ - ICU_IRQ13_IRQn = 30, /* ICU IRQ13 (External pin interrupt 13) */ - SPI0_RXI_IRQn = 31, /* SPI0 RXI (Receive buffer full) */ - SPI0_TXI_IRQn = 32, /* SPI0 TXI (Transmit buffer empty) */ - SPI0_TEI_IRQn = 33, /* SPI0 TEI (Transmission complete event) */ - SPI0_ERI_IRQn = 34, /* SPI0 ERI (Error) */ - IIC0_RXI_IRQn = 35, /* IIC0 RXI (Receive data full) */ - IIC0_TXI_IRQn = 36, /* IIC0 TXI (Transmit data empty) */ - IIC0_TEI_IRQn = 37, /* IIC0 TEI (Transmit end) */ - IIC0_ERI_IRQn = 38, /* IIC0 ERI (Transfer error) */ -} IRQn_Type; +#define IIC0_ERI_IRQn ((IRQn_Type)38) /* IIC0 ERI (Transfer error) */ +#ifdef __cplusplus +} +#endif #endif /* VECTOR_DATA_H */ diff --git a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/bsp/bsp_cfg.h index 7255cdd17..9952bf9b1 100644 --- a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/bsp/bsp_cfg.h +++ b/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -1,6 +1,10 @@ /* generated configuration header file - do not edit */ #ifndef BSP_CFG_H_ #define BSP_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #include "bsp_clock_cfg.h" #include "bsp_mcu_family_cfg.h" #include "board_cfg.h" @@ -14,7 +18,13 @@ #define BSP_CFG_RTOS (0) #endif #endif +#ifndef BSP_CFG_RTC_USED +#define BSP_CFG_RTC_USED (1) +#endif #undef RA_NOT_DEFINED +#if defined(_RA_BOOT_IMAGE) +#define BSP_CFG_BOOT_IMAGE (1) +#endif #define BSP_CFG_MCU_VCC_MV (3300) #define BSP_CFG_STACK_MAIN_BYTES (0x4000) #define BSP_CFG_HEAP_BYTES (0x4d000) @@ -25,15 +35,14 @@ #define BSP_CFG_PFS_PROTECT ((1)) #define BSP_CFG_C_RUNTIME_INIT ((1)) +#define BSP_CFG_EARLY_INIT ((0)) -#define BSP_CFG_SOFT_RESET_SUPPORTED ((0)) +#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) #endif -#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) -#endif + #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) #endif @@ -46,4 +55,8 @@ #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 #endif + +#ifdef __cplusplus +} +#endif #endif /* BSP_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h index 6097e9d7d..39e9384f7 100644 --- a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h +++ b/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -2,6 +2,7 @@ #ifndef BSP_MCU_DEVICE_PN_CFG_H_ #define BSP_MCU_DEVICE_PN_CFG_H_ #define BSP_MCU_R7FA6M2AF3CFB +#define BSP_MCU_FEATURE_SET ('A') #define BSP_ROM_SIZE_BYTES (1048576) #define BSP_RAM_SIZE_BYTES (393216) #define BSP_DATA_FLASH_SIZE_BYTES (32768) diff --git a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h index 51f399e3c..f3b369cbc 100644 --- a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ b/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -1,6 +1,10 @@ /* generated configuration header file - do not edit */ #ifndef BSP_MCU_FAMILY_CFG_H_ #define BSP_MCU_FAMILY_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #include "bsp_mcu_device_pn_cfg.h" #include "bsp_mcu_device_cfg.h" #include "../../../ra/fsp/src/bsp/mcu/ra6m2/bsp_mcu_info.h" @@ -23,7 +27,6 @@ #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) -#define BSP_MCU_VBATT_SUPPORT (1) #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) @@ -50,7 +53,9 @@ #define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) #define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) #define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) - +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ #define BSP_PRV_IELS_ENUM(vector) (ELC_##vector) @@ -71,4 +76,8 @@ #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) #endif + +#ifdef __cplusplus +} +#endif #endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_adc_cfg.h b/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_adc_cfg.h index 9c59889ca..be8a42720 100644 --- a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_adc_cfg.h +++ b/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_adc_cfg.h @@ -1,5 +1,13 @@ /* generated configuration header file - do not edit */ #ifndef R_ADC_CFG_H_ #define R_ADC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #define ADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif #endif /* R_ADC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_agt_cfg.h b/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_agt_cfg.h deleted file mode 100644 index d3ab55923..000000000 --- a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_agt_cfg.h +++ /dev/null @@ -1,7 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_AGT_CFG_H_ -#define R_AGT_CFG_H_ -#define AGT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#define AGT_CFG_OUTPUT_SUPPORT_ENABLE (0) -#define AGT_CFG_INPUT_SUPPORT_ENABLE (0) -#endif /* R_AGT_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_dtc_cfg.h b/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_dtc_cfg.h deleted file mode 100644 index 21405f967..000000000 --- a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_dtc_cfg.h +++ /dev/null @@ -1,6 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_DTC_CFG_H_ -#define R_DTC_CFG_H_ -#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#define DTC_CFG_VECTOR_TABLE_SECTION_NAME ".fsp_dtc_vector_table" -#endif /* R_DTC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_flash_hp_cfg.h b/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_flash_hp_cfg.h index 48c9dec4e..9f7819b71 100644 --- a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_flash_hp_cfg.h +++ b/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_flash_hp_cfg.h @@ -1,7 +1,15 @@ /* generated configuration header file - do not edit */ #ifndef R_FLASH_HP_CFG_H_ #define R_FLASH_HP_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #define FLASH_HP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) #define FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (1) #define FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (0) + +#ifdef __cplusplus +} +#endif #endif /* R_FLASH_HP_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_icu_cfg.h b/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_icu_cfg.h deleted file mode 100644 index 5e77b6980..000000000 --- a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_icu_cfg.h +++ /dev/null @@ -1,5 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_ICU_CFG_H_ -#define R_ICU_CFG_H_ -#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#endif /* R_ICU_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_iic_master_cfg.h b/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_iic_master_cfg.h deleted file mode 100644 index 595ea938d..000000000 --- a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_iic_master_cfg.h +++ /dev/null @@ -1,7 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_IIC_MASTER_CFG_H_ -#define R_IIC_MASTER_CFG_H_ -#define IIC_MASTER_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#define IIC_MASTER_CFG_DTC_ENABLE (0) -#define IIC_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE (0) -#endif /* R_IIC_MASTER_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_ioport_cfg.h b/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_ioport_cfg.h index 6b4353d23..d2688bf5b 100644 --- a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_ioport_cfg.h +++ b/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -1,5 +1,13 @@ /* generated configuration header file - do not edit */ #ifndef R_IOPORT_CFG_H_ #define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif #endif /* R_IOPORT_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_lpm_cfg.h b/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_lpm_cfg.h index 5f4d5c4a7..6712eee6a 100644 --- a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_lpm_cfg.h +++ b/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_lpm_cfg.h @@ -1,5 +1,14 @@ /* generated configuration header file - do not edit */ #ifndef R_LPM_CFG_H_ #define R_LPM_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #define LPM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define LPM_CFG_STANDBY_LIMIT (0) + +#ifdef __cplusplus +} +#endif #endif /* R_LPM_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_rtc_cfg.h b/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_rtc_cfg.h deleted file mode 100644 index 484b7ed04..000000000 --- a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_rtc_cfg.h +++ /dev/null @@ -1,5 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_RTC_CFG_H_ -#define R_RTC_CFG_H_ -#define RTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#endif /* R_RTC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_sci_uart_cfg.h b/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_sci_uart_cfg.h deleted file mode 100644 index c70c0be34..000000000 --- a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_sci_uart_cfg.h +++ /dev/null @@ -1,8 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_SCI_UART_CFG_H_ -#define R_SCI_UART_CFG_H_ -#define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#define SCI_UART_CFG_FIFO_SUPPORT (0) -#define SCI_UART_CFG_DTC_SUPPORTED (0) -#define SCI_UART_CFG_FLOW_CONTROL_SUPPORT (0) -#endif /* R_SCI_UART_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_spi_cfg.h b/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_spi_cfg.h deleted file mode 100644 index 861fe1219..000000000 --- a/ports/renesas-ra/boards/EK_RA6M2/ra_cfg/fsp_cfg/r_spi_cfg.h +++ /dev/null @@ -1,7 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_SPI_CFG_H_ -#define R_SPI_CFG_H_ -#define SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#define SPI_DTC_SUPPORT_ENABLE (1) -#define SPI_TRANSMIT_FROM_RXI_ISR (0) -#endif /* R_SPI_CFG_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M2/ra_gen/bsp_clock_cfg.h b/ports/renesas-ra/boards/EK_RA6M2/ra_gen/bsp_clock_cfg.h index 2c93a573b..85616224e 100644 --- a/ports/renesas-ra/boards/EK_RA6M2/ra_gen/bsp_clock_cfg.h +++ b/ports/renesas-ra/boards/EK_RA6M2/ra_gen/bsp_clock_cfg.h @@ -7,16 +7,16 @@ #define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ #define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ #define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_1) /* PLL Div /1 */ -#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL Mul x20.0 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(20U, 0U) /* PLL Mul x20.0 */ #define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ #define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */ #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ #define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ #define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ #define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ -#define BSP_CFG_SDCLK_OUTPUT (1) /* SDCLKout On */ +#define BSP_CFG_SDCLK_OUTPUT (1) /* SDCLK Enabled */ #define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ -#define BSP_CFG_BCLK_OUTPUT (2) /* BCK/2 */ +#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */ #define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ #define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ #define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ diff --git a/ports/renesas-ra/boards/EK_RA6M2/ra_gen/common_data.c b/ports/renesas-ra/boards/EK_RA6M2/ra_gen/common_data.c index 34aad762f..c52056c5c 100644 --- a/ports/renesas-ra/boards/EK_RA6M2/ra_gen/common_data.c +++ b/ports/renesas-ra/boards/EK_RA6M2/ra_gen/common_data.c @@ -1,7 +1,5 @@ -/* generated common source file - do not edit */ #include "common_data.h" + ioport_instance_ctrl_t g_ioport_ctrl; const ioport_instance_t g_ioport = { .p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg, }; -void g_common_init(void) { -} diff --git a/ports/renesas-ra/boards/EK_RA6M2/ra_gen/common_data.h b/ports/renesas-ra/boards/EK_RA6M2/ra_gen/common_data.h index e2eb70836..3cabbef1b 100644 --- a/ports/renesas-ra/boards/EK_RA6M2/ra_gen/common_data.h +++ b/ports/renesas-ra/boards/EK_RA6M2/ra_gen/common_data.h @@ -1,16 +1,17 @@ -/* generated common header file - do not edit */ #ifndef COMMON_DATA_H_ #define COMMON_DATA_H_ #include <stdint.h> #include "bsp_api.h" +#include "r_icu.h" +#include "r_external_irq_api.h" #include "r_ioport.h" #include "bsp_pin_cfg.h" FSP_HEADER + /* IOPORT Instance */ extern const ioport_instance_t g_ioport; /* IOPORT control structure. */ extern ioport_instance_ctrl_t g_ioport_ctrl; -void g_common_init(void); FSP_FOOTER #endif /* COMMON_DATA_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M2/ra_gen/hal_data.c b/ports/renesas-ra/boards/EK_RA6M2/ra_gen/hal_data.c index b0d38881e..0138e5b11 100644 --- a/ports/renesas-ra/boards/EK_RA6M2/ra_gen/hal_data.c +++ b/ports/renesas-ra/boards/EK_RA6M2/ra_gen/hal_data.c @@ -1,131 +1,16 @@ -/* generated HAL source file - do not edit */ #include "hal_data.h" -/* Macros to tie dynamic ELC links to ADC_TRIGGER_SYNC_ELC option in adc_trigger_t. */ -#define ADC_TRIGGER_ADC0 ADC_TRIGGER_SYNC_ELC -#define ADC_TRIGGER_ADC0_B ADC_TRIGGER_SYNC_ELC -#define ADC_TRIGGER_ADC1 ADC_TRIGGER_SYNC_ELC -#define ADC_TRIGGER_ADC1_B ADC_TRIGGER_SYNC_ELC -iic_master_instance_ctrl_t g_i2c_master2_ctrl; -const iic_master_extended_cfg_t g_i2c_master2_extend = -{ .timeout_mode = IIC_MASTER_TIMEOUT_MODE_SHORT, -/* Actual calculated bitrate: 98945. Actual calculated duty cycle: 51%. */ .clock_settings.brl_value = 15, - .clock_settings.brh_value = 16, .clock_settings.cks_value = 4, }; -const i2c_master_cfg_t g_i2c_master2_cfg = -{ .channel = 2, .rate = I2C_MASTER_RATE_STANDARD, .slave = 0x00, .addr_mode = I2C_MASTER_ADDR_MODE_7BIT, -#define RA_NOT_DEFINED (1) - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_tx = NULL, - #else - .p_transfer_tx = &RA_NOT_DEFINED, - #endif - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_rx = NULL, - #else - .p_transfer_rx = &RA_NOT_DEFINED, - #endif -#undef RA_NOT_DEFINED - .p_callback = callback_iic, - .p_context = NULL, - #if defined(VECTOR_NUMBER_IIC2_RXI) - .rxi_irq = VECTOR_NUMBER_IIC2_RXI, - #else - .rxi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_IIC2_TXI) - .txi_irq = VECTOR_NUMBER_IIC2_TXI, - #else - .txi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_IIC2_TEI) - .tei_irq = VECTOR_NUMBER_IIC2_TEI, - #else - .tei_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_IIC2_ERI) - .eri_irq = VECTOR_NUMBER_IIC2_ERI, - #else - .eri_irq = FSP_INVALID_VECTOR, - #endif - .ipl = (12), - .p_extend = &g_i2c_master2_extend, }; -/* Instance structure to use this module. */ -const i2c_master_instance_t g_i2c_master2 = -{ .p_ctrl = &g_i2c_master2_ctrl, .p_cfg = &g_i2c_master2_cfg, .p_api = &g_i2c_master_on_iic }; -adc_instance_ctrl_t g_adc1_ctrl; -const adc_extended_cfg_t g_adc1_cfg_extend = -{ .add_average_count = ADC_ADD_OFF, - .clearing = ADC_CLEAR_AFTER_READ_ON, - .trigger_group_b = ADC_TRIGGER_SYNC_ELC, - .double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED, - .adc_vref_control = ADC_VREF_CONTROL_VREFH, }; -const adc_cfg_t g_adc1_cfg = -{ .unit = 1, .mode = ADC_MODE_SINGLE_SCAN, .resolution = ADC_RESOLUTION_12_BIT, .alignment = - (adc_alignment_t)ADC_ALIGNMENT_RIGHT, - .trigger = ADC_TRIGGER_SOFTWARE, .p_callback = NULL, .p_context = NULL, .p_extend = &g_adc1_cfg_extend, - #if defined(VECTOR_NUMBER_ADC1_SCAN_END) - .scan_end_irq = VECTOR_NUMBER_ADC1_SCAN_END, - #else - .scan_end_irq = FSP_INVALID_VECTOR, - #endif - .scan_end_ipl = (BSP_IRQ_DISABLED), - #if defined(VECTOR_NUMBER_ADC1_SCAN_END_B) - .scan_end_b_irq = VECTOR_NUMBER_ADC1_SCAN_END_B, - #else - .scan_end_b_irq = FSP_INVALID_VECTOR, - #endif - .scan_end_b_ipl = (BSP_IRQ_DISABLED), }; -const adc_channel_cfg_t g_adc1_channel_cfg = -{ .scan_mask = 0, - .scan_mask_group_b = 0, - .priority_group_a = ADC_GROUP_A_PRIORITY_OFF, - .add_mask = 0, - .sample_hold_mask = 0, - .sample_hold_states = 24, }; -/* Instance structure to use this module. */ -const adc_instance_t g_adc1 = -{ .p_ctrl = &g_adc1_ctrl, .p_cfg = &g_adc1_cfg, .p_channel_cfg = &g_adc1_channel_cfg, .p_api = &g_adc_on_adc }; -adc_instance_ctrl_t g_adc0_ctrl; -const adc_extended_cfg_t g_adc0_cfg_extend = -{ .add_average_count = ADC_ADD_OFF, - .clearing = ADC_CLEAR_AFTER_READ_ON, - .trigger_group_b = ADC_TRIGGER_SYNC_ELC, - .double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED, - .adc_vref_control = ADC_VREF_CONTROL_VREFH, }; -const adc_cfg_t g_adc0_cfg = -{ .unit = 0, .mode = ADC_MODE_SINGLE_SCAN, .resolution = ADC_RESOLUTION_12_BIT, .alignment = - (adc_alignment_t)ADC_ALIGNMENT_RIGHT, - .trigger = ADC_TRIGGER_SOFTWARE, .p_callback = NULL, .p_context = NULL, .p_extend = &g_adc0_cfg_extend, - #if defined(VECTOR_NUMBER_ADC0_SCAN_END) - .scan_end_irq = VECTOR_NUMBER_ADC0_SCAN_END, - #else - .scan_end_irq = FSP_INVALID_VECTOR, - #endif - .scan_end_ipl = (BSP_IRQ_DISABLED), - #if defined(VECTOR_NUMBER_ADC0_SCAN_END_B) - .scan_end_b_irq = VECTOR_NUMBER_ADC0_SCAN_END_B, - #else - .scan_end_b_irq = FSP_INVALID_VECTOR, - #endif - .scan_end_b_ipl = (BSP_IRQ_DISABLED), }; -const adc_channel_cfg_t g_adc0_channel_cfg = -{ .scan_mask = 0, - .scan_mask_group_b = 0, - .priority_group_a = ADC_GROUP_A_PRIORITY_OFF, - .add_mask = 0, - .sample_hold_mask = 0, - .sample_hold_states = 24, }; -/* Instance structure to use this module. */ -const adc_instance_t g_adc0 = -{ .p_ctrl = &g_adc0_ctrl, .p_cfg = &g_adc0_cfg, .p_channel_cfg = &g_adc0_channel_cfg, .p_api = &g_adc_on_adc }; + lpm_instance_ctrl_t g_lpm0_ctrl; const lpm_cfg_t g_lpm0_cfg = -{ .low_power_mode = LPM_MODE_SLEEP, +{ .low_power_mode = LPM_MODE_SLEEP, .standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM + | (lpm_standby_wake_source_t)0, + #if BSP_FEATURE_LPM_HAS_SNOOZE .snooze_cancel_sources = LPM_SNOOZE_CANCEL_SOURCE_NONE, - .standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM | (lpm_standby_wake_source_t)0, .snooze_request_source = LPM_SNOOZE_REQUEST_RXD0_FALLING, .snooze_end_sources = (lpm_snooze_end_t)0, .dtc_state_in_snooze = LPM_SNOOZE_DTC_DISABLE, + #endif #if BSP_FEATURE_LPM_HAS_SBYCR_OPE .output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN, #endif @@ -135,598 +20,24 @@ const lpm_cfg_t g_lpm0_cfg = .deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0, .deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0, #endif - .p_extend = NULL, }; - -const lpm_instance_t g_lpm0 = -{ .p_api = &g_lpm_on_lpm, .p_ctrl = &g_lpm0_ctrl, .p_cfg = &g_lpm0_cfg }; -dtc_instance_ctrl_t g_transfer3_ctrl; - -transfer_info_t g_transfer3_info = -{ .dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, - .repeat_area = TRANSFER_REPEAT_AREA_DESTINATION, - .irq = TRANSFER_IRQ_END, - .chain_mode = TRANSFER_CHAIN_MODE_DISABLED, - .src_addr_mode = TRANSFER_ADDR_MODE_FIXED, - .size = TRANSFER_SIZE_2_BYTE, - .mode = TRANSFER_MODE_NORMAL, - .p_dest = (void *)NULL, - .p_src = (void const *)NULL, - .num_blocks = 0, - .length = 0, }; -const dtc_extended_cfg_t g_transfer3_cfg_extend = -{ .activation_source = VECTOR_NUMBER_SPI1_RXI, }; -const transfer_cfg_t g_transfer3_cfg = -{ .p_info = &g_transfer3_info, .p_extend = &g_transfer3_cfg_extend, }; - -/* Instance structure to use this module. */ -const transfer_instance_t g_transfer3 = -{ .p_ctrl = &g_transfer3_ctrl, .p_cfg = &g_transfer3_cfg, .p_api = &g_transfer_on_dtc }; -dtc_instance_ctrl_t g_transfer2_ctrl; - -transfer_info_t g_transfer2_info = -{ .dest_addr_mode = TRANSFER_ADDR_MODE_FIXED, - .repeat_area = TRANSFER_REPEAT_AREA_SOURCE, - .irq = TRANSFER_IRQ_END, - .chain_mode = TRANSFER_CHAIN_MODE_DISABLED, - .src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, - .size = TRANSFER_SIZE_2_BYTE, - .mode = TRANSFER_MODE_NORMAL, - .p_dest = (void *)NULL, - .p_src = (void const *)NULL, - .num_blocks = 0, - .length = 0, }; -const dtc_extended_cfg_t g_transfer2_cfg_extend = -{ .activation_source = VECTOR_NUMBER_SPI1_TXI, }; -const transfer_cfg_t g_transfer2_cfg = -{ .p_info = &g_transfer2_info, .p_extend = &g_transfer2_cfg_extend, }; - -/* Instance structure to use this module. */ -const transfer_instance_t g_transfer2 = -{ .p_ctrl = &g_transfer2_ctrl, .p_cfg = &g_transfer2_cfg, .p_api = &g_transfer_on_dtc }; -spi_instance_ctrl_t g_spi1_ctrl; - -/** SPI extended configuration for SPI HAL driver */ -const spi_extended_cfg_t g_spi1_ext_cfg = -{ .spi_clksyn = SPI_SSL_MODE_CLK_SYN, - .spi_comm = SPI_COMMUNICATION_FULL_DUPLEX, - .ssl_polarity = SPI_SSLP_LOW, - .ssl_select = SPI_SSL_SELECT_SSL0, - .mosi_idle = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE, - .parity = SPI_PARITY_MODE_DISABLE, - .byte_swap = SPI_BYTE_SWAP_DISABLE, - .spck_div = - { - /* Actual calculated bitrate: 15000000. */ .spbr = 3, - .brdv = 0 - }, - .spck_delay = SPI_DELAY_COUNT_1, - .ssl_negation_delay = SPI_DELAY_COUNT_1, - .next_access_delay = SPI_DELAY_COUNT_1 }; - -/** SPI configuration for SPI HAL driver */ -const spi_cfg_t g_spi1_cfg = -{ .channel = 1, - - #if defined(VECTOR_NUMBER_SPI1_RXI) - .rxi_irq = VECTOR_NUMBER_SPI1_RXI, - #else - .rxi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SPI1_TXI) - .txi_irq = VECTOR_NUMBER_SPI1_TXI, - #else - .txi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SPI1_TEI) - .tei_irq = VECTOR_NUMBER_SPI1_TEI, - #else - .tei_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SPI1_ERI) - .eri_irq = VECTOR_NUMBER_SPI1_ERI, - #else - .eri_irq = FSP_INVALID_VECTOR, - #endif - - .rxi_ipl = (12), - .txi_ipl = (12), - .tei_ipl = (12), - .eri_ipl = (12), - - .operating_mode = SPI_MODE_MASTER, - - .clk_phase = SPI_CLK_PHASE_EDGE_ODD, - .clk_polarity = SPI_CLK_POLARITY_LOW, - - .mode_fault = SPI_MODE_FAULT_ERROR_DISABLE, - .bit_order = SPI_BIT_ORDER_MSB_FIRST, - .p_transfer_tx = g_spi1_P_TRANSFER_TX, - .p_transfer_rx = g_spi1_P_TRANSFER_RX, - .p_callback = spi_callback, - - .p_context = NULL, - .p_extend = (void *)&g_spi1_ext_cfg, }; - -/* Instance structure to use this module. */ -const spi_instance_t g_spi1 = -{ .p_ctrl = &g_spi1_ctrl, .p_cfg = &g_spi1_cfg, .p_api = &g_spi_on_spi }; -dtc_instance_ctrl_t g_transfer1_ctrl; - -transfer_info_t g_transfer1_info = -{ .dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, - .repeat_area = TRANSFER_REPEAT_AREA_DESTINATION, - .irq = TRANSFER_IRQ_END, - .chain_mode = TRANSFER_CHAIN_MODE_DISABLED, - .src_addr_mode = TRANSFER_ADDR_MODE_FIXED, - .size = TRANSFER_SIZE_2_BYTE, - .mode = TRANSFER_MODE_NORMAL, - .p_dest = (void *)NULL, - .p_src = (void const *)NULL, - .num_blocks = 0, - .length = 0, }; -const dtc_extended_cfg_t g_transfer1_cfg_extend = -{ .activation_source = VECTOR_NUMBER_SPI0_RXI, }; -const transfer_cfg_t g_transfer1_cfg = -{ .p_info = &g_transfer1_info, .p_extend = &g_transfer1_cfg_extend, }; - -/* Instance structure to use this module. */ -const transfer_instance_t g_transfer1 = -{ .p_ctrl = &g_transfer1_ctrl, .p_cfg = &g_transfer1_cfg, .p_api = &g_transfer_on_dtc }; -dtc_instance_ctrl_t g_transfer0_ctrl; - -transfer_info_t g_transfer0_info = -{ .dest_addr_mode = TRANSFER_ADDR_MODE_FIXED, - .repeat_area = TRANSFER_REPEAT_AREA_SOURCE, - .irq = TRANSFER_IRQ_END, - .chain_mode = TRANSFER_CHAIN_MODE_DISABLED, - .src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, - .size = TRANSFER_SIZE_2_BYTE, - .mode = TRANSFER_MODE_NORMAL, - .p_dest = (void *)NULL, - .p_src = (void const *)NULL, - .num_blocks = 0, - .length = 0, }; -const dtc_extended_cfg_t g_transfer0_cfg_extend = -{ .activation_source = VECTOR_NUMBER_SPI0_TXI, }; -const transfer_cfg_t g_transfer0_cfg = -{ .p_info = &g_transfer0_info, .p_extend = &g_transfer0_cfg_extend, }; - -/* Instance structure to use this module. */ -const transfer_instance_t g_transfer0 = -{ .p_ctrl = &g_transfer0_ctrl, .p_cfg = &g_transfer0_cfg, .p_api = &g_transfer_on_dtc }; -spi_instance_ctrl_t g_spi0_ctrl; - -/** SPI extended configuration for SPI HAL driver */ -const spi_extended_cfg_t g_spi0_ext_cfg = -{ .spi_clksyn = SPI_SSL_MODE_CLK_SYN, - .spi_comm = SPI_COMMUNICATION_FULL_DUPLEX, - .ssl_polarity = SPI_SSLP_LOW, - .ssl_select = SPI_SSL_SELECT_SSL0, - .mosi_idle = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE, - .parity = SPI_PARITY_MODE_DISABLE, - .byte_swap = SPI_BYTE_SWAP_DISABLE, - .spck_div = - { - /* Actual calculated bitrate: 15000000. */ .spbr = 3, - .brdv = 0 - }, - .spck_delay = SPI_DELAY_COUNT_1, - .ssl_negation_delay = SPI_DELAY_COUNT_1, - .next_access_delay = SPI_DELAY_COUNT_1 }; - -/** SPI configuration for SPI HAL driver */ -const spi_cfg_t g_spi0_cfg = -{ .channel = 0, - - #if defined(VECTOR_NUMBER_SPI0_RXI) - .rxi_irq = VECTOR_NUMBER_SPI0_RXI, - #else - .rxi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SPI0_TXI) - .txi_irq = VECTOR_NUMBER_SPI0_TXI, - #else - .txi_irq = FSP_INVALID_VECTOR, + #if BSP_FEATURE_LPM_HAS_PDRAMSCR + .ram_retention_cfg.ram_retention = (uint8_t)(0), + .ram_retention_cfg.tcm_retention = false, #endif - #if defined(VECTOR_NUMBER_SPI0_TEI) - .tei_irq = VECTOR_NUMBER_SPI0_TEI, - #else - .tei_irq = FSP_INVALID_VECTOR, + #if BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP + .ram_retention_cfg.standby_ram_retention = false, #endif - #if defined(VECTOR_NUMBER_SPI0_ERI) - .eri_irq = VECTOR_NUMBER_SPI0_ERI, - #else - .eri_irq = FSP_INVALID_VECTOR, + #if BSP_FEATURE_LPM_HAS_LDO_CONTROL + .ldo_standby_cfg.pll1_ldo = false, + .ldo_standby_cfg.pll2_ldo = false, + .ldo_standby_cfg.hoco_ldo = false, #endif + .p_extend = NULL, }; - .rxi_ipl = (12), - .txi_ipl = (12), - .tei_ipl = (12), - .eri_ipl = (12), - - .operating_mode = SPI_MODE_MASTER, - - .clk_phase = SPI_CLK_PHASE_EDGE_ODD, - .clk_polarity = SPI_CLK_POLARITY_LOW, - - .mode_fault = SPI_MODE_FAULT_ERROR_DISABLE, - .bit_order = SPI_BIT_ORDER_MSB_FIRST, - .p_transfer_tx = g_spi0_P_TRANSFER_TX, - .p_transfer_rx = g_spi0_P_TRANSFER_RX, - .p_callback = spi_callback, +const lpm_instance_t g_lpm0 = +{ .p_api = &g_lpm_on_lpm, .p_ctrl = &g_lpm0_ctrl, .p_cfg = &g_lpm0_cfg }; - .p_context = NULL, - .p_extend = (void *)&g_spi0_ext_cfg, }; -/* Instance structure to use this module. */ -const spi_instance_t g_spi0 = -{ .p_ctrl = &g_spi0_ctrl, .p_cfg = &g_spi0_cfg, .p_api = &g_spi_on_spi }; -icu_instance_ctrl_t g_external_irq15_ctrl; -const external_irq_cfg_t g_external_irq15_cfg = -{ .channel = 15, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ15) - .irq = VECTOR_NUMBER_ICU_IRQ15, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq15 = -{ .p_ctrl = &g_external_irq15_ctrl, .p_cfg = &g_external_irq15_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq14_ctrl; -const external_irq_cfg_t g_external_irq14_cfg = -{ .channel = 14, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ14) - .irq = VECTOR_NUMBER_ICU_IRQ14, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq14 = -{ .p_ctrl = &g_external_irq14_ctrl, .p_cfg = &g_external_irq14_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq13_ctrl; -const external_irq_cfg_t g_external_irq13_cfg = -{ .channel = 13, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ13) - .irq = VECTOR_NUMBER_ICU_IRQ13, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq13 = -{ .p_ctrl = &g_external_irq13_ctrl, .p_cfg = &g_external_irq13_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq12_ctrl; -const external_irq_cfg_t g_external_irq12_cfg = -{ .channel = 12, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ12) - .irq = VECTOR_NUMBER_ICU_IRQ12, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq12 = -{ .p_ctrl = &g_external_irq12_ctrl, .p_cfg = &g_external_irq12_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq11_ctrl; -const external_irq_cfg_t g_external_irq11_cfg = -{ .channel = 11, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ11) - .irq = VECTOR_NUMBER_ICU_IRQ11, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq11 = -{ .p_ctrl = &g_external_irq11_ctrl, .p_cfg = &g_external_irq11_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq10_ctrl; -const external_irq_cfg_t g_external_irq10_cfg = -{ .channel = 10, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ10) - .irq = VECTOR_NUMBER_ICU_IRQ10, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq10 = -{ .p_ctrl = &g_external_irq10_ctrl, .p_cfg = &g_external_irq10_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq9_ctrl; -const external_irq_cfg_t g_external_irq9_cfg = -{ .channel = 9, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ9) - .irq = VECTOR_NUMBER_ICU_IRQ9, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq9 = -{ .p_ctrl = &g_external_irq9_ctrl, .p_cfg = &g_external_irq9_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq8_ctrl; -const external_irq_cfg_t g_external_irq8_cfg = -{ .channel = 8, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ8) - .irq = VECTOR_NUMBER_ICU_IRQ8, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq8 = -{ .p_ctrl = &g_external_irq8_ctrl, .p_cfg = &g_external_irq8_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq7_ctrl; -const external_irq_cfg_t g_external_irq7_cfg = -{ .channel = 7, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ7) - .irq = VECTOR_NUMBER_ICU_IRQ7, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq7 = -{ .p_ctrl = &g_external_irq7_ctrl, .p_cfg = &g_external_irq7_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq6_ctrl; -const external_irq_cfg_t g_external_irq6_cfg = -{ .channel = 6, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ6) - .irq = VECTOR_NUMBER_ICU_IRQ6, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq6 = -{ .p_ctrl = &g_external_irq6_ctrl, .p_cfg = &g_external_irq6_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq5_ctrl; -const external_irq_cfg_t g_external_irq5_cfg = -{ .channel = 5, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ5) - .irq = VECTOR_NUMBER_ICU_IRQ5, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq5 = -{ .p_ctrl = &g_external_irq5_ctrl, .p_cfg = &g_external_irq5_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq4_ctrl; -const external_irq_cfg_t g_external_irq4_cfg = -{ .channel = 4, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ4) - .irq = VECTOR_NUMBER_ICU_IRQ4, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq4 = -{ .p_ctrl = &g_external_irq4_ctrl, .p_cfg = &g_external_irq4_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq3_ctrl; -const external_irq_cfg_t g_external_irq3_cfg = -{ .channel = 3, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ3) - .irq = VECTOR_NUMBER_ICU_IRQ3, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq3 = -{ .p_ctrl = &g_external_irq3_ctrl, .p_cfg = &g_external_irq3_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq2_ctrl; -const external_irq_cfg_t g_external_irq2_cfg = -{ .channel = 2, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ2) - .irq = VECTOR_NUMBER_ICU_IRQ2, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq2 = -{ .p_ctrl = &g_external_irq2_ctrl, .p_cfg = &g_external_irq2_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq1_ctrl; -const external_irq_cfg_t g_external_irq1_cfg = -{ .channel = 1, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ1) - .irq = VECTOR_NUMBER_ICU_IRQ1, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq1 = -{ .p_ctrl = &g_external_irq1_ctrl, .p_cfg = &g_external_irq1_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq0_ctrl; -const external_irq_cfg_t g_external_irq0_cfg = -{ .channel = 0, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ0) - .irq = VECTOR_NUMBER_ICU_IRQ0, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq0 = -{ .p_ctrl = &g_external_irq0_ctrl, .p_cfg = &g_external_irq0_cfg, .p_api = &g_external_irq_on_icu }; -agt_instance_ctrl_t g_timer1_ctrl; -const agt_extended_cfg_t g_timer1_extend = -{ .count_source = AGT_CLOCK_PCLKB, - .agto = AGT_PIN_CFG_DISABLED, - .agtoa = AGT_PIN_CFG_DISABLED, - .agtob = AGT_PIN_CFG_DISABLED, - .measurement_mode = AGT_MEASURE_DISABLED, - .agtio_filter = AGT_AGTIO_FILTER_NONE, - .enable_pin = AGT_ENABLE_PIN_NOT_USED, - .trigger_edge = AGT_TRIGGER_EDGE_RISING, }; -const timer_cfg_t g_timer1_cfg = -{ .mode = TIMER_MODE_PERIODIC, -/* Actual period: 0.0010922666666666667 seconds. Actual duty: 50%. */ .period_counts = 0x10000, - .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 0, .p_callback = callback_agt, - /** If NULL then do not add & */ - #if defined(NULL) - .p_context = NULL, - #else - .p_context = &NULL, - #endif - .p_extend = &g_timer1_extend, - .cycle_end_ipl = (5), - #if defined(VECTOR_NUMBER_AGT0_INT) - .cycle_end_irq = VECTOR_NUMBER_AGT0_INT, - #else - .cycle_end_irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const timer_instance_t g_timer1 = -{ .p_ctrl = &g_timer1_ctrl, .p_cfg = &g_timer1_cfg, .p_api = &g_timer_on_agt }; -agt_instance_ctrl_t g_timer0_ctrl; -const agt_extended_cfg_t g_timer0_extend = -{ .count_source = AGT_CLOCK_PCLKB, - .agto = AGT_PIN_CFG_DISABLED, - .agtoa = AGT_PIN_CFG_DISABLED, - .agtob = AGT_PIN_CFG_DISABLED, - .measurement_mode = AGT_MEASURE_DISABLED, - .agtio_filter = AGT_AGTIO_FILTER_NONE, - .enable_pin = AGT_ENABLE_PIN_NOT_USED, - .trigger_edge = AGT_TRIGGER_EDGE_RISING, }; -const timer_cfg_t g_timer0_cfg = -{ .mode = TIMER_MODE_PERIODIC, -/* Actual period: 0.0010922666666666667 seconds. Actual duty: 50%. */ .period_counts = 0x10000, - .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 0, .p_callback = callback_agt, - /** If NULL then do not add & */ - #if defined(NULL) - .p_context = NULL, - #else - .p_context = &NULL, - #endif - .p_extend = &g_timer0_extend, - .cycle_end_ipl = (5), - #if defined(VECTOR_NUMBER_AGT0_INT) - .cycle_end_irq = VECTOR_NUMBER_AGT0_INT, - #else - .cycle_end_irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const timer_instance_t g_timer0 = -{ .p_ctrl = &g_timer0_ctrl, .p_cfg = &g_timer0_cfg, .p_api = &g_timer_on_agt }; flash_hp_instance_ctrl_t g_flash0_ctrl; const flash_cfg_t g_flash0_cfg = { .data_flash_bgo = false, .p_callback = NULL, .p_context = NULL, @@ -745,239 +56,3 @@ const flash_cfg_t g_flash0_cfg = /* Instance structure to use this module. */ const flash_instance_t g_flash0 = { .p_ctrl = &g_flash0_ctrl, .p_cfg = &g_flash0_cfg, .p_api = &g_flash_on_flash_hp }; -rtc_instance_ctrl_t g_rtc0_ctrl; -const rtc_error_adjustment_cfg_t g_rtc0_err_cfg = -{ .adjustment_mode = RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC, - .adjustment_period = RTC_ERROR_ADJUSTMENT_PERIOD_10_SECOND, - .adjustment_type = RTC_ERROR_ADJUSTMENT_NONE, - .adjustment_value = 0, }; -const rtc_cfg_t g_rtc0_cfg = -{ .clock_source = RTC_CLOCK_SOURCE_LOCO, .freq_compare_value_loco = 255, .p_err_cfg = &g_rtc0_err_cfg, .p_callback = - NULL, - .p_context = NULL, .alarm_ipl = (14), .periodic_ipl = (14), .carry_ipl = (14), - #if defined(VECTOR_NUMBER_RTC_ALARM) - .alarm_irq = VECTOR_NUMBER_RTC_ALARM, - #else - .alarm_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_RTC_PERIOD) - .periodic_irq = VECTOR_NUMBER_RTC_PERIOD, - #else - .periodic_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_RTC_CARRY) - .carry_irq = VECTOR_NUMBER_RTC_CARRY, - #else - .carry_irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const rtc_instance_t g_rtc0 = -{ .p_ctrl = &g_rtc0_ctrl, .p_cfg = &g_rtc0_cfg, .p_api = &g_rtc_on_rtc }; -sci_uart_instance_ctrl_t g_uart9_ctrl; - -baud_setting_t g_uart9_baud_setting = -{ -/* Baud rate calculated with 0.160% error. */ .abcse = 0, - .abcs = 0, .bgdm = 1, .cks = 0, .brr = 64, .mddr = (uint8_t)256, .brme = false -}; - -/** UART extended configuration for UARTonSCI HAL driver */ -const sci_uart_extended_cfg_t g_uart9_cfg_extend = -{ .clock = SCI_UART_CLOCK_INT, - .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, - .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, - .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, - .p_baud_setting = &g_uart9_baud_setting, - .uart_mode = UART_MODE_RS232, - .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, - #if 0 - .flow_control_pin = BSP_IO_PORT_00_PIN_00, - #else - .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), - #endif -}; - -/** UART interface configuration */ -const uart_cfg_t g_uart9_cfg = -{ .channel = 9, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = - user_uart_callback, - .p_context = NULL, .p_extend = &g_uart9_cfg_extend, -#define RA_NOT_DEFINED (1) - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_tx = NULL, - #else - .p_transfer_tx = &RA_NOT_DEFINED, - #endif - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_rx = NULL, - #else - .p_transfer_rx = &RA_NOT_DEFINED, - #endif -#undef RA_NOT_DEFINED - .rxi_ipl = (12), - .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), - #if defined(VECTOR_NUMBER_SCI9_RXI) - .rxi_irq = VECTOR_NUMBER_SCI9_RXI, - #else - .rxi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI9_TXI) - .txi_irq = VECTOR_NUMBER_SCI9_TXI, - #else - .txi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI9_TEI) - .tei_irq = VECTOR_NUMBER_SCI9_TEI, - #else - .tei_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI9_ERI) - .eri_irq = VECTOR_NUMBER_SCI9_ERI, - #else - .eri_irq = FSP_INVALID_VECTOR, - #endif -}; - -/* Instance structure to use this module. */ -const uart_instance_t g_uart9 = -{ .p_ctrl = &g_uart9_ctrl, .p_cfg = &g_uart9_cfg, .p_api = &g_uart_on_sci }; -sci_uart_instance_ctrl_t g_uart7_ctrl; - -baud_setting_t g_uart7_baud_setting = -{ -/* Baud rate calculated with 0.160% error. */ .abcse = 0, - .abcs = 0, .bgdm = 1, .cks = 0, .brr = 64, .mddr = (uint8_t)256, .brme = false -}; - -/** UART extended configuration for UARTonSCI HAL driver */ -const sci_uart_extended_cfg_t g_uart7_cfg_extend = -{ .clock = SCI_UART_CLOCK_INT, - .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, - .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, - .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, - .p_baud_setting = &g_uart7_baud_setting, - .uart_mode = UART_MODE_RS232, - .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, - #if 0 - .flow_control_pin = BSP_IO_PORT_00_PIN_00, - #else - .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), - #endif -}; - -/** UART interface configuration */ -const uart_cfg_t g_uart7_cfg = -{ .channel = 7, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = - user_uart_callback, - .p_context = NULL, .p_extend = &g_uart7_cfg_extend, -#define RA_NOT_DEFINED (1) - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_tx = NULL, - #else - .p_transfer_tx = &RA_NOT_DEFINED, - #endif - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_rx = NULL, - #else - .p_transfer_rx = &RA_NOT_DEFINED, - #endif -#undef RA_NOT_DEFINED - .rxi_ipl = (12), - .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), - #if defined(VECTOR_NUMBER_SCI7_RXI) - .rxi_irq = VECTOR_NUMBER_SCI7_RXI, - #else - .rxi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI7_TXI) - .txi_irq = VECTOR_NUMBER_SCI7_TXI, - #else - .txi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI7_TEI) - .tei_irq = VECTOR_NUMBER_SCI7_TEI, - #else - .tei_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI7_ERI) - .eri_irq = VECTOR_NUMBER_SCI7_ERI, - #else - .eri_irq = FSP_INVALID_VECTOR, - #endif -}; - -/* Instance structure to use this module. */ -const uart_instance_t g_uart7 = -{ .p_ctrl = &g_uart7_ctrl, .p_cfg = &g_uart7_cfg, .p_api = &g_uart_on_sci }; -sci_uart_instance_ctrl_t g_uart0_ctrl; - -baud_setting_t g_uart0_baud_setting = -{ -/* Baud rate calculated with 0.160% error. */ .abcse = 0, - .abcs = 0, .bgdm = 1, .cks = 0, .brr = 64, .mddr = (uint8_t)256, .brme = false -}; - -/** UART extended configuration for UARTonSCI HAL driver */ -const sci_uart_extended_cfg_t g_uart0_cfg_extend = -{ .clock = SCI_UART_CLOCK_INT, - .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, - .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, - .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, - .p_baud_setting = &g_uart0_baud_setting, - .uart_mode = UART_MODE_RS232, - .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, - #if 0 - .flow_control_pin = BSP_IO_PORT_00_PIN_00, - #else - .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), - #endif -}; - -/** UART interface configuration */ -const uart_cfg_t g_uart0_cfg = -{ .channel = 0, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = - user_uart_callback, - .p_context = NULL, .p_extend = &g_uart0_cfg_extend, -#define RA_NOT_DEFINED (1) - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_tx = NULL, - #else - .p_transfer_tx = &RA_NOT_DEFINED, - #endif - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_rx = NULL, - #else - .p_transfer_rx = &RA_NOT_DEFINED, - #endif -#undef RA_NOT_DEFINED - .rxi_ipl = (12), - .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), - #if defined(VECTOR_NUMBER_SCI0_RXI) - .rxi_irq = VECTOR_NUMBER_SCI0_RXI, - #else - .rxi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI0_TXI) - .txi_irq = VECTOR_NUMBER_SCI0_TXI, - #else - .txi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI0_TEI) - .tei_irq = VECTOR_NUMBER_SCI0_TEI, - #else - .tei_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI0_ERI) - .eri_irq = VECTOR_NUMBER_SCI0_ERI, - #else - .eri_irq = FSP_INVALID_VECTOR, - #endif -}; - -/* Instance structure to use this module. */ -const uart_instance_t g_uart0 = -{ .p_ctrl = &g_uart0_ctrl, .p_cfg = &g_uart0_cfg, .p_api = &g_uart_on_sci }; -void g_hal_init(void) { - g_common_init(); -} diff --git a/ports/renesas-ra/boards/EK_RA6M2/ra_gen/hal_data.h b/ports/renesas-ra/boards/EK_RA6M2/ra_gen/hal_data.h index 59d2a9122..51fe21a16 100644 --- a/ports/renesas-ra/boards/EK_RA6M2/ra_gen/hal_data.h +++ b/ports/renesas-ra/boards/EK_RA6M2/ra_gen/hal_data.h @@ -2,318 +2,20 @@ #ifndef HAL_DATA_H_ #define HAL_DATA_H_ #include <stdint.h> -#include "bsp_api.h" #include "common_data.h" -#include "r_iic_master.h" -#include "r_i2c_master_api.h" -#include "r_adc.h" -#include "r_adc_api.h" #include "r_lpm.h" #include "r_lpm_api.h" -#include "r_dtc.h" -#include "r_transfer_api.h" -#include "r_spi.h" -#include "r_icu.h" -#include "r_external_irq_api.h" -#include "r_agt.h" -#include "r_timer_api.h" #include "r_flash_hp.h" #include "r_flash_api.h" -#include "r_rtc.h" -#include "r_rtc_api.h" -#include "r_sci_uart.h" -#include "r_uart_api.h" FSP_HEADER -/* I2C Master on IIC Instance. */ -extern const i2c_master_instance_t g_i2c_master2; -/** Access the I2C Master instance using these structures when calling API functions directly (::p_api is not used). */ -extern iic_master_instance_ctrl_t g_i2c_master2_ctrl; -extern const i2c_master_cfg_t g_i2c_master2_cfg; - -#ifndef callback_iic -void callback_iic(i2c_master_callback_args_t *p_args); -#endif -/** ADC on ADC Instance. */ -extern const adc_instance_t g_adc1; - -/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */ -extern adc_instance_ctrl_t g_adc1_ctrl; -extern const adc_cfg_t g_adc1_cfg; -extern const adc_channel_cfg_t g_adc1_channel_cfg; - -#ifndef NULL -void NULL(adc_callback_args_t *p_args); -#endif -/** ADC on ADC Instance. */ -extern const adc_instance_t g_adc0; - -/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */ -extern adc_instance_ctrl_t g_adc0_ctrl; -extern const adc_cfg_t g_adc0_cfg; -extern const adc_channel_cfg_t g_adc0_channel_cfg; - -#ifndef NULL -void NULL(adc_callback_args_t *p_args); -#endif /** lpm Instance */ extern const lpm_instance_t g_lpm0; /** Access the LPM instance using these structures when calling API functions directly (::p_api is not used). */ extern lpm_instance_ctrl_t g_lpm0_ctrl; extern const lpm_cfg_t g_lpm0_cfg; -/* Transfer on DTC Instance. */ -extern const transfer_instance_t g_transfer3; - -/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ -extern dtc_instance_ctrl_t g_transfer3_ctrl; -extern const transfer_cfg_t g_transfer3_cfg; -/* Transfer on DTC Instance. */ -extern const transfer_instance_t g_transfer2; - -/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ -extern dtc_instance_ctrl_t g_transfer2_ctrl; -extern const transfer_cfg_t g_transfer2_cfg; -/** SPI on SPI Instance. */ -extern const spi_instance_t g_spi1; - -/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */ -extern spi_instance_ctrl_t g_spi1_ctrl; -extern const spi_cfg_t g_spi1_cfg; - -/** Callback used by SPI Instance. */ -#ifndef spi_callback -void spi_callback(spi_callback_args_t *p_args); -#endif - -#define RA_NOT_DEFINED (1) -#if (RA_NOT_DEFINED == g_transfer2) - #define g_spi1_P_TRANSFER_TX (NULL) -#else -#define g_spi1_P_TRANSFER_TX (&g_transfer2) -#endif -#if (RA_NOT_DEFINED == g_transfer3) - #define g_spi1_P_TRANSFER_RX (NULL) -#else -#define g_spi1_P_TRANSFER_RX (&g_transfer3) -#endif -#undef RA_NOT_DEFINED -/* Transfer on DTC Instance. */ -extern const transfer_instance_t g_transfer1; - -/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ -extern dtc_instance_ctrl_t g_transfer1_ctrl; -extern const transfer_cfg_t g_transfer1_cfg; -/* Transfer on DTC Instance. */ -extern const transfer_instance_t g_transfer0; - -/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ -extern dtc_instance_ctrl_t g_transfer0_ctrl; -extern const transfer_cfg_t g_transfer0_cfg; -/** SPI on SPI Instance. */ -extern const spi_instance_t g_spi0; - -/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */ -extern spi_instance_ctrl_t g_spi0_ctrl; -extern const spi_cfg_t g_spi0_cfg; - -/** Callback used by SPI Instance. */ -#ifndef spi_callback -void spi_callback(spi_callback_args_t *p_args); -#endif - -#define RA_NOT_DEFINED (1) -#if (RA_NOT_DEFINED == g_transfer0) - #define g_spi0_P_TRANSFER_TX (NULL) -#else -#define g_spi0_P_TRANSFER_TX (&g_transfer0) -#endif -#if (RA_NOT_DEFINED == g_transfer1) - #define g_spi0_P_TRANSFER_RX (NULL) -#else -#define g_spi0_P_TRANSFER_RX (&g_transfer1) -#endif -#undef RA_NOT_DEFINED -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq15; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq15_ctrl; -extern const external_irq_cfg_t g_external_irq15_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq14; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq14_ctrl; -extern const external_irq_cfg_t g_external_irq14_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq13; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq13_ctrl; -extern const external_irq_cfg_t g_external_irq13_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq12; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq12_ctrl; -extern const external_irq_cfg_t g_external_irq12_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq11; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq11_ctrl; -extern const external_irq_cfg_t g_external_irq11_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq10; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq10_ctrl; -extern const external_irq_cfg_t g_external_irq10_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq9; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq9_ctrl; -extern const external_irq_cfg_t g_external_irq9_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq8; -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq8_ctrl; -extern const external_irq_cfg_t g_external_irq8_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq7; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq7_ctrl; -extern const external_irq_cfg_t g_external_irq7_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq6; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq6_ctrl; -extern const external_irq_cfg_t g_external_irq6_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq5; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq5_ctrl; -extern const external_irq_cfg_t g_external_irq5_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq4; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq4_ctrl; -extern const external_irq_cfg_t g_external_irq4_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq3; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq3_ctrl; -extern const external_irq_cfg_t g_external_irq3_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq2; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq2_ctrl; -extern const external_irq_cfg_t g_external_irq2_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq1; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq1_ctrl; -extern const external_irq_cfg_t g_external_irq1_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq0; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq0_ctrl; -extern const external_irq_cfg_t g_external_irq0_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** AGT Timer Instance */ -extern const timer_instance_t g_timer1; - -/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ -extern agt_instance_ctrl_t g_timer1_ctrl; -extern const timer_cfg_t g_timer1_cfg; - -#ifndef callback_agt -void callback_agt(timer_callback_args_t *p_args); -#endif -/** AGT Timer Instance */ -extern const timer_instance_t g_timer0; - -/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ -extern agt_instance_ctrl_t g_timer0_ctrl; -extern const timer_cfg_t g_timer0_cfg; - -#ifndef callback_agt -void callback_agt(timer_callback_args_t *p_args); -#endif /* Flash on Flash HP Instance */ extern const flash_instance_t g_flash0; @@ -321,53 +23,6 @@ extern const flash_instance_t g_flash0; extern flash_hp_instance_ctrl_t g_flash0_ctrl; extern const flash_cfg_t g_flash0_cfg; -#ifndef NULL -void NULL(flash_callback_args_t *p_args); -#endif -/* RTC Instance. */ -extern const rtc_instance_t g_rtc0; - -/** Access the RTC instance using these structures when calling API functions directly (::p_api is not used). */ -extern rtc_instance_ctrl_t g_rtc0_ctrl; -extern const rtc_cfg_t g_rtc0_cfg; - -#ifndef NULL -void NULL(rtc_callback_args_t *p_args); -#endif -/** UART on SCI Instance. */ -extern const uart_instance_t g_uart9; - -/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ -extern sci_uart_instance_ctrl_t g_uart9_ctrl; -extern const uart_cfg_t g_uart9_cfg; -extern const sci_uart_extended_cfg_t g_uart9_cfg_extend; - -#ifndef user_uart_callback -void user_uart_callback(uart_callback_args_t *p_args); -#endif -/** UART on SCI Instance. */ -extern const uart_instance_t g_uart7; - -/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ -extern sci_uart_instance_ctrl_t g_uart7_ctrl; -extern const uart_cfg_t g_uart7_cfg; -extern const sci_uart_extended_cfg_t g_uart7_cfg_extend; - -#ifndef user_uart_callback -void user_uart_callback(uart_callback_args_t *p_args); -#endif -/** UART on SCI Instance. */ -extern const uart_instance_t g_uart0; - -/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ -extern sci_uart_instance_ctrl_t g_uart0_ctrl; -extern const uart_cfg_t g_uart0_cfg; -extern const sci_uart_extended_cfg_t g_uart0_cfg_extend; - -#ifndef user_uart_callback -void user_uart_callback(uart_callback_args_t *p_args); -#endif void hal_entry(void); -void g_hal_init(void); FSP_FOOTER #endif /* HAL_DATA_H_ */ diff --git a/ports/renesas-ra/boards/EK_RA6M2/ra_gen/pin_data.c b/ports/renesas-ra/boards/EK_RA6M2/ra_gen/pin_data.c index 28330830c..da649d158 100644 --- a/ports/renesas-ra/boards/EK_RA6M2/ra_gen/pin_data.c +++ b/ports/renesas-ra/boards/EK_RA6M2/ra_gen/pin_data.c @@ -1,117 +1,97 @@ /* generated pin source file - do not edit */ #include "bsp_api.h" #include "r_ioport_api.h" -const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { - { - .pin = BSP_IO_PORT_00_PIN_04, - .pin_cfg = ((uint32_t)IOPORT_CFG_ANALOG_ENABLE), - }, - { - .pin = BSP_IO_PORT_01_PIN_00, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), - }, - { - .pin = BSP_IO_PORT_01_PIN_01, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), - }, - { - .pin = BSP_IO_PORT_01_PIN_02, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), - }, - { - .pin = BSP_IO_PORT_01_PIN_03, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), - }, - { - .pin = BSP_IO_PORT_01_PIN_05, - .pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT), - }, - { - .pin = BSP_IO_PORT_01_PIN_06, - .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW), - }, - { - .pin = BSP_IO_PORT_01_PIN_08, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), - }, - { - .pin = BSP_IO_PORT_01_PIN_09, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), - }, - { - .pin = BSP_IO_PORT_01_PIN_10, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), - }, - { - .pin = BSP_IO_PORT_02_PIN_05, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_CTSU), - }, - { - .pin = BSP_IO_PORT_02_PIN_07, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_CTSU), - }, - { - .pin = BSP_IO_PORT_03_PIN_00, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), - }, - { - .pin = BSP_IO_PORT_04_PIN_00, - .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW), - }, - { - .pin = BSP_IO_PORT_04_PIN_01, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9), - }, - { - .pin = BSP_IO_PORT_04_PIN_02, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9), - }, - { - .pin = BSP_IO_PORT_04_PIN_07, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_USB_FS), - }, - { - .pin = BSP_IO_PORT_04_PIN_10, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), - }, - { - .pin = BSP_IO_PORT_04_PIN_11, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), - }, - { - .pin = BSP_IO_PORT_05_PIN_11, - .pin_cfg = ((uint32_t)IOPORT_CFG_DRIVE_MID | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_IIC), - }, - { - .pin = BSP_IO_PORT_05_PIN_12, - .pin_cfg = ((uint32_t)IOPORT_CFG_DRIVE_MID | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_IIC), - }, - { - .pin = BSP_IO_PORT_06_PIN_01, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9), - }, - { - .pin = BSP_IO_PORT_06_PIN_02, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9), - }, - { - .pin = BSP_IO_PORT_07_PIN_00, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), - }, - { - .pin = BSP_IO_PORT_07_PIN_01, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), - }, - { - .pin = BSP_IO_PORT_07_PIN_02, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), - }, - { - .pin = BSP_IO_PORT_07_PIN_03, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), - }, -}; -const ioport_cfg_t g_bsp_pin_cfg = { - .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), - .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = +{ + { .pin = BSP_IO_PORT_00_PIN_04, .pin_cfg = ((uint32_t)IOPORT_CFG_ANALOG_ENABLE) }, + { .pin = BSP_IO_PORT_01_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SPI) }, + { .pin = BSP_IO_PORT_01_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SPI) }, + { .pin = BSP_IO_PORT_01_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SPI) }, + { .pin = BSP_IO_PORT_01_PIN_03, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SPI) }, + { .pin = BSP_IO_PORT_01_PIN_05, .pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE + | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT) }, + { .pin = BSP_IO_PORT_01_PIN_06, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT + | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) }, + { .pin = BSP_IO_PORT_01_PIN_08, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_DEBUG) }, + { .pin = BSP_IO_PORT_01_PIN_09, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_DEBUG) }, + { .pin = BSP_IO_PORT_01_PIN_10, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_DEBUG) }, + { .pin = BSP_IO_PORT_02_PIN_05, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_CTSU) }, + { .pin = BSP_IO_PORT_02_PIN_07, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_CTSU) }, + { .pin = BSP_IO_PORT_03_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_DEBUG) }, + { .pin = BSP_IO_PORT_04_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT + | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) }, + { .pin = BSP_IO_PORT_04_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, + { .pin = BSP_IO_PORT_04_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, + { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_USB_FS) }, + { .pin = BSP_IO_PORT_04_PIN_10, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) }, + { .pin = BSP_IO_PORT_04_PIN_11, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) }, + { .pin = BSP_IO_PORT_05_PIN_11, .pin_cfg = ((uint32_t)IOPORT_CFG_DRIVE_MID + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_IIC) }, + { .pin = BSP_IO_PORT_05_PIN_12, .pin_cfg = ((uint32_t)IOPORT_CFG_DRIVE_MID + | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_IIC) }, + { .pin = BSP_IO_PORT_06_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, + { .pin = BSP_IO_PORT_06_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, + { .pin = BSP_IO_PORT_07_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SPI) }, + { .pin = BSP_IO_PORT_07_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SPI) }, + { .pin = BSP_IO_PORT_07_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SPI) }, + { .pin = BSP_IO_PORT_07_PIN_03, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SPI) }, }; + +const ioport_cfg_t g_bsp_pin_cfg = +{ .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], }; + +#if BSP_TZ_SECURE_BUILD + +void R_BSP_PinCfgSecurityInit(void); + +/* Initialize SAR registers for secure pins. */ +void R_BSP_PinCfgSecurityInit(void) { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #else + uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #endif + memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0])); + + + for (uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++) + { + uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin; + uint32_t port = port_pin >> 8U; + uint32_t pin = port_pin & 0xFFU; + pmsar[port] &= (uint16_t) ~(1U << pin); + } + + for (uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + R_PMISC->PMSAR[i].PMSAR = (uint16_t)pmsar[i]; + #else + R_PMISC->PMSAR[i].PMSAR = pmsar[i]; + #endif + } + +} +#endif diff --git a/ports/renesas-ra/boards/EK_RA6M2/ra_gen/vector_data.c b/ports/renesas-ra/boards/EK_RA6M2/ra_gen/vector_data.c index 35de44a48..db8a3fd39 100644 --- a/ports/renesas-ra/boards/EK_RA6M2/ra_gen/vector_data.c +++ b/ports/renesas-ra/boards/EK_RA6M2/ra_gen/vector_data.c @@ -14,40 +14,40 @@ BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BS [7] = sci_uart_eri_isr, /* SCI7 ERI (Receive error) */ [8] = sci_uart_rxi_isr, /* SCI9 RXI (Received data full) */ [9] = sci_uart_txi_isr, /* SCI9 TXI (Transmit data empty) */ - [10] = sci_uart_tei_isr, /* SCI9 TEI (Transmit end) */ - [11] = sci_uart_eri_isr, /* SCI9 ERI (Receive error) */ - [12] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */ - [13] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */ - [14] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */ - [15] = agt_int_isr, /* AGT0 INT (AGT interrupt) */ - [16] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */ - [17] = r_icu_isr, /* ICU IRQ1 (External pin interrupt 1) */ - [18] = r_icu_isr, /* ICU IRQ2 (External pin interrupt 2) */ - [19] = r_icu_isr, /* ICU IRQ3 (External pin interrupt 3) */ - [20] = r_icu_isr, /* ICU IRQ4 (External pin interrupt 4) */ - [21] = r_icu_isr, /* ICU IRQ5 (External pin interrupt 5) */ - [22] = r_icu_isr, /* ICU IRQ6 (External pin interrupt 6) */ - [23] = r_icu_isr, /* ICU IRQ7 (External pin interrupt 7) */ - [24] = r_icu_isr, /* ICU IRQ8 (External pin interrupt 8) */ - [25] = r_icu_isr, /* ICU IRQ9 (External pin interrupt 9) */ - [26] = r_icu_isr, /* ICU IRQ10 (External pin interrupt 10) */ - [27] = r_icu_isr, /* ICU IRQ11 (External pin interrupt 11) */ - [28] = r_icu_isr, /* ICU IRQ12 (External pin interrupt 12) */ - [29] = r_icu_isr, /* ICU IRQ13 (External pin interrupt 13) */ - [30] = r_icu_isr, /* ICU IRQ14 (External pin interrupt 14) */ - [31] = r_icu_isr, /* ICU IRQ15 (External pin interrupt 15) */ - [32] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */ - [33] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */ - [34] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */ - [35] = spi_eri_isr, /* SPI0 ERI (Error) */ - [36] = spi_rxi_isr, /* SPI1 RXI (Receive buffer full) */ - [37] = spi_txi_isr, /* SPI1 TXI (Transmit buffer empty) */ - [38] = spi_tei_isr, /* SPI1 TEI (Transmission complete event) */ - [39] = spi_eri_isr, /* SPI1 ERI (Error) */ - [40] = iic_master_rxi_isr, /* IIC2 RXI (Receive data full) */ - [41] = iic_master_txi_isr, /* IIC2 TXI (Transmit data empty) */ - [42] = iic_master_tei_isr, /* IIC2 TEI (Transmit end) */ - [43] = iic_master_eri_isr, /* IIC2 ERI (Transfer error) */ + [10] = sci_uart_tei_isr, /* SCI9 TEI (Transmit end) */ + [11] = sci_uart_eri_isr, /* SCI9 ERI (Receive error) */ + [12] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */ + [13] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */ + [14] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */ + [15] = agt_int_isr, /* AGT0 INT (AGT interrupt) */ + [16] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */ + [17] = r_icu_isr, /* ICU IRQ1 (External pin interrupt 1) */ + [18] = r_icu_isr, /* ICU IRQ2 (External pin interrupt 2) */ + [19] = r_icu_isr, /* ICU IRQ3 (External pin interrupt 3) */ + [20] = r_icu_isr, /* ICU IRQ4 (External pin interrupt 4) */ + [21] = r_icu_isr, /* ICU IRQ5 (External pin interrupt 5) */ + [22] = r_icu_isr, /* ICU IRQ6 (External pin interrupt 6) */ + [23] = r_icu_isr, /* ICU IRQ7 (External pin interrupt 7) */ + [24] = r_icu_isr, /* ICU IRQ8 (External pin interrupt 8) */ + [25] = r_icu_isr, /* ICU IRQ9 (External pin interrupt 9) */ + [26] = r_icu_isr, /* ICU IRQ10 (External pin interrupt 10) */ + [27] = r_icu_isr, /* ICU IRQ11 (External pin interrupt 11) */ + [28] = r_icu_isr, /* ICU IRQ12 (External pin interrupt 12) */ + [29] = r_icu_isr, /* ICU IRQ13 (External pin interrupt 13) */ + [30] = r_icu_isr, /* ICU IRQ14 (External pin interrupt 14) */ + [31] = r_icu_isr, /* ICU IRQ15 (External pin interrupt 15) */ + [32] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */ + [33] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */ + [34] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */ + [35] = spi_eri_isr, /* SPI0 ERI (Error) */ + [36] = spi_rxi_isr, /* SPI1 RXI (Receive buffer full) */ + [37] = spi_txi_isr, /* SPI1 TXI (Transmit buffer empty) */ + [38] = spi_tei_isr, /* SPI1 TEI (Transmission complete event) */ + [39] = spi_eri_isr, /* SPI1 ERI (Error) */ + [40] = iic_master_rxi_isr, /* IIC2 RXI (Receive data full) */ + [41] = iic_master_txi_isr, /* IIC2 TXI (Transmit data empty) */ + [42] = iic_master_tei_isr, /* IIC2 TEI (Transmit end) */ + [43] = iic_master_eri_isr, /* IIC2 ERI (Transfer error) */ }; const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = { @@ -61,39 +61,39 @@ const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENT [7] = BSP_PRV_IELS_ENUM(EVENT_SCI7_ERI), /* SCI7 ERI (Receive error) */ [8] = BSP_PRV_IELS_ENUM(EVENT_SCI9_RXI), /* SCI9 RXI (Received data full) */ [9] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TXI), /* SCI9 TXI (Transmit data empty) */ - [10] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TEI), /* SCI9 TEI (Transmit end) */ - [11] = BSP_PRV_IELS_ENUM(EVENT_SCI9_ERI), /* SCI9 ERI (Receive error) */ - [12] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */ - [13] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */ - [14] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */ - [15] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */ - [16] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ0), /* ICU IRQ0 (External pin interrupt 0) */ - [17] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ1), /* ICU IRQ1 (External pin interrupt 1) */ - [18] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ2), /* ICU IRQ2 (External pin interrupt 2) */ - [19] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ3), /* ICU IRQ3 (External pin interrupt 3) */ - [20] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ4), /* ICU IRQ4 (External pin interrupt 4) */ - [21] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ5), /* ICU IRQ5 (External pin interrupt 5) */ - [22] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ6), /* ICU IRQ6 (External pin interrupt 6) */ - [23] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ7), /* ICU IRQ7 (External pin interrupt 7) */ - [24] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ8), /* ICU IRQ8 (External pin interrupt 8) */ - [25] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ9), /* ICU IRQ9 (External pin interrupt 9) */ - [26] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ10), /* ICU IRQ10 (External pin interrupt 10) */ - [27] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ11), /* ICU IRQ11 (External pin interrupt 11) */ - [28] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ12), /* ICU IRQ12 (External pin interrupt 12) */ - [29] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ13), /* ICU IRQ13 (External pin interrupt 13) */ - [30] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ14), /* ICU IRQ14 (External pin interrupt 14) */ - [31] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ15), /* ICU IRQ15 (External pin interrupt 15) */ - [32] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */ - [33] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */ - [34] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */ - [35] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */ - [36] = BSP_PRV_IELS_ENUM(EVENT_SPI1_RXI), /* SPI1 RXI (Receive buffer full) */ - [37] = BSP_PRV_IELS_ENUM(EVENT_SPI1_TXI), /* SPI1 TXI (Transmit buffer empty) */ - [38] = BSP_PRV_IELS_ENUM(EVENT_SPI1_TEI), /* SPI1 TEI (Transmission complete event) */ - [39] = BSP_PRV_IELS_ENUM(EVENT_SPI1_ERI), /* SPI1 ERI (Error) */ - [40] = BSP_PRV_IELS_ENUM(EVENT_IIC2_RXI), /* IIC2 RXI (Receive data full) */ - [41] = BSP_PRV_IELS_ENUM(EVENT_IIC2_TXI), /* IIC2 TXI (Transmit data empty) */ - [42] = BSP_PRV_IELS_ENUM(EVENT_IIC2_TEI), /* IIC2 TEI (Transmit end) */ - [43] = BSP_PRV_IELS_ENUM(EVENT_IIC2_ERI), /* IIC2 ERI (Transfer error) */ + [10] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TEI), /* SCI9 TEI (Transmit end) */ + [11] = BSP_PRV_IELS_ENUM(EVENT_SCI9_ERI), /* SCI9 ERI (Receive error) */ + [12] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */ + [13] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */ + [14] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */ + [15] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */ + [16] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ0), /* ICU IRQ0 (External pin interrupt 0) */ + [17] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ1), /* ICU IRQ1 (External pin interrupt 1) */ + [18] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ2), /* ICU IRQ2 (External pin interrupt 2) */ + [19] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ3), /* ICU IRQ3 (External pin interrupt 3) */ + [20] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ4), /* ICU IRQ4 (External pin interrupt 4) */ + [21] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ5), /* ICU IRQ5 (External pin interrupt 5) */ + [22] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ6), /* ICU IRQ6 (External pin interrupt 6) */ + [23] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ7), /* ICU IRQ7 (External pin interrupt 7) */ + [24] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ8), /* ICU IRQ8 (External pin interrupt 8) */ + [25] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ9), /* ICU IRQ9 (External pin interrupt 9) */ + [26] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ10), /* ICU IRQ10 (External pin interrupt 10) */ + [27] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ11), /* ICU IRQ11 (External pin interrupt 11) */ + [28] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ12), /* ICU IRQ12 (External pin interrupt 12) */ + [29] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ13), /* ICU IRQ13 (External pin interrupt 13) */ + [30] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ14), /* ICU IRQ14 (External pin interrupt 14) */ + [31] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ15), /* ICU IRQ15 (External pin interrupt 15) */ + [32] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */ + [33] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */ + [34] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */ + [35] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */ + [36] = BSP_PRV_IELS_ENUM(EVENT_SPI1_RXI), /* SPI1 RXI (Receive buffer full) */ + [37] = BSP_PRV_IELS_ENUM(EVENT_SPI1_TXI), /* SPI1 TXI (Transmit buffer empty) */ + [38] = BSP_PRV_IELS_ENUM(EVENT_SPI1_TEI), /* SPI1 TEI (Transmission complete event) */ + [39] = BSP_PRV_IELS_ENUM(EVENT_SPI1_ERI), /* SPI1 ERI (Error) */ + [40] = BSP_PRV_IELS_ENUM(EVENT_IIC2_RXI), /* IIC2 RXI (Receive data full) */ + [41] = BSP_PRV_IELS_ENUM(EVENT_IIC2_TXI), /* IIC2 TXI (Transmit data empty) */ + [42] = BSP_PRV_IELS_ENUM(EVENT_IIC2_TEI), /* IIC2 TEI (Transmit end) */ + [43] = BSP_PRV_IELS_ENUM(EVENT_IIC2_ERI), /* IIC2 ERI (Transfer error) */ }; #endif diff --git a/ports/renesas-ra/boards/EK_RA6M2/ra_gen/vector_data.h b/ports/renesas-ra/boards/EK_RA6M2/ra_gen/vector_data.h index 6629824be..955834de5 100644 --- a/ports/renesas-ra/boards/EK_RA6M2/ra_gen/vector_data.h +++ b/ports/renesas-ra/boards/EK_RA6M2/ra_gen/vector_data.h @@ -1,6 +1,9 @@ /* generated vector header file - do not edit */ #ifndef VECTOR_DATA_H #define VECTOR_DATA_H +#ifdef __cplusplus +extern "C" { +#endif /* Number of interrupts allocated */ #ifndef VECTOR_DATA_IRQ_COUNT #define VECTOR_DATA_IRQ_COUNT (44) @@ -25,105 +28,94 @@ void iic_master_eri_isr(void); /* Vector table allocations */ #define VECTOR_NUMBER_SCI0_RXI ((IRQn_Type)0) /* SCI0 RXI (Receive data full) */ +#define SCI0_RXI_IRQn ((IRQn_Type)0) /* SCI0 RXI (Receive data full) */ #define VECTOR_NUMBER_SCI0_TXI ((IRQn_Type)1) /* SCI0 TXI (Transmit data empty) */ +#define SCI0_TXI_IRQn ((IRQn_Type)1) /* SCI0 TXI (Transmit data empty) */ #define VECTOR_NUMBER_SCI0_TEI ((IRQn_Type)2) /* SCI0 TEI (Transmit end) */ +#define SCI0_TEI_IRQn ((IRQn_Type)2) /* SCI0 TEI (Transmit end) */ #define VECTOR_NUMBER_SCI0_ERI ((IRQn_Type)3) /* SCI0 ERI (Receive error) */ +#define SCI0_ERI_IRQn ((IRQn_Type)3) /* SCI0 ERI (Receive error) */ #define VECTOR_NUMBER_SCI7_RXI ((IRQn_Type)4) /* SCI7 RXI (Received data full) */ +#define SCI7_RXI_IRQn ((IRQn_Type)4) /* SCI7 RXI (Received data full) */ #define VECTOR_NUMBER_SCI7_TXI ((IRQn_Type)5) /* SCI7 TXI (Transmit data empty) */ +#define SCI7_TXI_IRQn ((IRQn_Type)5) /* SCI7 TXI (Transmit data empty) */ #define VECTOR_NUMBER_SCI7_TEI ((IRQn_Type)6) /* SCI7 TEI (Transmit end) */ +#define SCI7_TEI_IRQn ((IRQn_Type)6) /* SCI7 TEI (Transmit end) */ #define VECTOR_NUMBER_SCI7_ERI ((IRQn_Type)7) /* SCI7 ERI (Receive error) */ +#define SCI7_ERI_IRQn ((IRQn_Type)7) /* SCI7 ERI (Receive error) */ #define VECTOR_NUMBER_SCI9_RXI ((IRQn_Type)8) /* SCI9 RXI (Received data full) */ +#define SCI9_RXI_IRQn ((IRQn_Type)8) /* SCI9 RXI (Received data full) */ #define VECTOR_NUMBER_SCI9_TXI ((IRQn_Type)9) /* SCI9 TXI (Transmit data empty) */ +#define SCI9_TXI_IRQn ((IRQn_Type)9) /* SCI9 TXI (Transmit data empty) */ #define VECTOR_NUMBER_SCI9_TEI ((IRQn_Type)10) /* SCI9 TEI (Transmit end) */ +#define SCI9_TEI_IRQn ((IRQn_Type)10) /* SCI9 TEI (Transmit end) */ #define VECTOR_NUMBER_SCI9_ERI ((IRQn_Type)11) /* SCI9 ERI (Receive error) */ +#define SCI9_ERI_IRQn ((IRQn_Type)11) /* SCI9 ERI (Receive error) */ #define VECTOR_NUMBER_RTC_ALARM ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */ +#define RTC_ALARM_IRQn ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */ #define VECTOR_NUMBER_RTC_PERIOD ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */ +#define RTC_PERIOD_IRQn ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */ #define VECTOR_NUMBER_RTC_CARRY ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */ +#define RTC_CARRY_IRQn ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */ #define VECTOR_NUMBER_AGT0_INT ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */ +#define AGT0_INT_IRQn ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */ #define VECTOR_NUMBER_ICU_IRQ0 ((IRQn_Type)16) /* ICU IRQ0 (External pin interrupt 0) */ +#define ICU_IRQ0_IRQn ((IRQn_Type)16) /* ICU IRQ0 (External pin interrupt 0) */ #define VECTOR_NUMBER_ICU_IRQ1 ((IRQn_Type)17) /* ICU IRQ1 (External pin interrupt 1) */ +#define ICU_IRQ1_IRQn ((IRQn_Type)17) /* ICU IRQ1 (External pin interrupt 1) */ #define VECTOR_NUMBER_ICU_IRQ2 ((IRQn_Type)18) /* ICU IRQ2 (External pin interrupt 2) */ +#define ICU_IRQ2_IRQn ((IRQn_Type)18) /* ICU IRQ2 (External pin interrupt 2) */ #define VECTOR_NUMBER_ICU_IRQ3 ((IRQn_Type)19) /* ICU IRQ3 (External pin interrupt 3) */ +#define ICU_IRQ3_IRQn ((IRQn_Type)19) /* ICU IRQ3 (External pin interrupt 3) */ #define VECTOR_NUMBER_ICU_IRQ4 ((IRQn_Type)20) /* ICU IRQ4 (External pin interrupt 4) */ +#define ICU_IRQ4_IRQn ((IRQn_Type)20) /* ICU IRQ4 (External pin interrupt 4) */ #define VECTOR_NUMBER_ICU_IRQ5 ((IRQn_Type)21) /* ICU IRQ5 (External pin interrupt 5) */ +#define ICU_IRQ5_IRQn ((IRQn_Type)21) /* ICU IRQ5 (External pin interrupt 5) */ #define VECTOR_NUMBER_ICU_IRQ6 ((IRQn_Type)22) /* ICU IRQ6 (External pin interrupt 6) */ +#define ICU_IRQ6_IRQn ((IRQn_Type)22) /* ICU IRQ6 (External pin interrupt 6) */ #define VECTOR_NUMBER_ICU_IRQ7 ((IRQn_Type)23) /* ICU IRQ7 (External pin interrupt 7) */ +#define ICU_IRQ7_IRQn ((IRQn_Type)23) /* ICU IRQ7 (External pin interrupt 7) */ #define VECTOR_NUMBER_ICU_IRQ8 ((IRQn_Type)24) /* ICU IRQ8 (External pin interrupt 8) */ +#define ICU_IRQ8_IRQn ((IRQn_Type)24) /* ICU IRQ8 (External pin interrupt 8) */ #define VECTOR_NUMBER_ICU_IRQ9 ((IRQn_Type)25) /* ICU IRQ9 (External pin interrupt 9) */ +#define ICU_IRQ9_IRQn ((IRQn_Type)25) /* ICU IRQ9 (External pin interrupt 9) */ #define VECTOR_NUMBER_ICU_IRQ10 ((IRQn_Type)26) /* ICU IRQ10 (External pin interrupt 10) */ +#define ICU_IRQ10_IRQn ((IRQn_Type)26) /* ICU IRQ10 (External pin interrupt 10) */ #define VECTOR_NUMBER_ICU_IRQ11 ((IRQn_Type)27) /* ICU IRQ11 (External pin interrupt 11) */ +#define ICU_IRQ11_IRQn ((IRQn_Type)27) /* ICU IRQ11 (External pin interrupt 11) */ #define VECTOR_NUMBER_ICU_IRQ12 ((IRQn_Type)28) /* ICU IRQ12 (External pin interrupt 12) */ +#define ICU_IRQ12_IRQn ((IRQn_Type)28) /* ICU IRQ12 (External pin interrupt 12) */ #define VECTOR_NUMBER_ICU_IRQ13 ((IRQn_Type)29) /* ICU IRQ13 (External pin interrupt 13) */ +#define ICU_IRQ13_IRQn ((IRQn_Type)29) /* ICU IRQ13 (External pin interrupt 13) */ #define VECTOR_NUMBER_ICU_IRQ14 ((IRQn_Type)30) /* ICU IRQ14 (External pin interrupt 14) */ +#define ICU_IRQ14_IRQn ((IRQn_Type)30) /* ICU IRQ14 (External pin interrupt 14) */ #define VECTOR_NUMBER_ICU_IRQ15 ((IRQn_Type)31) /* ICU IRQ15 (External pin interrupt 15) */ +#define ICU_IRQ15_IRQn ((IRQn_Type)31) /* ICU IRQ15 (External pin interrupt 15) */ #define VECTOR_NUMBER_SPI0_RXI ((IRQn_Type)32) /* SPI0 RXI (Receive buffer full) */ +#define SPI0_RXI_IRQn ((IRQn_Type)32) /* SPI0 RXI (Receive buffer full) */ #define VECTOR_NUMBER_SPI0_TXI ((IRQn_Type)33) /* SPI0 TXI (Transmit buffer empty) */ +#define SPI0_TXI_IRQn ((IRQn_Type)33) /* SPI0 TXI (Transmit buffer empty) */ #define VECTOR_NUMBER_SPI0_TEI ((IRQn_Type)34) /* SPI0 TEI (Transmission complete event) */ +#define SPI0_TEI_IRQn ((IRQn_Type)34) /* SPI0 TEI (Transmission complete event) */ #define VECTOR_NUMBER_SPI0_ERI ((IRQn_Type)35) /* SPI0 ERI (Error) */ +#define SPI0_ERI_IRQn ((IRQn_Type)35) /* SPI0 ERI (Error) */ #define VECTOR_NUMBER_SPI1_RXI ((IRQn_Type)36) /* SPI1 RXI (Receive buffer full) */ +#define SPI1_RXI_IRQn ((IRQn_Type)36) /* SPI1 RXI (Receive buffer full) */ #define VECTOR_NUMBER_SPI1_TXI ((IRQn_Type)37) /* SPI1 TXI (Transmit buffer empty) */ +#define SPI1_TXI_IRQn ((IRQn_Type)37) /* SPI1 TXI (Transmit buffer empty) */ #define VECTOR_NUMBER_SPI1_TEI ((IRQn_Type)38) /* SPI1 TEI (Transmission complete event) */ +#define SPI1_TEI_IRQn ((IRQn_Type)38) /* SPI1 TEI (Transmission complete event) */ #define VECTOR_NUMBER_SPI1_ERI ((IRQn_Type)39) /* SPI1 ERI (Error) */ +#define SPI1_ERI_IRQn ((IRQn_Type)39) /* SPI1 ERI (Error) */ #define VECTOR_NUMBER_IIC2_RXI ((IRQn_Type)40) /* IIC2 RXI (Receive data full) */ +#define IIC2_RXI_IRQn ((IRQn_Type)40) /* IIC2 RXI (Receive data full) */ #define VECTOR_NUMBER_IIC2_TXI ((IRQn_Type)41) /* IIC2 TXI (Transmit data empty) */ +#define IIC2_TXI_IRQn ((IRQn_Type)41) /* IIC2 TXI (Transmit data empty) */ #define VECTOR_NUMBER_IIC2_TEI ((IRQn_Type)42) /* IIC2 TEI (Transmit end) */ +#define IIC2_TEI_IRQn ((IRQn_Type)42) /* IIC2 TEI (Transmit end) */ #define VECTOR_NUMBER_IIC2_ERI ((IRQn_Type)43) /* IIC2 ERI (Transfer error) */ -typedef enum IRQn -{ - Reset_IRQn = -15, - NonMaskableInt_IRQn = -14, - HardFault_IRQn = -13, - MemoryManagement_IRQn = -12, - BusFault_IRQn = -11, - UsageFault_IRQn = -10, - SecureFault_IRQn = -9, - SVCall_IRQn = -5, - DebugMonitor_IRQn = -4, - PendSV_IRQn = -2, - SysTick_IRQn = -1, - SCI0_RXI_IRQn = 0, /* SCI0 RXI (Receive data full) */ - SCI0_TXI_IRQn = 1, /* SCI0 TXI (Transmit data empty) */ - SCI0_TEI_IRQn = 2, /* SCI0 TEI (Transmit end) */ - SCI0_ERI_IRQn = 3, /* SCI0 ERI (Receive error) */ - SCI7_RXI_IRQn = 4, /* SCI7 RXI (Received data full) */ - SCI7_TXI_IRQn = 5, /* SCI7 TXI (Transmit data empty) */ - SCI7_TEI_IRQn = 6, /* SCI7 TEI (Transmit end) */ - SCI7_ERI_IRQn = 7, /* SCI7 ERI (Receive error) */ - SCI9_RXI_IRQn = 8, /* SCI9 RXI (Received data full) */ - SCI9_TXI_IRQn = 9, /* SCI9 TXI (Transmit data empty) */ - SCI9_TEI_IRQn = 10, /* SCI9 TEI (Transmit end) */ - SCI9_ERI_IRQn = 11, /* SCI9 ERI (Receive error) */ - RTC_ALARM_IRQn = 12, /* RTC ALARM (Alarm interrupt) */ - RTC_PERIOD_IRQn = 13, /* RTC PERIOD (Periodic interrupt) */ - RTC_CARRY_IRQn = 14, /* RTC CARRY (Carry interrupt) */ - AGT0_INT_IRQn = 15, /* AGT0 INT (AGT interrupt) */ - ICU_IRQ0_IRQn = 16, /* ICU IRQ0 (External pin interrupt 0) */ - ICU_IRQ1_IRQn = 17, /* ICU IRQ1 (External pin interrupt 1) */ - ICU_IRQ2_IRQn = 18, /* ICU IRQ2 (External pin interrupt 2) */ - ICU_IRQ3_IRQn = 19, /* ICU IRQ3 (External pin interrupt 3) */ - ICU_IRQ4_IRQn = 20, /* ICU IRQ4 (External pin interrupt 4) */ - ICU_IRQ5_IRQn = 21, /* ICU IRQ5 (External pin interrupt 5) */ - ICU_IRQ6_IRQn = 22, /* ICU IRQ6 (External pin interrupt 6) */ - ICU_IRQ7_IRQn = 23, /* ICU IRQ7 (External pin interrupt 7) */ - ICU_IRQ8_IRQn = 24, /* ICU IRQ8 (External pin interrupt 8) */ - ICU_IRQ9_IRQn = 25, /* ICU IRQ9 (External pin interrupt 9) */ - ICU_IRQ10_IRQn = 26, /* ICU IRQ10 (External pin interrupt 10) */ - ICU_IRQ11_IRQn = 27, /* ICU IRQ11 (External pin interrupt 11) */ - ICU_IRQ12_IRQn = 28, /* ICU IRQ12 (External pin interrupt 12) */ - ICU_IRQ13_IRQn = 29, /* ICU IRQ13 (External pin interrupt 13) */ - ICU_IRQ14_IRQn = 30, /* ICU IRQ14 (External pin interrupt 14) */ - ICU_IRQ15_IRQn = 31, /* ICU IRQ15 (External pin interrupt 15) */ - SPI0_RXI_IRQn = 32, /* SPI0 RXI (Receive buffer full) */ - SPI0_TXI_IRQn = 33, /* SPI0 TXI (Transmit buffer empty) */ - SPI0_TEI_IRQn = 34, /* SPI0 TEI (Transmission complete event) */ - SPI0_ERI_IRQn = 35, /* SPI0 ERI (Error) */ - SPI1_RXI_IRQn = 36, /* SPI1 RXI (Receive buffer full) */ - SPI1_TXI_IRQn = 37, /* SPI1 TXI (Transmit buffer empty) */ - SPI1_TEI_IRQn = 38, /* SPI1 TEI (Transmission complete event) */ - SPI1_ERI_IRQn = 39, /* SPI1 ERI (Error) */ - IIC2_RXI_IRQn = 40, /* IIC2 RXI (Receive data full) */ - IIC2_TXI_IRQn = 41, /* IIC2 TXI (Transmit data empty) */ - IIC2_TEI_IRQn = 42, /* IIC2 TEI (Transmit end) */ - IIC2_ERI_IRQn = 43, /* IIC2 ERI (Transfer error) */ -} IRQn_Type; +#define IIC2_ERI_IRQn ((IRQn_Type)43) /* IIC2 ERI (Transfer error) */ +#ifdef __cplusplus +} +#endif #endif /* VECTOR_DATA_H */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/board_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/board_cfg.h index 87cb51e00..a57cf3249 100644 --- a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/board_cfg.h +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/board_cfg.h @@ -1,5 +1,13 @@ /* generated configuration header file - do not edit */ #ifndef BOARD_CFG_H_ #define BOARD_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + void bsp_init(void *p_args); + +#ifdef __cplusplus +} +#endif #endif /* BOARD_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_cfg.h index 9940d7ed3..e341e9994 100644 --- a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_cfg.h +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -1,6 +1,10 @@ /* generated configuration header file - do not edit */ #ifndef BSP_CFG_H_ #define BSP_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #include "bsp_clock_cfg.h" #include "bsp_mcu_family_cfg.h" #include "board_cfg.h" @@ -14,7 +18,13 @@ #define BSP_CFG_RTOS (0) #endif #endif +#ifndef BSP_CFG_RTC_USED +#define BSP_CFG_RTC_USED (1) +#endif #undef RA_NOT_DEFINED +#if defined(_RA_BOOT_IMAGE) +#define BSP_CFG_BOOT_IMAGE (1) +#endif #define BSP_CFG_MCU_VCC_MV (3300) #define BSP_CFG_STACK_MAIN_BYTES (0x1000) #define BSP_CFG_HEAP_BYTES (0x4980) @@ -25,15 +35,14 @@ #define BSP_CFG_PFS_PROTECT ((1)) #define BSP_CFG_C_RUNTIME_INIT ((1)) +#define BSP_CFG_EARLY_INIT ((0)) -#define BSP_CFG_SOFT_RESET_SUPPORTED ((0)) +#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) #endif -#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) -#endif + #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) #endif @@ -46,4 +55,8 @@ #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 #endif + +#ifdef __cplusplus +} +#endif #endif /* BSP_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h index 713af295b..d840f2495 100644 --- a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -2,6 +2,7 @@ #ifndef BSP_MCU_DEVICE_PN_CFG_H_ #define BSP_MCU_DEVICE_PN_CFG_H_ #define BSP_MCU_R7FA4M1AB3CFM +#define BSP_MCU_FEATURE_SET ('A') #define BSP_ROM_SIZE_BYTES (262144) #define BSP_RAM_SIZE_BYTES (32768) #define BSP_DATA_FLASH_SIZE_BYTES (8192) diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h index 4766823b3..a9b4de20c 100644 --- a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -1,6 +1,10 @@ /* generated configuration header file - do not edit */ #ifndef BSP_MCU_FAMILY_CFG_H_ #define BSP_MCU_FAMILY_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #include "bsp_mcu_device_pn_cfg.h" #include "bsp_mcu_device_cfg.h" #include "../../../ra/fsp/src/bsp/mcu/ra4m1/bsp_mcu_info.h" @@ -22,7 +26,6 @@ #endif #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) #define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) -#define BSP_MCU_VBATT_SUPPORT (1) #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) @@ -50,7 +53,9 @@ #define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) #define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) #define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) - +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ #define BSP_PRV_IELS_ENUM(vector) (ELC_##vector) @@ -71,4 +76,8 @@ #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) #endif + +#ifdef __cplusplus +} +#endif #endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_adc_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_adc_cfg.h index 9c59889ca..be8a42720 100644 --- a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_adc_cfg.h +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_adc_cfg.h @@ -1,5 +1,13 @@ /* generated configuration header file - do not edit */ #ifndef R_ADC_CFG_H_ #define R_ADC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #define ADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif #endif /* R_ADC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_agt_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_agt_cfg.h deleted file mode 100644 index d3ab55923..000000000 --- a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_agt_cfg.h +++ /dev/null @@ -1,7 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_AGT_CFG_H_ -#define R_AGT_CFG_H_ -#define AGT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#define AGT_CFG_OUTPUT_SUPPORT_ENABLE (0) -#define AGT_CFG_INPUT_SUPPORT_ENABLE (0) -#endif /* R_AGT_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_dtc_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_dtc_cfg.h deleted file mode 100644 index 21405f967..000000000 --- a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_dtc_cfg.h +++ /dev/null @@ -1,6 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_DTC_CFG_H_ -#define R_DTC_CFG_H_ -#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#define DTC_CFG_VECTOR_TABLE_SECTION_NAME ".fsp_dtc_vector_table" -#endif /* R_DTC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_flash_lp_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_flash_lp_cfg.h index 26879f9f4..7f285cace 100644 --- a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_flash_lp_cfg.h +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_flash_lp_cfg.h @@ -1,7 +1,15 @@ /* generated configuration header file - do not edit */ #ifndef R_FLASH_LP_CFG_H_ #define R_FLASH_LP_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #define FLASH_LP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) #define FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (1) #define FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (0) + +#ifdef __cplusplus +} +#endif #endif /* R_FLASH_LP_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_icu_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_icu_cfg.h deleted file mode 100644 index 5e77b6980..000000000 --- a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_icu_cfg.h +++ /dev/null @@ -1,5 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_ICU_CFG_H_ -#define R_ICU_CFG_H_ -#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#endif /* R_ICU_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_iic_master_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_iic_master_cfg.h deleted file mode 100644 index 595ea938d..000000000 --- a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_iic_master_cfg.h +++ /dev/null @@ -1,7 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_IIC_MASTER_CFG_H_ -#define R_IIC_MASTER_CFG_H_ -#define IIC_MASTER_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#define IIC_MASTER_CFG_DTC_ENABLE (0) -#define IIC_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE (0) -#endif /* R_IIC_MASTER_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_ioport_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_ioport_cfg.h index 6b4353d23..d2688bf5b 100644 --- a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_ioport_cfg.h +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -1,5 +1,13 @@ /* generated configuration header file - do not edit */ #ifndef R_IOPORT_CFG_H_ #define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif #endif /* R_IOPORT_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_lpm_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_lpm_cfg.h index 5f4d5c4a7..6712eee6a 100644 --- a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_lpm_cfg.h +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_lpm_cfg.h @@ -1,5 +1,14 @@ /* generated configuration header file - do not edit */ #ifndef R_LPM_CFG_H_ #define R_LPM_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + #define LPM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define LPM_CFG_STANDBY_LIMIT (0) + +#ifdef __cplusplus +} +#endif #endif /* R_LPM_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_rtc_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_rtc_cfg.h deleted file mode 100644 index 484b7ed04..000000000 --- a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_rtc_cfg.h +++ /dev/null @@ -1,5 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_RTC_CFG_H_ -#define R_RTC_CFG_H_ -#define RTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#endif /* R_RTC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_sci_uart_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_sci_uart_cfg.h deleted file mode 100644 index c70c0be34..000000000 --- a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_sci_uart_cfg.h +++ /dev/null @@ -1,8 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_SCI_UART_CFG_H_ -#define R_SCI_UART_CFG_H_ -#define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#define SCI_UART_CFG_FIFO_SUPPORT (0) -#define SCI_UART_CFG_DTC_SUPPORTED (0) -#define SCI_UART_CFG_FLOW_CONTROL_SUPPORT (0) -#endif /* R_SCI_UART_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_spi_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_spi_cfg.h deleted file mode 100644 index 861fe1219..000000000 --- a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_spi_cfg.h +++ /dev/null @@ -1,7 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_SPI_CFG_H_ -#define R_SPI_CFG_H_ -#define SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) -#define SPI_DTC_SUPPORT_ENABLE (1) -#define SPI_TRANSMIT_FROM_RXI_ISR (0) -#endif /* R_SPI_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/bsp_clock_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/bsp_clock_cfg.h index cf28c33d7..5f407b90f 100644 --- a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/bsp_clock_cfg.h +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/bsp_clock_cfg.h @@ -7,7 +7,7 @@ #define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ #define BSP_CFG_HOCO_FREQUENCY (0) /* HOCO 24MHz */ #define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */ -#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_8_0 /* PLL Mul x8 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(8U, 0U) /* PLL Mul x8 */ #define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ #define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/common_data.c b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/common_data.c index 34aad762f..48640e8b7 100644 --- a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/common_data.c +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/common_data.c @@ -1,4 +1,3 @@ -/* generated common source file - do not edit */ #include "common_data.h" ioport_instance_ctrl_t g_ioport_ctrl; const ioport_instance_t g_ioport = diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/common_data.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/common_data.h index e2eb70836..a81384f8f 100644 --- a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/common_data.h +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/common_data.h @@ -3,6 +3,8 @@ #define COMMON_DATA_H_ #include <stdint.h> #include "bsp_api.h" +#include "r_icu.h" +#include "r_external_irq_api.h" #include "r_ioport.h" #include "bsp_pin_cfg.h" FSP_HEADER @@ -11,6 +13,5 @@ extern const ioport_instance_t g_ioport; /* IOPORT control structure. */ extern ioport_instance_ctrl_t g_ioport_ctrl; -void g_common_init(void); FSP_FOOTER #endif /* COMMON_DATA_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/hal_data.c b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/hal_data.c index ebef37a7d..64c728b99 100644 --- a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/hal_data.c +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/hal_data.c @@ -1,136 +1,17 @@ /* generated HAL source file - do not edit */ #include "hal_data.h" -/* Macros to tie dynamic ELC links to ADC_TRIGGER_SYNC_ELC option in adc_trigger_t. */ -#define ADC_TRIGGER_ADC0 ADC_TRIGGER_SYNC_ELC -#define ADC_TRIGGER_ADC0_B ADC_TRIGGER_SYNC_ELC -#define ADC_TRIGGER_ADC1 ADC_TRIGGER_SYNC_ELC -#define ADC_TRIGGER_ADC1_B ADC_TRIGGER_SYNC_ELC -icu_instance_ctrl_t g_external_irq9_ctrl; -const external_irq_cfg_t g_external_irq9_cfg = -{ .channel = 9, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ9) - .irq = VECTOR_NUMBER_ICU_IRQ9, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq9 = -{ .p_ctrl = &g_external_irq9_ctrl, .p_cfg = &g_external_irq9_cfg, .p_api = &g_external_irq_on_icu }; -icu_instance_ctrl_t g_external_irq6_ctrl; -const external_irq_cfg_t g_external_irq6_cfg = -{ .channel = 6, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ6) - .irq = VECTOR_NUMBER_ICU_IRQ6, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq6 = -{ .p_ctrl = &g_external_irq6_ctrl, .p_cfg = &g_external_irq6_cfg, .p_api = &g_external_irq_on_icu }; -iic_master_instance_ctrl_t g_i2c_master1_ctrl; -const iic_master_extended_cfg_t g_i2c_master1_extend = -{ .timeout_mode = IIC_MASTER_TIMEOUT_MODE_SHORT, -/* Actual calculated bitrate: 99272. Actual calculated duty cycle: 49%. */ .clock_settings.brl_value = 27, - .clock_settings.brh_value = 26, .clock_settings.cks_value = 2, }; -const i2c_master_cfg_t g_i2c_master1_cfg = -{ .channel = 1, .rate = I2C_MASTER_RATE_STANDARD, .slave = 0x00, .addr_mode = I2C_MASTER_ADDR_MODE_7BIT, -#define RA_NOT_DEFINED (1) - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_tx = NULL, - #else - .p_transfer_tx = &RA_NOT_DEFINED, - #endif - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_rx = NULL, - #else - .p_transfer_rx = &RA_NOT_DEFINED, - #endif -#undef RA_NOT_DEFINED - .p_callback = callback_iic, - .p_context = NULL, - #if defined(VECTOR_NUMBER_IIC1_RXI) - .rxi_irq = VECTOR_NUMBER_IIC1_RXI, - #else - .rxi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_IIC1_TXI) - .txi_irq = VECTOR_NUMBER_IIC1_TXI, - #else - .txi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_IIC1_TEI) - .tei_irq = VECTOR_NUMBER_IIC1_TEI, - #else - .tei_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_IIC1_ERI) - .eri_irq = VECTOR_NUMBER_IIC1_ERI, - #else - .eri_irq = FSP_INVALID_VECTOR, - #endif - .ipl = (12), - .p_extend = &g_i2c_master1_extend, }; -/* Instance structure to use this module. */ -const i2c_master_instance_t g_i2c_master1 = -{ .p_ctrl = &g_i2c_master1_ctrl, .p_cfg = &g_i2c_master1_cfg, .p_api = &g_i2c_master_on_iic }; -adc_instance_ctrl_t g_adc0_ctrl; -const adc_extended_cfg_t g_adc0_cfg_extend = -{ .add_average_count = ADC_ADD_OFF, - .clearing = ADC_CLEAR_AFTER_READ_ON, - .trigger_group_b = ADC_TRIGGER_SYNC_ELC, - .double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED, - .adc_vref_control = ADC_VREF_CONTROL_VREFH, }; -const adc_cfg_t g_adc0_cfg = -{ .unit = 0, .mode = ADC_MODE_SINGLE_SCAN, .resolution = ADC_RESOLUTION_14_BIT, .alignment = - (adc_alignment_t)ADC_ALIGNMENT_RIGHT, - .trigger = ADC_TRIGGER_SOFTWARE, .p_callback = NULL, .p_context = NULL, .p_extend = &g_adc0_cfg_extend, - #if defined(VECTOR_NUMBER_ADC0_SCAN_END) - .scan_end_irq = VECTOR_NUMBER_ADC0_SCAN_END, - #else - .scan_end_irq = FSP_INVALID_VECTOR, - #endif - .scan_end_ipl = (BSP_IRQ_DISABLED), - #if defined(VECTOR_NUMBER_ADC0_SCAN_END_B) - .scan_end_b_irq = VECTOR_NUMBER_ADC0_SCAN_END_B, - #else - .scan_end_b_irq = FSP_INVALID_VECTOR, - #endif - .scan_end_b_ipl = (BSP_IRQ_DISABLED), }; -const adc_channel_cfg_t g_adc0_channel_cfg = -{ .scan_mask = 0, - .scan_mask_group_b = 0, - .priority_group_a = ADC_GROUP_A_PRIORITY_OFF, - .add_mask = 0, - .sample_hold_mask = 0, - .sample_hold_states = 24, }; -/* Instance structure to use this module. */ -const adc_instance_t g_adc0 = -{ .p_ctrl = &g_adc0_ctrl, .p_cfg = &g_adc0_cfg, .p_channel_cfg = &g_adc0_channel_cfg, .p_api = &g_adc_on_adc }; + lpm_instance_ctrl_t g_lpm0_ctrl; const lpm_cfg_t g_lpm0_cfg = -{ .low_power_mode = LPM_MODE_SLEEP, +{ .low_power_mode = LPM_MODE_SLEEP, .standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM + | (lpm_standby_wake_source_t)0, + #if BSP_FEATURE_LPM_HAS_SNOOZE .snooze_cancel_sources = LPM_SNOOZE_CANCEL_SOURCE_NONE, - .standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM | (lpm_standby_wake_source_t)0, .snooze_request_source = LPM_SNOOZE_REQUEST_RXD0_FALLING, .snooze_end_sources = (lpm_snooze_end_t)0, .dtc_state_in_snooze = LPM_SNOOZE_DTC_DISABLE, + #endif #if BSP_FEATURE_LPM_HAS_SBYCR_OPE .output_port_enable = 0, #endif @@ -140,171 +21,24 @@ const lpm_cfg_t g_lpm0_cfg = .deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0, .deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0, #endif - .p_extend = NULL, }; - -const lpm_instance_t g_lpm0 = -{ .p_api = &g_lpm_on_lpm, .p_ctrl = &g_lpm0_ctrl, .p_cfg = &g_lpm0_cfg }; -dtc_instance_ctrl_t g_transfer1_ctrl; - -transfer_info_t g_transfer1_info = -{ .dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, - .repeat_area = TRANSFER_REPEAT_AREA_DESTINATION, - .irq = TRANSFER_IRQ_END, - .chain_mode = TRANSFER_CHAIN_MODE_DISABLED, - .src_addr_mode = TRANSFER_ADDR_MODE_FIXED, - .size = TRANSFER_SIZE_2_BYTE, - .mode = TRANSFER_MODE_NORMAL, - .p_dest = (void *)NULL, - .p_src = (void const *)NULL, - .num_blocks = 0, - .length = 0, }; -const dtc_extended_cfg_t g_transfer1_cfg_extend = -{ .activation_source = VECTOR_NUMBER_SPI0_RXI, }; -const transfer_cfg_t g_transfer1_cfg = -{ .p_info = &g_transfer1_info, .p_extend = &g_transfer1_cfg_extend, }; - -/* Instance structure to use this module. */ -const transfer_instance_t g_transfer1 = -{ .p_ctrl = &g_transfer1_ctrl, .p_cfg = &g_transfer1_cfg, .p_api = &g_transfer_on_dtc }; -dtc_instance_ctrl_t g_transfer0_ctrl; - -transfer_info_t g_transfer0_info = -{ .dest_addr_mode = TRANSFER_ADDR_MODE_FIXED, - .repeat_area = TRANSFER_REPEAT_AREA_SOURCE, - .irq = TRANSFER_IRQ_END, - .chain_mode = TRANSFER_CHAIN_MODE_DISABLED, - .src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, - .size = TRANSFER_SIZE_2_BYTE, - .mode = TRANSFER_MODE_NORMAL, - .p_dest = (void *)NULL, - .p_src = (void const *)NULL, - .num_blocks = 0, - .length = 0, }; -const dtc_extended_cfg_t g_transfer0_cfg_extend = -{ .activation_source = VECTOR_NUMBER_SPI0_TXI, }; -const transfer_cfg_t g_transfer0_cfg = -{ .p_info = &g_transfer0_info, .p_extend = &g_transfer0_cfg_extend, }; - -/* Instance structure to use this module. */ -const transfer_instance_t g_transfer0 = -{ .p_ctrl = &g_transfer0_ctrl, .p_cfg = &g_transfer0_cfg, .p_api = &g_transfer_on_dtc }; -spi_instance_ctrl_t g_spi0_ctrl; - -/** SPI extended configuration for SPI HAL driver */ -const spi_extended_cfg_t g_spi0_ext_cfg = -{ .spi_clksyn = SPI_SSL_MODE_CLK_SYN, - .spi_comm = SPI_COMMUNICATION_FULL_DUPLEX, - .ssl_polarity = SPI_SSLP_LOW, - .ssl_select = SPI_SSL_SELECT_SSL0, - .mosi_idle = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE, - .parity = SPI_PARITY_MODE_DISABLE, - .byte_swap = SPI_BYTE_SWAP_DISABLE, - .spck_div = - { - /* Actual calculated bitrate: 12000000. */ .spbr = 1, - .brdv = 0 - }, - .spck_delay = SPI_DELAY_COUNT_1, - .ssl_negation_delay = SPI_DELAY_COUNT_1, - .next_access_delay = SPI_DELAY_COUNT_1 }; - -/** SPI configuration for SPI HAL driver */ -const spi_cfg_t g_spi0_cfg = -{ .channel = 0, - - #if defined(VECTOR_NUMBER_SPI0_RXI) - .rxi_irq = VECTOR_NUMBER_SPI0_RXI, - #else - .rxi_irq = FSP_INVALID_VECTOR, + #if BSP_FEATURE_LPM_HAS_PDRAMSCR + .ram_retention_cfg.ram_retention = (uint8_t)(0), + .ram_retention_cfg.tcm_retention = false, #endif - #if defined(VECTOR_NUMBER_SPI0_TXI) - .txi_irq = VECTOR_NUMBER_SPI0_TXI, - #else - .txi_irq = FSP_INVALID_VECTOR, + #if BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP + .ram_retention_cfg.standby_ram_retention = false, #endif - #if defined(VECTOR_NUMBER_SPI0_TEI) - .tei_irq = VECTOR_NUMBER_SPI0_TEI, - #else - .tei_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SPI0_ERI) - .eri_irq = VECTOR_NUMBER_SPI0_ERI, - #else - .eri_irq = FSP_INVALID_VECTOR, + #if BSP_FEATURE_LPM_HAS_LDO_CONTROL + .ldo_standby_cfg.pll1_ldo = false, + .ldo_standby_cfg.pll2_ldo = false, + .ldo_standby_cfg.hoco_ldo = false, #endif + .p_extend = NULL, }; - .rxi_ipl = (12), - .txi_ipl = (12), - .tei_ipl = (12), - .eri_ipl = (12), - - .operating_mode = SPI_MODE_MASTER, - - .clk_phase = SPI_CLK_PHASE_EDGE_ODD, - .clk_polarity = SPI_CLK_POLARITY_LOW, - - .mode_fault = SPI_MODE_FAULT_ERROR_DISABLE, - .bit_order = SPI_BIT_ORDER_MSB_FIRST, - .p_transfer_tx = g_spi0_P_TRANSFER_TX, - .p_transfer_rx = g_spi0_P_TRANSFER_RX, - .p_callback = spi_callback, +const lpm_instance_t g_lpm0 = +{ .p_api = &g_lpm_on_lpm, .p_ctrl = &g_lpm0_ctrl, .p_cfg = &g_lpm0_cfg }; - .p_context = NULL, - .p_extend = (void *)&g_spi0_ext_cfg, }; -/* Instance structure to use this module. */ -const spi_instance_t g_spi0 = -{ .p_ctrl = &g_spi0_ctrl, .p_cfg = &g_spi0_cfg, .p_api = &g_spi_on_spi }; -icu_instance_ctrl_t g_external_irq5_ctrl; -const external_irq_cfg_t g_external_irq5_cfg = -{ .channel = 5, - .trigger = EXTERNAL_IRQ_TRIG_RISING, - .filter_enable = false, - .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, - .p_callback = callback_icu, - .p_context = NULL, - .p_extend = NULL, - .ipl = (12), - #if defined(VECTOR_NUMBER_ICU_IRQ5) - .irq = VECTOR_NUMBER_ICU_IRQ5, - #else - .irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const external_irq_instance_t g_external_irq5 = -{ .p_ctrl = &g_external_irq5_ctrl, .p_cfg = &g_external_irq5_cfg, .p_api = &g_external_irq_on_icu }; -agt_instance_ctrl_t g_timer0_ctrl; -const agt_extended_cfg_t g_timer0_extend = -{ .count_source = AGT_CLOCK_PCLKB, - .agto = AGT_PIN_CFG_DISABLED, - .agtoa = AGT_PIN_CFG_DISABLED, - .agtob = AGT_PIN_CFG_DISABLED, - .measurement_mode = AGT_MEASURE_DISABLED, - .agtio_filter = AGT_AGTIO_FILTER_NONE, - .enable_pin = AGT_ENABLE_PIN_NOT_USED, - .trigger_edge = AGT_TRIGGER_EDGE_RISING, }; -const timer_cfg_t g_timer0_cfg = -{ .mode = TIMER_MODE_PERIODIC, -/* Actual period: 0.002730666666666667 seconds. Actual duty: 50%. */ .period_counts = 0x10000, - .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 0, .p_callback = callback_agt, - /** If NULL then do not add & */ - #if defined(NULL) - .p_context = NULL, - #else - .p_context = &NULL, - #endif - .p_extend = &g_timer0_extend, - .cycle_end_ipl = (5), - #if defined(VECTOR_NUMBER_AGT0_INT) - .cycle_end_irq = VECTOR_NUMBER_AGT0_INT, - #else - .cycle_end_irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const timer_instance_t g_timer0 = -{ .p_ctrl = &g_timer0_ctrl, .p_cfg = &g_timer0_cfg, .p_api = &g_timer_on_agt }; flash_lp_instance_ctrl_t g_flash0_ctrl; const flash_cfg_t g_flash0_cfg = { .data_flash_bgo = false, .p_callback = NULL, .p_context = NULL, .ipl = (BSP_IRQ_DISABLED), @@ -317,171 +51,3 @@ const flash_cfg_t g_flash0_cfg = /* Instance structure to use this module. */ const flash_instance_t g_flash0 = { .p_ctrl = &g_flash0_ctrl, .p_cfg = &g_flash0_cfg, .p_api = &g_flash_on_flash_lp }; -rtc_instance_ctrl_t g_rtc0_ctrl; -const rtc_error_adjustment_cfg_t g_rtc0_err_cfg = -{ .adjustment_mode = RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC, - .adjustment_period = RTC_ERROR_ADJUSTMENT_PERIOD_10_SECOND, - .adjustment_type = RTC_ERROR_ADJUSTMENT_NONE, - .adjustment_value = 0, }; -const rtc_cfg_t g_rtc0_cfg = -{ .clock_source = RTC_CLOCK_SOURCE_SUBCLK, .freq_compare_value_loco = 255, .p_err_cfg = &g_rtc0_err_cfg, .p_callback = - NULL, - .p_context = NULL, .alarm_ipl = (14), .periodic_ipl = (14), .carry_ipl = (14), - #if defined(VECTOR_NUMBER_RTC_ALARM) - .alarm_irq = VECTOR_NUMBER_RTC_ALARM, - #else - .alarm_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_RTC_PERIOD) - .periodic_irq = VECTOR_NUMBER_RTC_PERIOD, - #else - .periodic_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_RTC_CARRY) - .carry_irq = VECTOR_NUMBER_RTC_CARRY, - #else - .carry_irq = FSP_INVALID_VECTOR, - #endif -}; -/* Instance structure to use this module. */ -const rtc_instance_t g_rtc0 = -{ .p_ctrl = &g_rtc0_ctrl, .p_cfg = &g_rtc0_cfg, .p_api = &g_rtc_on_rtc }; -sci_uart_instance_ctrl_t g_uart1_ctrl; - -baud_setting_t g_uart1_baud_setting = -{ -/* Baud rate calculated with 0.160% error. */ .abcse = 0, - .abcs = 0, .bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t)256, .brme = false -}; - -/** UART extended configuration for UARTonSCI HAL driver */ -const sci_uart_extended_cfg_t g_uart1_cfg_extend = -{ .clock = SCI_UART_CLOCK_INT, - .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, - .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, - .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, - .p_baud_setting = &g_uart1_baud_setting, - .uart_mode = UART_MODE_RS232, - .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, - #if 0 - .flow_control_pin = BSP_IO_PORT_00_PIN_00, - #else - .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), - #endif -}; - -/** UART interface configuration */ -const uart_cfg_t g_uart1_cfg = -{ .channel = 1, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = - user_uart_callback, - .p_context = NULL, .p_extend = &g_uart1_cfg_extend, -#define RA_NOT_DEFINED (1) - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_tx = NULL, - #else - .p_transfer_tx = &RA_NOT_DEFINED, - #endif - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_rx = NULL, - #else - .p_transfer_rx = &RA_NOT_DEFINED, - #endif -#undef RA_NOT_DEFINED - .rxi_ipl = (12), - .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), - #if defined(VECTOR_NUMBER_SCI1_RXI) - .rxi_irq = VECTOR_NUMBER_SCI1_RXI, - #else - .rxi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI1_TXI) - .txi_irq = VECTOR_NUMBER_SCI1_TXI, - #else - .txi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI1_TEI) - .tei_irq = VECTOR_NUMBER_SCI1_TEI, - #else - .tei_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI1_ERI) - .eri_irq = VECTOR_NUMBER_SCI1_ERI, - #else - .eri_irq = FSP_INVALID_VECTOR, - #endif -}; - -/* Instance structure to use this module. */ -const uart_instance_t g_uart1 = -{ .p_ctrl = &g_uart1_ctrl, .p_cfg = &g_uart1_cfg, .p_api = &g_uart_on_sci }; -sci_uart_instance_ctrl_t g_uart0_ctrl; - -baud_setting_t g_uart0_baud_setting = -{ -/* Baud rate calculated with 0.160% error. */ .abcse = 0, - .abcs = 0, .bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t)256, .brme = false -}; - -/** UART extended configuration for UARTonSCI HAL driver */ -const sci_uart_extended_cfg_t g_uart0_cfg_extend = -{ .clock = SCI_UART_CLOCK_INT, - .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, - .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, - .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, - .p_baud_setting = &g_uart0_baud_setting, - .uart_mode = UART_MODE_RS232, - .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, - #if 0 - .flow_control_pin = BSP_IO_PORT_00_PIN_00, - #else - .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), - #endif -}; - -/** UART interface configuration */ -const uart_cfg_t g_uart0_cfg = -{ .channel = 0, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = - user_uart_callback, - .p_context = NULL, .p_extend = &g_uart0_cfg_extend, -#define RA_NOT_DEFINED (1) - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_tx = NULL, - #else - .p_transfer_tx = &RA_NOT_DEFINED, - #endif - #if (RA_NOT_DEFINED == RA_NOT_DEFINED) - .p_transfer_rx = NULL, - #else - .p_transfer_rx = &RA_NOT_DEFINED, - #endif -#undef RA_NOT_DEFINED - .rxi_ipl = (12), - .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), - #if defined(VECTOR_NUMBER_SCI0_RXI) - .rxi_irq = VECTOR_NUMBER_SCI0_RXI, - #else - .rxi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI0_TXI) - .txi_irq = VECTOR_NUMBER_SCI0_TXI, - #else - .txi_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI0_TEI) - .tei_irq = VECTOR_NUMBER_SCI0_TEI, - #else - .tei_irq = FSP_INVALID_VECTOR, - #endif - #if defined(VECTOR_NUMBER_SCI0_ERI) - .eri_irq = VECTOR_NUMBER_SCI0_ERI, - #else - .eri_irq = FSP_INVALID_VECTOR, - #endif -}; - -/* Instance structure to use this module. */ -const uart_instance_t g_uart0 = -{ .p_ctrl = &g_uart0_ctrl, .p_cfg = &g_uart0_cfg, .p_api = &g_uart_on_sci }; -void g_hal_init(void) { - g_common_init(); -} diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/hal_data.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/hal_data.h index 2c95755ee..41019e6dd 100644 --- a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/hal_data.h +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/hal_data.h @@ -2,131 +2,21 @@ #ifndef HAL_DATA_H_ #define HAL_DATA_H_ #include <stdint.h> -#include "bsp_api.h" #include "common_data.h" -#include "r_icu.h" -#include "r_external_irq_api.h" -#include "r_iic_master.h" -#include "r_i2c_master_api.h" -#include "r_adc.h" -#include "r_adc_api.h" #include "r_lpm.h" #include "r_lpm_api.h" -#include "r_dtc.h" -#include "r_transfer_api.h" -#include "r_spi.h" -#include "r_agt.h" -#include "r_timer_api.h" #include "r_flash_lp.h" #include "r_flash_api.h" -#include "r_rtc.h" -#include "r_rtc_api.h" -#include "r_sci_uart.h" -#include "r_uart_api.h" FSP_HEADER -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq9; -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq9_ctrl; -extern const external_irq_cfg_t g_external_irq9_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq6; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq6_ctrl; -extern const external_irq_cfg_t g_external_irq6_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/* I2C Master on IIC Instance. */ -extern const i2c_master_instance_t g_i2c_master1; - -/** Access the I2C Master instance using these structures when calling API functions directly (::p_api is not used). */ -extern iic_master_instance_ctrl_t g_i2c_master1_ctrl; -extern const i2c_master_cfg_t g_i2c_master1_cfg; - -#ifndef callback_iic -void callback_iic(i2c_master_callback_args_t *p_args); -#endif -/** ADC on ADC Instance. */ -extern const adc_instance_t g_adc0; - -/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */ -extern adc_instance_ctrl_t g_adc0_ctrl; -extern const adc_cfg_t g_adc0_cfg; -extern const adc_channel_cfg_t g_adc0_channel_cfg; - -#ifndef NULL -void NULL(adc_callback_args_t *p_args); -#endif /** lpm Instance */ extern const lpm_instance_t g_lpm0; /** Access the LPM instance using these structures when calling API functions directly (::p_api is not used). */ extern lpm_instance_ctrl_t g_lpm0_ctrl; extern const lpm_cfg_t g_lpm0_cfg; -/* Transfer on DTC Instance. */ -extern const transfer_instance_t g_transfer1; - -/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ -extern dtc_instance_ctrl_t g_transfer1_ctrl; -extern const transfer_cfg_t g_transfer1_cfg; -/* Transfer on DTC Instance. */ -extern const transfer_instance_t g_transfer0; - -/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ -extern dtc_instance_ctrl_t g_transfer0_ctrl; -extern const transfer_cfg_t g_transfer0_cfg; -/** SPI on SPI Instance. */ -extern const spi_instance_t g_spi0; - -/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */ -extern spi_instance_ctrl_t g_spi0_ctrl; -extern const spi_cfg_t g_spi0_cfg; -/** Callback used by SPI Instance. */ -#ifndef spi_callback -void spi_callback(spi_callback_args_t *p_args); -#endif -#define RA_NOT_DEFINED (1) -#if (RA_NOT_DEFINED == g_transfer0) - #define g_spi0_P_TRANSFER_TX (NULL) -#else -#define g_spi0_P_TRANSFER_TX (&g_transfer0) -#endif -#if (RA_NOT_DEFINED == g_transfer1) - #define g_spi0_P_TRANSFER_RX (NULL) -#else -#define g_spi0_P_TRANSFER_RX (&g_transfer1) -#endif -#undef RA_NOT_DEFINED -/** External IRQ on ICU Instance. */ -extern const external_irq_instance_t g_external_irq5; - -/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ -extern icu_instance_ctrl_t g_external_irq5_ctrl; -extern const external_irq_cfg_t g_external_irq5_cfg; - -#ifndef callback_icu -void callback_icu(external_irq_callback_args_t *p_args); -#endif -/** AGT Timer Instance */ -extern const timer_instance_t g_timer0; - -/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ -extern agt_instance_ctrl_t g_timer0_ctrl; -extern const timer_cfg_t g_timer0_cfg; - -#ifndef callback_agt -void callback_agt(timer_callback_args_t *p_args); -#endif /* Flash on Flash LP Instance. */ extern const flash_instance_t g_flash0; @@ -134,42 +24,6 @@ extern const flash_instance_t g_flash0; extern flash_lp_instance_ctrl_t g_flash0_ctrl; extern const flash_cfg_t g_flash0_cfg; -#ifndef NULL -void NULL(flash_callback_args_t *p_args); -#endif -/* RTC Instance. */ -extern const rtc_instance_t g_rtc0; - -/** Access the RTC instance using these structures when calling API functions directly (::p_api is not used). */ -extern rtc_instance_ctrl_t g_rtc0_ctrl; -extern const rtc_cfg_t g_rtc0_cfg; - -#ifndef NULL -void NULL(rtc_callback_args_t *p_args); -#endif -/** UART on SCI Instance. */ -extern const uart_instance_t g_uart1; - -/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ -extern sci_uart_instance_ctrl_t g_uart1_ctrl; -extern const uart_cfg_t g_uart1_cfg; -extern const sci_uart_extended_cfg_t g_uart1_cfg_extend; - -#ifndef user_uart_callback -void user_uart_callback(uart_callback_args_t *p_args); -#endif -/** UART on SCI Instance. */ -extern const uart_instance_t g_uart0; - -/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ -extern sci_uart_instance_ctrl_t g_uart0_ctrl; -extern const uart_cfg_t g_uart0_cfg; -extern const sci_uart_extended_cfg_t g_uart0_cfg_extend; - -#ifndef user_uart_callback -void user_uart_callback(uart_callback_args_t *p_args); -#endif void hal_entry(void); -void g_hal_init(void); FSP_FOOTER #endif /* HAL_DATA_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/pin_data.c b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/pin_data.c index 2479b76a0..a260afed8 100644 --- a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/pin_data.c +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/pin_data.c @@ -1,73 +1,76 @@ /* generated pin source file - do not edit */ #include "bsp_api.h" #include "r_ioport_api.h" -const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { - { - .pin = BSP_IO_PORT_01_PIN_00, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), - }, - { - .pin = BSP_IO_PORT_01_PIN_01, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), - }, - { - .pin = BSP_IO_PORT_01_PIN_02, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), - }, - { - .pin = BSP_IO_PORT_01_PIN_08, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), - }, - { - .pin = BSP_IO_PORT_01_PIN_09, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), - }, - { - .pin = BSP_IO_PORT_01_PIN_10, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), - }, - { - .pin = BSP_IO_PORT_03_PIN_00, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), - }, - { - .pin = BSP_IO_PORT_03_PIN_01, - .pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT), - }, - { - .pin = BSP_IO_PORT_03_PIN_02, - .pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT), - }, - { - .pin = BSP_IO_PORT_03_PIN_04, - .pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT), - }, - { - .pin = BSP_IO_PORT_04_PIN_01, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9), - }, - { - .pin = BSP_IO_PORT_04_PIN_02, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9), - }, - { - .pin = BSP_IO_PORT_04_PIN_08, - .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW), - }, - { - .pin = BSP_IO_PORT_04_PIN_09, - .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW), - }, - { - .pin = BSP_IO_PORT_04_PIN_10, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), - }, - { - .pin = BSP_IO_PORT_04_PIN_11, - .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), - }, -}; -const ioport_cfg_t g_bsp_pin_cfg = { - .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), - .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = +{ + { .pin = BSP_IO_PORT_01_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SPI) }, + { .pin = BSP_IO_PORT_01_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SPI) }, + { .pin = BSP_IO_PORT_01_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SPI) }, + { .pin = BSP_IO_PORT_01_PIN_08, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_DEBUG) }, + { .pin = BSP_IO_PORT_01_PIN_09, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_DEBUG) }, + { .pin = BSP_IO_PORT_01_PIN_10, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_DEBUG) }, + { .pin = BSP_IO_PORT_03_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_DEBUG) }, + { .pin = BSP_IO_PORT_03_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE + | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT) }, + { .pin = BSP_IO_PORT_03_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE + | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT) }, + { .pin = BSP_IO_PORT_03_PIN_04, .pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE + | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT) }, + { .pin = BSP_IO_PORT_04_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, + { .pin = BSP_IO_PORT_04_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, + { .pin = BSP_IO_PORT_04_PIN_08, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT + | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) }, + { .pin = BSP_IO_PORT_04_PIN_09, .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT + | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW) }, + { .pin = BSP_IO_PORT_04_PIN_10, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) }, + { .pin = BSP_IO_PORT_04_PIN_11, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) }, }; + +const ioport_cfg_t g_bsp_pin_cfg = +{ .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], }; + +#if BSP_TZ_SECURE_BUILD + +void R_BSP_PinCfgSecurityInit(void); + +/* Initialize SAR registers for secure pins. */ +void R_BSP_PinCfgSecurityInit(void) { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #else + uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #endif + memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0])); + + + for (uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++) + { + uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin; + uint32_t port = port_pin >> 8U; + uint32_t pin = port_pin & 0xFFU; + pmsar[port] &= (uint16_t) ~(1U << pin); + } + + for (uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + R_PMISC->PMSAR[i].PMSAR = (uint16_t)pmsar[i]; + #else + R_PMISC->PMSAR[i].PMSAR = pmsar[i]; + #endif + } + +} +#endif diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/vector_data.c b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/vector_data.c index ea2f3b066..44ae4d253 100644 --- a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/vector_data.c +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/vector_data.c @@ -12,21 +12,21 @@ BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BS [5] = sci_uart_txi_isr, /* SCI1 TXI (Transmit data empty) */ [6] = sci_uart_tei_isr, /* SCI1 TEI (Transmit end) */ [7] = sci_uart_eri_isr, /* SCI1 ERI (Receive error) */ - [8] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */ - [9] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */ - [10] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */ - [11] = agt_int_isr, /* AGT0 INT (AGT interrupt) */ - [12] = r_icu_isr, /* ICU IRQ5 (External pin interrupt 5) */ - [13] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */ - [14] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */ - [15] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */ - [16] = spi_eri_isr, /* SPI0 ERI (Error) */ - [17] = iic_master_rxi_isr, /* IIC1 RXI (Receive data full) */ - [18] = iic_master_txi_isr, /* IIC1 TXI (Transmit data empty) */ - [19] = iic_master_tei_isr, /* IIC1 TEI (Transmit end) */ - [20] = iic_master_eri_isr, /* IIC1 ERI (Transfer error) */ - [21] = r_icu_isr, /* ICU IRQ6 (External pin interrupt 6) */ - [22] = r_icu_isr, /* ICU IRQ9 (External pin interrupt 9) */ + [8] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */ + [9] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */ + [10] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */ + [11] = agt_int_isr, /* AGT0 INT (AGT interrupt) */ + [12] = r_icu_isr, /* ICU IRQ5 (External pin interrupt 5) */ + [13] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */ + [14] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */ + [15] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */ + [16] = spi_eri_isr, /* SPI0 ERI (Error) */ + [17] = iic_master_rxi_isr, /* IIC1 RXI (Receive data full) */ + [18] = iic_master_txi_isr, /* IIC1 TXI (Transmit data empty) */ + [19] = iic_master_tei_isr, /* IIC1 TEI (Transmit end) */ + [20] = iic_master_eri_isr, /* IIC1 ERI (Transfer error) */ + [21] = r_icu_isr, /* ICU IRQ6 (External pin interrupt 6) */ + [22] = r_icu_isr, /* ICU IRQ9 (External pin interrupt 9) */ }; const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = { @@ -38,20 +38,20 @@ const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENT [5] = BSP_PRV_IELS_ENUM(EVENT_SCI1_TXI), /* SCI1 TXI (Transmit data empty) */ [6] = BSP_PRV_IELS_ENUM(EVENT_SCI1_TEI), /* SCI1 TEI (Transmit end) */ [7] = BSP_PRV_IELS_ENUM(EVENT_SCI1_ERI), /* SCI1 ERI (Receive error) */ - [8] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */ - [9] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */ - [10] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */ - [11] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */ - [12] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ5), /* ICU IRQ5 (External pin interrupt 5) */ - [13] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */ - [14] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */ - [15] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */ - [16] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */ - [17] = BSP_PRV_IELS_ENUM(EVENT_IIC1_RXI), /* IIC1 RXI (Receive data full) */ - [18] = BSP_PRV_IELS_ENUM(EVENT_IIC1_TXI), /* IIC1 TXI (Transmit data empty) */ - [19] = BSP_PRV_IELS_ENUM(EVENT_IIC1_TEI), /* IIC1 TEI (Transmit end) */ - [20] = BSP_PRV_IELS_ENUM(EVENT_IIC1_ERI), /* IIC1 ERI (Transfer error) */ - [21] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ6), /* ICU IRQ6 (External pin interrupt 6) */ - [22] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ9), /* ICU IRQ9 (External pin interrupt 9) */ + [8] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */ + [9] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */ + [10] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */ + [11] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */ + [12] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ5), /* ICU IRQ5 (External pin interrupt 5) */ + [13] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */ + [14] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */ + [15] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */ + [16] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */ + [17] = BSP_PRV_IELS_ENUM(EVENT_IIC1_RXI), /* IIC1 RXI (Receive data full) */ + [18] = BSP_PRV_IELS_ENUM(EVENT_IIC1_TXI), /* IIC1 TXI (Transmit data empty) */ + [19] = BSP_PRV_IELS_ENUM(EVENT_IIC1_TEI), /* IIC1 TEI (Transmit end) */ + [20] = BSP_PRV_IELS_ENUM(EVENT_IIC1_ERI), /* IIC1 ERI (Transfer error) */ + [21] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ6), /* ICU IRQ6 (External pin interrupt 6) */ + [22] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ9), /* ICU IRQ9 (External pin interrupt 9) */ }; #endif diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/vector_data.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/vector_data.h index 5481e446c..7ff71ed14 100644 --- a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/vector_data.h +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/vector_data.h @@ -1,6 +1,9 @@ /* generated vector header file - do not edit */ #ifndef VECTOR_DATA_H #define VECTOR_DATA_H +#ifdef __cplusplus +extern "C" { +#endif /* Number of interrupts allocated */ #ifndef VECTOR_DATA_IRQ_COUNT #define VECTOR_DATA_IRQ_COUNT (23) @@ -25,63 +28,52 @@ void iic_master_eri_isr(void); /* Vector table allocations */ #define VECTOR_NUMBER_SCI0_RXI ((IRQn_Type)0) /* SCI0 RXI (Receive data full) */ +#define SCI0_RXI_IRQn ((IRQn_Type)0) /* SCI0 RXI (Receive data full) */ #define VECTOR_NUMBER_SCI0_TXI ((IRQn_Type)1) /* SCI0 TXI (Transmit data empty) */ +#define SCI0_TXI_IRQn ((IRQn_Type)1) /* SCI0 TXI (Transmit data empty) */ #define VECTOR_NUMBER_SCI0_TEI ((IRQn_Type)2) /* SCI0 TEI (Transmit end) */ +#define SCI0_TEI_IRQn ((IRQn_Type)2) /* SCI0 TEI (Transmit end) */ #define VECTOR_NUMBER_SCI0_ERI ((IRQn_Type)3) /* SCI0 ERI (Receive error) */ +#define SCI0_ERI_IRQn ((IRQn_Type)3) /* SCI0 ERI (Receive error) */ #define VECTOR_NUMBER_SCI1_RXI ((IRQn_Type)4) /* SCI1 RXI (Received data full) */ +#define SCI1_RXI_IRQn ((IRQn_Type)4) /* SCI1 RXI (Received data full) */ #define VECTOR_NUMBER_SCI1_TXI ((IRQn_Type)5) /* SCI1 TXI (Transmit data empty) */ +#define SCI1_TXI_IRQn ((IRQn_Type)5) /* SCI1 TXI (Transmit data empty) */ #define VECTOR_NUMBER_SCI1_TEI ((IRQn_Type)6) /* SCI1 TEI (Transmit end) */ +#define SCI1_TEI_IRQn ((IRQn_Type)6) /* SCI1 TEI (Transmit end) */ #define VECTOR_NUMBER_SCI1_ERI ((IRQn_Type)7) /* SCI1 ERI (Receive error) */ +#define SCI1_ERI_IRQn ((IRQn_Type)7) /* SCI1 ERI (Receive error) */ #define VECTOR_NUMBER_RTC_ALARM ((IRQn_Type)8) /* RTC ALARM (Alarm interrupt) */ +#define RTC_ALARM_IRQn ((IRQn_Type)8) /* RTC ALARM (Alarm interrupt) */ #define VECTOR_NUMBER_RTC_PERIOD ((IRQn_Type)9) /* RTC PERIOD (Periodic interrupt) */ +#define RTC_PERIOD_IRQn ((IRQn_Type)9) /* RTC PERIOD (Periodic interrupt) */ #define VECTOR_NUMBER_RTC_CARRY ((IRQn_Type)10) /* RTC CARRY (Carry interrupt) */ +#define RTC_CARRY_IRQn ((IRQn_Type)10) /* RTC CARRY (Carry interrupt) */ #define VECTOR_NUMBER_AGT0_INT ((IRQn_Type)11) /* AGT0 INT (AGT interrupt) */ +#define AGT0_INT_IRQn ((IRQn_Type)11) /* AGT0 INT (AGT interrupt) */ #define VECTOR_NUMBER_ICU_IRQ5 ((IRQn_Type)12) /* ICU IRQ5 (External pin interrupt 5) */ +#define ICU_IRQ5_IRQn ((IRQn_Type)12) /* ICU IRQ5 (External pin interrupt 5) */ #define VECTOR_NUMBER_SPI0_RXI ((IRQn_Type)13) /* SPI0 RXI (Receive buffer full) */ +#define SPI0_RXI_IRQn ((IRQn_Type)13) /* SPI0 RXI (Receive buffer full) */ #define VECTOR_NUMBER_SPI0_TXI ((IRQn_Type)14) /* SPI0 TXI (Transmit buffer empty) */ +#define SPI0_TXI_IRQn ((IRQn_Type)14) /* SPI0 TXI (Transmit buffer empty) */ #define VECTOR_NUMBER_SPI0_TEI ((IRQn_Type)15) /* SPI0 TEI (Transmission complete event) */ +#define SPI0_TEI_IRQn ((IRQn_Type)15) /* SPI0 TEI (Transmission complete event) */ #define VECTOR_NUMBER_SPI0_ERI ((IRQn_Type)16) /* SPI0 ERI (Error) */ +#define SPI0_ERI_IRQn ((IRQn_Type)16) /* SPI0 ERI (Error) */ #define VECTOR_NUMBER_IIC1_RXI ((IRQn_Type)17) /* IIC1 RXI (Receive data full) */ +#define IIC1_RXI_IRQn ((IRQn_Type)17) /* IIC1 RXI (Receive data full) */ #define VECTOR_NUMBER_IIC1_TXI ((IRQn_Type)18) /* IIC1 TXI (Transmit data empty) */ +#define IIC1_TXI_IRQn ((IRQn_Type)18) /* IIC1 TXI (Transmit data empty) */ #define VECTOR_NUMBER_IIC1_TEI ((IRQn_Type)19) /* IIC1 TEI (Transmit end) */ +#define IIC1_TEI_IRQn ((IRQn_Type)19) /* IIC1 TEI (Transmit end) */ #define VECTOR_NUMBER_IIC1_ERI ((IRQn_Type)20) /* IIC1 ERI (Transfer error) */ +#define IIC1_ERI_IRQn ((IRQn_Type)20) /* IIC1 ERI (Transfer error) */ #define VECTOR_NUMBER_ICU_IRQ6 ((IRQn_Type)21) /* ICU IRQ6 (External pin interrupt 6) */ +#define ICU_IRQ6_IRQn ((IRQn_Type)21) /* ICU IRQ6 (External pin interrupt 6) */ #define VECTOR_NUMBER_ICU_IRQ9 ((IRQn_Type)22) /* ICU IRQ9 (External pin interrupt 9) */ -typedef enum IRQn -{ - Reset_IRQn = -15, - NonMaskableInt_IRQn = -14, - HardFault_IRQn = -13, - MemoryManagement_IRQn = -12, - BusFault_IRQn = -11, - UsageFault_IRQn = -10, - SecureFault_IRQn = -9, - SVCall_IRQn = -5, - DebugMonitor_IRQn = -4, - PendSV_IRQn = -2, - SysTick_IRQn = -1, - SCI0_RXI_IRQn = 0, /* SCI0 RXI (Receive data full) */ - SCI0_TXI_IRQn = 1, /* SCI0 TXI (Transmit data empty) */ - SCI0_TEI_IRQn = 2, /* SCI0 TEI (Transmit end) */ - SCI0_ERI_IRQn = 3, /* SCI0 ERI (Receive error) */ - SCI1_RXI_IRQn = 4, /* SCI1 RXI (Received data full) */ - SCI1_TXI_IRQn = 5, /* SCI1 TXI (Transmit data empty) */ - SCI1_TEI_IRQn = 6, /* SCI1 TEI (Transmit end) */ - SCI1_ERI_IRQn = 7, /* SCI1 ERI (Receive error) */ - RTC_ALARM_IRQn = 8, /* RTC ALARM (Alarm interrupt) */ - RTC_PERIOD_IRQn = 9, /* RTC PERIOD (Periodic interrupt) */ - RTC_CARRY_IRQn = 10, /* RTC CARRY (Carry interrupt) */ - AGT0_INT_IRQn = 11, /* AGT0 INT (AGT interrupt) */ - ICU_IRQ5_IRQn = 12, /* ICU IRQ5 (External pin interrupt 5) */ - SPI0_RXI_IRQn = 13, /* SPI0 RXI (Receive buffer full) */ - SPI0_TXI_IRQn = 14, /* SPI0 TXI (Transmit buffer empty) */ - SPI0_TEI_IRQn = 15, /* SPI0 TEI (Transmission complete event) */ - SPI0_ERI_IRQn = 16, /* SPI0 ERI (Error) */ - IIC1_RXI_IRQn = 17, /* IIC1 RXI (Receive data full) */ - IIC1_TXI_IRQn = 18, /* IIC1 TXI (Transmit data empty) */ - IIC1_TEI_IRQn = 19, /* IIC1 TEI (Transmit end) */ - IIC1_ERI_IRQn = 20, /* IIC1 ERI (Transfer error) */ - ICU_IRQ6_IRQn = 21, /* ICU IRQ6 (External pin interrupt 6) */ - ICU_IRQ9_IRQn = 22, /* ICU IRQ9 (External pin interrupt 9) */ -} IRQn_Type; +#define ICU_IRQ9_IRQn ((IRQn_Type)22) /* ICU IRQ9 (External pin interrupt 9) */ +#ifdef __cplusplus +} +#endif #endif /* VECTOR_DATA_H */ diff --git a/ports/renesas-ra/ra/ra_timer.c b/ports/renesas-ra/ra/ra_timer.c index 5f2adcdfa..9c2a3c010 100644 --- a/ports/renesas-ra/ra/ra_timer.c +++ b/ports/renesas-ra/ra/ra_timer.c @@ -1,7 +1,7 @@ /* * The MIT License (MIT) * - * Copyright (c) 2021 Renesas Electronics Corporation + * Copyright (c) 2021-2023 Renesas Electronics Corporation * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -42,9 +42,9 @@ enum AGT_SOURCE { AGT_AGTSCLK }; -static R_AGT0_Type *agt_regs[AGT_CH_SIZE] = { - (R_AGT0_Type *)0x40084000, - (R_AGT0_Type *)0x40084100 +static R_AGTX0_AGT16_Type *agt_regs[AGT_CH_SIZE] = { + (R_AGTX0_AGT16_Type *)0x40084000, + (R_AGTX0_AGT16_Type *)0x40084100 }; static uint8_t ch_to_irq[AGT_CH_SIZE] = { @@ -77,15 +77,15 @@ static void ra_agt_timer_chk_callback(uint32_t ch) { } void ra_agt_timer_start(uint32_t ch) { - agt_regs[ch]->AGTCR_b.TSTART = 1; /* start counter */ + agt_regs[ch]->CTRL.AGTCR_b.TSTART = 1; /* start counter */ } void ra_agt_timer_stop(uint32_t ch) { - agt_regs[ch]->AGTCR_b.TSTART = 0; /* stop counter */ + agt_regs[ch]->CTRL.AGTCR_b.TSTART = 0; /* stop counter */ } void ra_agt_timer_set_freq(uint32_t ch, float freq) { - R_AGT0_Type *agt_reg = agt_regs[ch]; + R_AGTX0_AGT16_Type *agt_reg = agt_regs[ch]; uint8_t source = 0; uint16_t period = 0; uint8_t cks = 0; @@ -107,9 +107,9 @@ void ra_agt_timer_set_freq(uint32_t ch, float freq) { return; } ra_agt_freq[ch] = freq; - agt_reg->AGTCR_b.TSTART = 0; // stop counter - agt_reg->AGTMR2 = cks; - agt_reg->AGTMR1 = (uint8_t)(source << 4); // mode is timer mode + agt_reg->CTRL.AGTCR_b.TSTART = 0; // stop counter + agt_reg->CTRL.AGTMR2 = cks; + agt_reg->CTRL.AGTMR1 = (uint8_t)(source << 4); // mode is timer mode agt_reg->AGT = (uint16_t)period; } @@ -118,14 +118,14 @@ float ra_agt_timer_get_freq(uint32_t ch) { } void ra_agt_timer_init(uint32_t ch, float freq) { - R_AGT0_Type *agt_reg = agt_regs[ch]; + R_AGTX0_AGT16_Type *agt_reg = agt_regs[ch]; if (ch == 0) { ra_mstpcrd_start(R_MSTP_MSTPCRD_MSTPD3_Msk); } else { ra_mstpcrd_start(R_MSTP_MSTPCRD_MSTPD2_Msk); } ra_agt_timer_set_freq(ch, freq); - agt_reg->AGTCR_b.TUNDF = 1; // underflow interrupt + agt_reg->CTRL.AGTCR_b.TUNDF = 1; // underflow interrupt R_BSP_IrqCfgEnable((IRQn_Type const)ch_to_irq[ch], RA_PRI_TIM5, (void *)NULL); } diff --git a/ports/renesas-ra/ra/ra_utils.c b/ports/renesas-ra/ra/ra_utils.c index 94e30ded1..ae91427ee 100644 --- a/ports/renesas-ra/ra/ra_utils.c +++ b/ports/renesas-ra/ra/ra_utils.c @@ -27,7 +27,7 @@ #include "ra_utils.h" static R_SYSTEM_Type *system_reg = (R_SYSTEM_Type *)0x4001E000; -static R_MSTP_Type *mstp_reg = (R_MSTP_Type *)0x40047000; +static R_MSTP_Type *mstp_reg = (R_MSTP_Type *)R_MSTP; void ra_mstpcra_stop(uint32_t mod_mask) { system_reg->PRCR = 0xa502; diff --git a/ports/renesas-ra/ra/ra_utils.h b/ports/renesas-ra/ra/ra_utils.h index 4da30d06c..3ff0f3a37 100644 --- a/ports/renesas-ra/ra/ra_utils.h +++ b/ports/renesas-ra/ra/ra_utils.h @@ -1,7 +1,7 @@ /* * The MIT License (MIT) * - * Copyright (c) 2021 Renesas Electronics Corporation + * Copyright (c) 2021-2023 Renesas Electronics Corporation * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -53,4 +53,77 @@ void ra_mstpcrc_start(uint32_t mod_mask); void ra_mstpcrd_stop(uint32_t mod_mask); void ra_mstpcrd_start(uint32_t mod_mask); +/* mask bit definition for Module Stop Control Register B */ +#ifndef R_MSTP_MSTPCRB_MSTPB7_Msk +#define R_MSTP_MSTPCRB_MSTPB7_Msk (0x1UL << 7) +#endif +#ifndef R_MSTP_MSTPCRB_MSTPB8_Msk +#define R_MSTP_MSTPCRB_MSTPB8_Msk (0x1UL << 8) +#endif +#ifndef R_MSTP_MSTPCRB_MSTPB9_Msk +#define R_MSTP_MSTPCRB_MSTPB9_Msk (0x1UL << 9) +#endif +#ifndef R_MSTP_MSTPCRB_MSTPB18_Msk +#define R_MSTP_MSTPCRB_MSTPB18_Msk (0x1UL << 18) +#endif +#ifndef R_MSTP_MSTPCRB_MSTPB19_Msk +#define R_MSTP_MSTPCRB_MSTPB19_Msk (0x1UL << 19) +#endif +#ifndef R_MSTP_MSTPCRB_MSTPB22_Msk +#define R_MSTP_MSTPCRB_MSTPB22_Msk (0x1UL << 22) +#endif +#ifndef R_MSTP_MSTPCRB_MSTPB23_Msk +#define R_MSTP_MSTPCRB_MSTPB23_Msk (0x1UL << 23) +#endif +#ifndef R_MSTP_MSTPCRB_MSTPB24_Msk +#define R_MSTP_MSTPCRB_MSTPB24_Msk (0x1UL << 24) +#endif +#ifndef R_MSTP_MSTPCRB_MSTPB25_Msk +#define R_MSTP_MSTPCRB_MSTPB25_Msk (0x1UL << 25) +#endif +#ifndef R_MSTP_MSTPCRB_MSTPB26_Msk +#define R_MSTP_MSTPCRB_MSTPB26_Msk (0x1UL << 26) +#endif +#ifndef R_MSTP_MSTPCRB_MSTPB27_Msk +#define R_MSTP_MSTPCRB_MSTPB27_Msk (0x1UL << 27) +#endif +#ifndef R_MSTP_MSTPCRB_MSTPB28_Msk +#define R_MSTP_MSTPCRB_MSTPB28_Msk (0x1UL << 28) +#endif +#ifndef R_MSTP_MSTPCRB_MSTPB29_Msk +#define R_MSTP_MSTPCRB_MSTPB29_Msk (0x1UL << 29) +#endif +#ifndef R_MSTP_MSTPCRB_MSTPB30_Msk +#define R_MSTP_MSTPCRB_MSTPB30_Msk (0x1UL << 30) +#endif +#ifndef R_MSTP_MSTPCRB_MSTPB31_Msk +#define R_MSTP_MSTPCRB_MSTPB31_Msk (0x1UL << 31) +#endif + +/* mask bit definition for Module Stop Control Register D */ +#ifndef R_MSTP_MSTPCRD_MSTPD2_Msk +#define R_MSTP_MSTPCRD_MSTPD2_Msk (0x1UL << 2) +#endif +#ifndef R_MSTP_MSTPCRD_MSTPD3_Msk +#define R_MSTP_MSTPCRD_MSTPD3_Msk (0x1UL << 3) +#endif +#ifndef R_MSTP_MSTPCRD_MSTPD5_Msk +#define R_MSTP_MSTPCRD_MSTPD5_Msk (0x1UL << 5) +#endif +#ifndef R_MSTP_MSTPCRD_MSTPD6_Msk +#define R_MSTP_MSTPCRD_MSTPD6_Msk (0x1UL << 6) +#endif +#ifndef R_MSTP_MSTPCRD_MSTPD15_Msk +#define R_MSTP_MSTPCRD_MSTPD15_Msk (0x1UL << 15) +#endif +#ifndef R_MSTP_MSTPCRD_MSTPD16_Msk +#define R_MSTP_MSTPCRD_MSTPD16_Msk (0x1UL << 16) +#endif +#ifndef R_MSTP_MSTPCRD_MSTPD20_Msk +#define R_MSTP_MSTPCRD_MSTPD20_Msk (0x1UL << 20) +#endif +#ifndef R_MSTP_MSTPCRD_MSTPD22_Msk +#define R_MSTP_MSTPCRD_MSTPD22_Msk (0x1UL << 22) +#endif + #endif /* RA_RA_UTILS_H_ */ |