diff options
| -rw-r--r-- | ports/esp32/Makefile | 15 | ||||
| -rw-r--r-- | ports/esp32/esp32.custom_common.ld | 37 |
2 files changed, 44 insertions, 8 deletions
diff --git a/ports/esp32/Makefile b/ports/esp32/Makefile index bb766dafc..b0baa0dca 100644 --- a/ports/esp32/Makefile +++ b/ports/esp32/Makefile @@ -21,7 +21,7 @@ FLASH_FREQ ?= 40m FLASH_SIZE ?= 4MB CROSS_COMPILE ?= xtensa-esp32-elf- -ESPIDF_SUPHASH := 1f7b41e206646417adc572da928175d33c986bd3 +ESPIDF_SUPHASH := 9a55b42f0841b3d38a61089b1dda4bf28135decd # paths to ESP IDF and its components ifeq ($(ESPIDF),) @@ -93,6 +93,7 @@ INC_ESPCOMP += -I$(ESPCOMP)/ethernet/include INC_ESPCOMP += -I$(ESPCOMP)/app_trace/include INC_ESPCOMP += -I$(ESPCOMP)/app_update/include INC_ESPCOMP += -I$(ESPCOMP)/pthread/include +INC_ESPCOMP += -I$(ESPCOMP)/smartconfig_ack/include # these flags are common to C and C++ compilation CFLAGS_COMMON = -Os -ffunction-sections -fdata-sections -fstrict-volatile-bitfields \ @@ -271,7 +272,7 @@ ESPIDF_ESP32_O = $(addprefix $(ESPCOMP)/esp32/,\ intr_alloc.o \ dport_access.o \ wifi_init.o \ - wifi_internal.o \ + wifi_os_adapter.o \ sleep_modes.o \ spiram.o \ spiram_psram.o \ @@ -291,6 +292,7 @@ ESPIDF_SOC_O = $(addprefix $(ESPCOMP)/soc/,\ esp32/rtc_sleep.o \ esp32/rtc_time.o \ esp32/soc_memory_layout.o \ + esp32/spi_periph.o \ ) ESPIDF_CXX_O = $(addprefix $(ESPCOMP)/cxx/,\ @@ -331,7 +333,7 @@ $(BUILD)/$(ESPCOMP)/freertos/portasm.o: CFLAGS = $(CFLAGS_ASM) $(BUILD)/$(ESPCOMP)/freertos/xtensa_context.o: CFLAGS = $(CFLAGS_ASM) $(BUILD)/$(ESPCOMP)/freertos/xtensa_intr_asm.o: CFLAGS = $(CFLAGS_ASM) $(BUILD)/$(ESPCOMP)/freertos/xtensa_vectors.o: CFLAGS = $(CFLAGS_ASM) -$(BUILD)/$(ESPCOMP)/freertos/%.o: CFLAGS = $(CFLAGS_BASE) -I. $(INC_ESPCOMP) -I$(ESPCOMP)/freertos/include/freertos +$(BUILD)/$(ESPCOMP)/freertos/%.o: CFLAGS = $(CFLAGS_BASE) -I. $(INC_ESPCOMP) -I$(ESPCOMP)/freertos/include/freertos -D_ESP_FREERTOS_INTERNAL ESPIDF_FREERTOS_O = $(addprefix $(ESPCOMP)/freertos/,\ croutine.o \ event_groups.o \ @@ -429,6 +431,10 @@ ESPIDF_NVS_FLASH_O = $(addprefix $(ESPCOMP)/nvs_flash/,\ ESPIDF_OPENSSL_O = $(addprefix $(ESPCOMP)/openssl/,\ ) +ESPIDF_SMARTCONFIG_ACK_O = $(addprefix $(ESPCOMP)/smartconfig_ack/,\ + smartconfig_ack.o \ + ) + ESPIDF_SPI_FLASH_O = $(addprefix $(ESPCOMP)/spi_flash/,\ flash_mmap.o \ partition.o \ @@ -629,6 +635,7 @@ OBJ_ESPIDF += $(addprefix $(BUILD)/, $(ESPIDF_APP_UPDATE_O)) OBJ_ESPIDF += $(addprefix $(BUILD)/, $(ESPIDF_NGHTTP_O)) OBJ_ESPIDF += $(addprefix $(BUILD)/, $(ESPIDF_NVS_FLASH_O)) OBJ_ESPIDF += $(addprefix $(BUILD)/, $(ESPIDF_OPENSSL_O)) +OBJ_ESPIDF += $(addprefix $(BUILD)/, $(ESPIDF_SMARTCONFIG_ACK_O)) OBJ_ESPIDF += $(addprefix $(BUILD)/, $(ESPIDF_SPI_FLASH_O)) OBJ_ESPIDF += $(addprefix $(BUILD)/, $(ESPIDF_ULP_O)) OBJ_ESPIDF += $(addprefix $(BUILD)/, $(ESPIDF_WPA_SUPPLICANT_O)) @@ -666,7 +673,7 @@ APP_LD_ARGS += -L$(dir $(LIBGCC_FILE_NAME)) -lgcc APP_LD_ARGS += -L$(dir $(LIBSTDCXX_FILE_NAME)) -lstdc++ APP_LD_ARGS += $(LIBC_LIBM) APP_LD_ARGS += $(ESPCOMP)/esp32/libhal.a -APP_LD_ARGS += -L$(ESPCOMP)/esp32/lib -lcore -lnet80211 -lphy -lrtc -lpp -lwpa -lsmartconfig -lcoexist -lwps -lwpa2 +APP_LD_ARGS += -L$(ESPCOMP)/esp32/lib -lcore -lmesh -lnet80211 -lphy -lrtc -lpp -lwpa -lsmartconfig -lcoexist -lwps -lwpa2 APP_LD_ARGS += $(OBJ) APP_LD_ARGS += --end-group diff --git a/ports/esp32/esp32.custom_common.ld b/ports/esp32/esp32.custom_common.ld index f49ff9b20..716e9ac1d 100644 --- a/ports/esp32/esp32.custom_common.ld +++ b/ports/esp32/esp32.custom_common.ld @@ -11,7 +11,7 @@ SECTIONS . = ALIGN(4); *(.rtc.literal .rtc.text) *rtc_wake_stub*.o(.literal .text .literal.* .text.*) - } >rtc_iram_seg + } > rtc_iram_seg /* RTC slow memory holds RTC wake stub data/rodata, including from any source file @@ -35,6 +35,20 @@ SECTIONS _rtc_bss_end = ABSOLUTE(.); } > rtc_slow_seg + /* This section holds data that should not be initialized at power up + and will be retained during deep sleep. The section located in + RTC SLOW Memory area. User data marked with RTC_NOINIT_ATTR will be placed + into this section. See the file "esp_attr.h" for more information. + */ + .rtc_noinit (NOLOAD): + { + . = ALIGN(4); + _rtc_noinit_start = ABSOLUTE(.); + *(.rtc_noinit .rtc_noinit.*) + . = ALIGN(4) ; + _rtc_noinit_end = ABSOLUTE(.); + } > rtc_slow_seg + /* Send .iram0 code to iram */ .iram0.vectors : { @@ -99,7 +113,7 @@ SECTIONS *py/scheduler.o*(.literal .text .literal.* .text.*) _iram_text_end = ABSOLUTE(.); } > iram0_0_seg - + .dram0.data : { _data_start = ABSOLUTE(.); @@ -125,7 +139,21 @@ SECTIONS INCLUDE esp32.spiram.rom-functions-dram.ld _data_end = ABSOLUTE(.); . = ALIGN(4); - } >dram0_0_seg + } > dram0_0_seg + + /*This section holds data that should not be initialized at power up. + The section located in Internal SRAM memory region. The macro _NOINIT + can be used as attribute to place data into this section. + See the esp_attr.h file for more information. + */ + .noinit (NOLOAD): + { + . = ALIGN(4); + _noinit_start = ABSOLUTE(.); + *(.noinit .noinit.*) + . = ALIGN(4) ; + _noinit_end = ABSOLUTE(.); + } > dram0_0_seg /* Shared RAM */ .dram0.bss (NOLOAD) : @@ -148,8 +176,9 @@ SECTIONS *(COMMON) . = ALIGN (8); _bss_end = ABSOLUTE(.); + /* The heap starts right after end of this section */ _heap_start = ABSOLUTE(.); - } >dram0_0_seg + } > dram0_0_seg .flash.rodata : { |