diff options
46 files changed, 1662 insertions, 438 deletions
diff --git a/ports/mimxrt/Makefile b/ports/mimxrt/Makefile index 3a001182a..0c893f963 100644 --- a/ports/mimxrt/Makefile +++ b/ports/mimxrt/Makefile @@ -23,6 +23,16 @@ GIT_SUBMODULES = lib/tinyusb lib/nxp_driver MCU_DIR = lib/nxp_driver/sdk/devices/$(MCU_SERIES) LD_FILES = boards/$(MCU_SERIES).ld $(TOP)/$(MCU_DIR)/gcc/$(MCU_SERIES)xxxxx_flexspi_nor.ld +MAKE_PINS = boards/make-pins.py +BOARD_PINS = $(BOARD_DIR)/pins.csv +AF_FILE = boards/$(MCU_SERIES)_af.csv +PREFIX_FILE = boards/mimxrt_prefix.c +GEN_PINS_SRC = $(BUILD)/pins_gen.c +GEN_PINS_HDR = $(HEADER_BUILD)/pins.h +GEN_PINS_QSTR = $(BUILD)/pins_qstr.h +GEN_PINS_AF_CONST = $(HEADER_BUILD)/pins_af_const.h +GEN_PINS_AF_PY = $(BUILD)/pins_af.py + # mcu driver cause following warnings #CFLAGS += -Wno-error=float-equal -Wno-error=nested-externs CFLAGS += -Wno-error=unused-parameter @@ -49,12 +59,14 @@ CFLAGS += -DXIP_EXTERNAL_FLASH=1 \ -D__START=main \ -DCPU_HEADER_H='<$(MCU_SERIES).h>' -LDFLAGS = $(addprefix -T,$(LD_FILES)) -Map=$@.map --cref +LDFLAGS = $(addprefix -T,$(LD_FILES)) -Map=$@.map --cref --print-memory-usage LIBS = $(shell $(CC) $(CFLAGS) -print-libgcc-file-name) # Tune for Debugging or Optimization ifeq ($(DEBUG),1) CFLAGS += -O0 -ggdb +LDFLAGS += --gc-sections +CFLAGS += -fdata-sections -ffunction-sections else CFLAGS += -Os -DNDEBUG LDFLAGS += --gc-sections @@ -95,8 +107,8 @@ SRC_C = \ tusb_port.c \ board_init.c \ $(BOARD_DIR)/flash_config.c \ - $(BOARD_DIR)/pins.c \ machine_led.c \ + machine_pin.c \ modutime.c \ modmachine.c \ mphalport.c \ @@ -116,15 +128,17 @@ SRC_S = lib/utils/gchelper_m3.s \ # List of sources for qstr extraction SRC_QSTR += \ machine_led.c \ + machine_pin.c \ modutime.c \ modmachine.c \ pin.c \ - $(BOARD_DIR)/pins.c \ + $(GEN_PINS_SRC) \ OBJ += $(PY_O) OBJ += $(addprefix $(BUILD)/, $(SRC_C:.c=.o)) OBJ += $(addprefix $(BUILD)/, $(SRC_S:.s=.o)) OBJ += $(addprefix $(BUILD)/, $(SRC_SS:.S=.o)) +OBJ += $(BUILD)/pins_gen.o # Workaround for bug in older gcc, warning on "static usbd_device_t _usbd_dev = { 0 };" $(BUILD)/lib/tinyusb/src/device/usbd.o: CFLAGS += -Wno-missing-braces @@ -142,4 +156,25 @@ $(BUILD)/firmware.bin: $(BUILD)/firmware.elf $(BUILD)/firmware.hex: $(BUILD)/firmware.elf $(Q)$(OBJCOPY) -O ihex -R .eeprom $< $@ +# Making OBJ use an order-only depenedency on the generated pins.h file +# has the side effect of making the pins.h file before we actually compile +# any of the objects. The normal dependency generation will deal with the +# case when pins.h is modified. But when it doesn't exist, we don't know +# which source files might need it. +$(OBJ): | $(GEN_PINS_HDR) + +# With conditional pins, we may need to regenerate qstrdefs.h when config +# options change. +$(HEADER_BUILD)/qstrdefs.generated.h: $(BOARD_DIR)/mpconfigboard.h + +# Use a pattern rule here so that make will only call make-pins.py once to make +# both pins_gen.c and pins.h +$(BUILD)/%_gen.c $(HEADER_BUILD)/%.h: $(BOARD_PINS) $(MAKE_PINS) $(AF_FILE) $(PREFIX_FILE) | $(HEADER_BUILD) + $(ECHO) "Create $@" + $(Q)$(PYTHON) $(MAKE_PINS) --board $(BOARD_PINS) --af $(AF_FILE)\ + --prefix $(PREFIX_FILE) --hdr $(GEN_PINS_HDR) > $(GEN_PINS_SRC) + +$(BUILD)/pins_gen.o: $(BUILD)/pins_gen.c + $(call compile_c) + include $(TOP)/py/mkrules.mk diff --git a/ports/mimxrt/README.md b/ports/mimxrt/README.md index a2b5cf79a..c24939f47 100644 --- a/ports/mimxrt/README.md +++ b/ports/mimxrt/README.md @@ -5,10 +5,13 @@ Currently supports Teensy 4.0 and the i.MX RT1010 EVK board. Features: - REPL over USB VCP + - machine.Pin Known issues: - pyboard.py doesn't work with files larger than 64 bytes + - machine.Pin class currently does not support GPIOMUX option of + i.MX RT101x variants TODO: - Enable TCM - - Peripherals (pins, LED, Timers, etc) + - Peripherals (LED, Timers, etc) diff --git a/ports/mimxrt/board_init.c b/ports/mimxrt/board_init.c index 9095c8804..0336cdf68 100644 --- a/ports/mimxrt/board_init.c +++ b/ports/mimxrt/board_init.c @@ -39,8 +39,6 @@ #include "clock_config.h" -#define LED_STATE_ON (0) - volatile uint32_t systick_ms = 0; const uint8_t dcd_data[] = { 0x00 }; diff --git a/ports/mimxrt/boards/MIMXRT1010_EVK/mpconfigboard.h b/ports/mimxrt/boards/MIMXRT1010_EVK/mpconfigboard.h index eeddd0e02..5a89423b5 100644 --- a/ports/mimxrt/boards/MIMXRT1010_EVK/mpconfigboard.h +++ b/ports/mimxrt/boards/MIMXRT1010_EVK/mpconfigboard.h @@ -4,6 +4,6 @@ #define BOARD_FLASH_SIZE (16 * 1024 * 1024) // i.MX RT1010 EVK has 1 board LED -#define MICROPY_HW_LED1_PIN (GPIO_11) +#define MICROPY_HW_LED1_PIN (pin_GPIO_11) #define MICROPY_HW_LED_ON(pin) (mp_hal_pin_high(pin)) #define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_low(pin)) diff --git a/ports/mimxrt/boards/MIMXRT1010_EVK/mpconfigboard.mk b/ports/mimxrt/boards/MIMXRT1010_EVK/mpconfigboard.mk index e17854584..c5b505532 100644 --- a/ports/mimxrt/boards/MIMXRT1010_EVK/mpconfigboard.mk +++ b/ports/mimxrt/boards/MIMXRT1010_EVK/mpconfigboard.mk @@ -2,6 +2,25 @@ MCU_SERIES = MIMXRT1011 MCU_VARIANT = MIMXRT1011DAE5A JLINK_PATH = /media/RT1010-EVK/ +JLINK_COMMANDER_SCRIPT = $(BUILD)/script.jlink + + +ifdef JLINK_IP +JLINK_CONNECTION_SETTINGS = -IP $(JLINK_IP) +else +JLINK_CONNECTION_SETTINGS = -USB +endif + + +deploy_jlink: $(BUILD)/firmware.hex + $(Q)$(TOUCH) $(JLINK_COMMANDER_SCRIPT) + $(ECHO) "ExitOnError 1" > $(JLINK_COMMANDER_SCRIPT) + $(ECHO) "speed auto" >> $(JLINK_COMMANDER_SCRIPT) + $(ECHO) "r" >> $(JLINK_COMMANDER_SCRIPT) + $(ECHO) "st" >> $(JLINK_COMMANDER_SCRIPT) + $(ECHO) "loadfile \"$(realpath $(BUILD)/firmware.hex)\"" >> $(JLINK_COMMANDER_SCRIPT) + $(ECHO) "qc" >> $(JLINK_COMMANDER_SCRIPT) + $(JLINK_PATH)JLinkExe -device $(MCU_VARIANT) -if SWD $(JLINK_CONNECTION_SETTINGS) -CommanderScript $(JLINK_COMMANDER_SCRIPT) deploy: $(BUILD)/firmware.bin cp $< $(JLINK_PATH) diff --git a/ports/mimxrt/boards/MIMXRT1010_EVK/pins.c b/ports/mimxrt/boards/MIMXRT1010_EVK/pins.c deleted file mode 100644 index e0397e09e..000000000 --- a/ports/mimxrt/boards/MIMXRT1010_EVK/pins.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the MicroPython project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2020 Philipp Ebensberger - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "pin.h" - -static pin_af_obj_t GPIO_11_af[] = { - PIN_AF(GPIOMUX_IO11, PIN_AF_MODE_ALT5, GPIO1, 0x10B0U), -}; - -pin_obj_t GPIO_11 = PIN(GPIO_11, GPIO1, 5, GPIO_11_af); diff --git a/ports/mimxrt/boards/MIMXRT1010_EVK/pins.csv b/ports/mimxrt/boards/MIMXRT1010_EVK/pins.csv new file mode 100644 index 000000000..f7fdf3964 --- /dev/null +++ b/ports/mimxrt/boards/MIMXRT1010_EVK/pins.csv @@ -0,0 +1,57 @@ +D0,GPIO_09 +D1,GPIO_10 +D2,GPIO_AD_05 +D3,GPIO_AD_06 +D4,GPIO_08 +D5,GPIO_01 +D6,GPIO_AD_01 +D7,GPIO_AD_02 +D8,GPIO_SD_02 +D9,GPIO_03 +D10,GPIO_AD_05 +D11,GPIO_AD_04 +D12,GPIO_AD_03 +D13,GPIO_AD_06 +D14,GPIO_01 +D15,GPIO_02 +CUR_A,GPIO_AD_01 +CUR_B,GPIO_AD_02 +CUR_C,GPIO_AD_07 +VOLT_DCB,GPIO_AD_09 +CUR_DCB,GPIO_AD_10 +A0,GPIO_AD_07 +A1,GPIO_AD_09 +A2,GPIO_AD_10 +A3,GPIO_AD_14 +A4,GPIO_AD_01 +A5,GPIO_AD_02 +PWM_AT,GPIO_02 +PWM_AB,GPIO_01 +PWM_BT,GPIO_04 +PWM_BB,GPIO_03 +PWM_CT,GPIO_06 +PWM_CB,GPIO_05 +ENC_A,GPIO_AD_05 +ENC_B,GPIO_AD_06 +LED_GREEN,GPIO_11 +GPIO_01,GPIO_01 +GPIO_02,GPIO_02 +GPIO_03,GPIO_03 +GPIO_04,GPIO_04 +GPIO_05,GPIO_05 +GPIO_06,GPIO_06 +GPIO_08,GPIO_08 +GPIO_09,GPIO_09 +GPIO_10,GPIO_10 +GPIO_11,GPIO_11 +GPIO_AD_01,GPIO_AD_01 +GPIO_AD_02,GPIO_AD_02 +GPIO_AD_03,GPIO_AD_03 +GPIO_AD_04,GPIO_AD_04 +GPIO_AD_05,GPIO_AD_05 +GPIO_AD_06,GPIO_AD_06 +GPIO_AD_07,GPIO_AD_07 +GPIO_AD_09,GPIO_AD_09 +GPIO_AD_10,GPIO_AD_10 +GPIO_AD_14,GPIO_AD_14 +GPIO_SD_02,GPIO_SD_02 diff --git a/ports/mimxrt/boards/MIMXRT1010_EVK/pins.h b/ports/mimxrt/boards/MIMXRT1010_EVK/pins.h deleted file mode 100644 index 99534932a..000000000 --- a/ports/mimxrt/boards/MIMXRT1010_EVK/pins.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the MicroPython project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2020 Philipp Ebensberger - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -// NOTE: pins.h shall only be included in in pin.h -// hence no include guards are needed since they will be provided by pin.h - -extern pin_obj_t GPIO_11; diff --git a/ports/mimxrt/boards/MIMXRT1011.ld b/ports/mimxrt/boards/MIMXRT1011.ld index 0512c48a7..9db30adee 100644 --- a/ports/mimxrt/boards/MIMXRT1011.ld +++ b/ports/mimxrt/boards/MIMXRT1011.ld @@ -1,5 +1,5 @@ /* 24kiB stack. */ -__stack_size__ = 0x6000; +__stack_size__ = 0x4000; _estack = __StackTop; _sstack = __StackLimit; diff --git a/ports/mimxrt/boards/MIMXRT1011_af.csv b/ports/mimxrt/boards/MIMXRT1011_af.csv new file mode 100644 index 000000000..11dd08546 --- /dev/null +++ b/ports/mimxrt/boards/MIMXRT1011_af.csv @@ -0,0 +1,44 @@ +Pad,ALT0, ALT1, ALT2, ALT3, ALT4, ALT5, ALT6, ALT7, ALT8, ALT9,ADC,ACMP,Default +GPIO_00,FLEXSPI_B_DQS,SAI3_MCLK,LPSPI2_PCS3,LPSPI1_PCS3,PIT_TRIGGER0,GPIO1_IO00,,,,,,,ALT5 +GPIO_01,SAI1_RX_BCLK,WDOG1_ANY,FLEXPWM1_PWM0_B,LPI2C1_SDA,KPP_ROW3,GPIO1_IO01,,,,,,,ALT5 +GPIO_02,SAI1_RX_SYNC,WDOG2_B,FLEXPWM1_PWM0_A,LPI2C1_SCL,KPP_COL3,GPIO1_IO02,,,,,,,ALT5 +GPIO_03,SAI1_RX_DATA0,GPT1_COMPARE3,FLEXPWM1_PWM1_B,,SPDIF_SR_CLK,GPIO1_IO03,,,,,,,ALT5 +GPIO_04,SAI1_TX_DATA0,GPT1_CAPTURE2,FLEXPWM1_PWM1_A,,SPDIF_IN,GPIO1_IO04,,,,,,,ALT5 +GPIO_05,SAI1_TX_DATA1,GPT1_COMPARE2,FLEXPWM1_PWM2_B,LPUART4_RXD,SPDIF_OUT,GPIO1_IO05,,,,,,,ALT0 +GPIO_06,SAI1_TX_BCLK,GPT1_CAPTURE1,FLEXPWM1_PWM2_A,LPUART4_TXD,SPDIF_EXT_CLK,GPIO1_IO06,,,,,,,ALT5 +GPIO_07,SAI1_TX_SYNC,GPT1_COMPARE1,FLEXPWM1_PWM3_B,LPUART3_RXD,SPDIF_LOCK,GPIO1_IO07,LPUART1_RTS_B,,,,,,ALT5 +GPIO_08,SAI1_MCLK,GPT1_CLK,FLEXPWM1_PWM3_A,LPUART3_TXD,FLEXIO1_IO00,GPIO1_IO08,LPUART1_CTS_B,,,,,,ALT5 +GPIO_09,LPUART1_RXD,WDOG1_B,FLEXSPI_A_SS1_B,LPI2C2_SDA,FLEXIO1_IO01,GPIO1_IO09,SPDIF_SR_CLK,,,,,,ALT5 +GPIO_10,LPUART1_TXD,LPI2C1_HREQ,EWM_OUT_B,LPI2C2_SCL,FLEXIO1_IO02,GPIO1_IO10,SPDIF_IN,,,,,,ALT5 +GPIO_11,LPUART3_RXD,LPI2C1_SDA,KPP_ROW0,FLEXSPI_B_SS1_B,FLEXIO1_IO03,GPIO1_IO11,SPDIF_OUT,ARM_TRACE3,,,,,ALT5 +GPIO_12,LPUART3_TXD,LPI2C1_SCL,KPP_COL0,USB_OTG1_OC,FLEXIO1_IO04,GPIO1_IO12,SPDIF_EXT_CLK,ARM_TRACE2,,,,,ALT5 +GPIO_13,LPUART2_RXD,LPSPI2_PCS2,KPP_ROW3,USB_OTG1_ID,FLEXIO1_IO05,GPIO1_IO13,SPDIF_LOCK,ARM_TRACE1,,,,,ALT5 +GPIO_AD_00,LPUART2_TXD,LPSPI1_PCS2,KPP_COL3,USB_OTG1_PWR,FLEXIO1_IO20,GPIO1_IO14,ARM_NMI,ARM_TRACE0,,,ADC1_IN0,,ALT5 +GPIO_AD_01,LPUART4_RXD,LPSPI2_PCS1,WDOG1_ANY,LPI2C2_SDA,MQS_LEFT,GPIO1_IO15,USB_OTG1_OC,ARM_TRACE_SWO,,,ADC1_IN1,,ALT5 +GPIO_AD_02,LPUART4_TXD,LPSPI1_PCS1,WDOG2_B,LPI2C2_SCL,MQS_RIGHT,GPIO1_IO16,,ARM_TRACE_CLK,,,ADC1_IN2,,ALT5 +GPIO_AD_03,LPSPI1_SDI,PIT_TRIGGER3,FLEXPWM1_PWM2_B,KPP_ROW2,GPT2_CLK,GPIO1_IO17,SNVS_VIO_5_B,JTAG_DE_B,,,ADC1_IN3,,ALT5 +GPIO_AD_04,LPSPI1_SDO,PIT_TRIGGER2,FLEXPWM1_PWM2_A,KPP_COL2,GPT2_COMPARE1,GPIO1_IO18,SNVS_VIO_5_CTL,,,,ADC1_IN4,,ALT5 +GPIO_AD_05,LPSPI1_PCS0,PIT_TRIGGER1,FLEXPWM1_PWM3_B,KPP_ROW1,GPT2_CAPTURE1,GPIO1_IO19,,,,,ADC1_IN5,,ALT5 +GPIO_AD_06,LPSPI1_SCK,PIT_TRIGGER0,FLEXPWM1_PWM3_A,KPP_COL1,GPT2_COMPARE2,GPIO1_IO20,LPI2C1_HREQ,,,,ADC1_IN6,,ALT5 +GPIO_AD_07,LPI2C2_SDA,LPUART3_RXD,ARM_CM7_RXEV,LPUART2_RTS_B,GPT2_CAPTURE2,GPIO1_IO21,OCOTP_FUSE_LATCHED,XBAR1_INOUT03,,,ADC1_IN7,,ALT5 +GPIO_AD_08,LPI2C2_SCL,LPUART3_TXD,ARM_CM7_TXEV,LPUART2_CTS_B,GPT2_COMPARE3,GPIO1_IO22,EWM_OUT_B,JTAG_TRSTB,,,ADC1_IN8,,ALT7 +GPIO_AD_09,LPSPI2_SDI,FLEXPWM1_PWM3_X,KPP_ROW2,ARM_TRACE_SWO,FLEXIO1_IO21,GPIO1_IO23,REF_CLK_32K,JTAG_TDO,,,ADC1_IN9,,ALT7 +GPIO_AD_10,LPSPI2_SDO,FLEXPWM1_PWM2_X,KPP_COL2,PIT_TRIGGER3,FLEXIO1_IO22,GPIO1_IO24,USB_OTG1_ID,JTAG_TDI,,,ADC1_IN10,,ALT7 +GPIO_AD_11,LPSPI2_PCS0,FLEXPWM1_PWM1_X,KPP_ROW1,PIT_TRIGGER2,FLEXIO1_IO23,GPIO1_IO25,WDOG1_B,JTAG_MOD,,,ADC1_IN11,,ALT7 +GPIO_AD_12,LPSPI2_SCK,FLEXPWM1_PWM0_X,KPP_COL1,PIT_TRIGGER1,FLEXIO1_IO24,GPIO1_IO26,USB_OTG1_PWR,JTAG_TCK,,,ADC1_IN12,,ALT7 +GPIO_AD_13,LPI2C1_SDA,LPUART3_RTS_B,KPP_ROW0,LPUART4_RTS_B,FLEXIO1_IO25,GPIO1_IO27,ARM_NMI,JTAG_TMS,,,ADC1_IN13,,ALT7 +GPIO_AD_14,LPI2C1_SCL,LPUART3_CTS_B,KPP_COL0,LPUART4_CTS_B,FLEXIO1_IO26,GPIO1_IO28,REF_CLK_24M,XBAR1_INOUT02,,,ADC1_IN14,,ALT5 +GPIO_SD_00,FLEXSPI_B_SS0_B,SAI3_TX_SYNC,ARM_CM7_RXEV,CCM_STOP,FLEXIO1_IO06,GPIO2_IO00,SRC_BT_CFG2,,,,,,ALT5 +GPIO_SD_01,FLEXSPI_B_DATA1,SAI3_TX_BCLK,FLEXPWM1_PWM0_B,CCM_CLKO2,FLEXIO1_IO07,GPIO2_IO01,SRC_BT_CFG1,,,,,,ALT5 +GPIO_SD_02,FLEXSPI_B_DATA2,SAI3_TX_DATA,FLEXPWM1_PWM0_A,CCM_CLKO1,FLEXIO1_IO08,GPIO2_IO02,SRC_BT_CFG0,,,,,,ALT5 +GPIO_SD_03,FLEXSPI_B_DATA0,SAI3_RX_DATA,FLEXPWM1_PWM1_B,CCM_REF_EN_B,FLEXIO1_IO09,GPIO2_IO03,SRC_BOOT_MODE1,,,,,,ALT6 +GPIO_SD_04,FLEXSPI_B_DATA3,SAI3_RX_SYNC,FLEXPWM1_PWM1_A,CCM_WAIT,FLEXIO1_IO10,GPIO2_IO04,SRC_BOOT_MODE0,,,,,,ALT6 +GPIO_SD_05,FLEXSPI_A_SS1_B,LPI2C1_SDA,LPSPI1_SDI,,FLEXIO1_IO11,GPIO2_IO05,,,,,,,ALT5 +GPIO_SD_06,FLEXSPI_A_SS0_B,LPI2C1_SCL,LPSPI1_SDO,,FLEXIO1_IO12,GPIO2_IO06,,,,,,,ALT5 +GPIO_SD_07,FLEXSPI_A_DATA1,LPI2C2_SDA,LPSPI1_PCS0,,FLEXIO1_IO13,GPIO2_IO07,,,,,,,ALT5 +GPIO_SD_08,FLEXSPI_A_DATA2,LPI2C2_SCL,LPSPI1_SCK,,FLEXIO1_IO14,GPIO2_IO08,,,,,,,ALT5 +GPIO_SD_09,FLEXSPI_A_DATA0,LPSPI2_SDI,LPUART2_RXD,,FLEXIO1_IO15,GPIO2_IO09,,,,,,,ALT5 +GPIO_SD_10,FLEXSPI_A_SCLK,LPSPI2_SDO,LPUART2_TXD,,FLEXIO1_IO16,GPIO2_IO10,,,,,,,ALT5 +GPIO_SD_11,FLEXSPI_A_DATA3,LPSPI2_SCK,LPUART1_RXD,,FLEXIO1_IO17,GPIO2_IO11,WDOG1_RST_B_DEB,,,,,,ALT5 +GPIO_SD_12,FLEXSPI_A_DQS,LPSPI2_PCS0,LPUART1_TXD,,FLEXIO1_IO18,GPIO2_IO12,WDOG2_RST_B_DEB,,,,,,ALT5 +GPIO_SD_13,FLEXSPI_B_SCLK,SAI3_RX_BCLK,ARM_CM7_TXEV,CCM_PMIC_RDY,FLEXIO1_IO19,GPIO2_IO13,SRC_BT_CFG3,,,,,,ALT5 diff --git a/ports/mimxrt/boards/MIMXRT1020_EVK/mpconfigboard.h b/ports/mimxrt/boards/MIMXRT1020_EVK/mpconfigboard.h index 8598f76bf..d8c0f00e2 100644 --- a/ports/mimxrt/boards/MIMXRT1020_EVK/mpconfigboard.h +++ b/ports/mimxrt/boards/MIMXRT1020_EVK/mpconfigboard.h @@ -4,6 +4,7 @@ #define BOARD_FLASH_SIZE (8 * 1024 * 1024) // i.MX RT1020 EVK has 1 board LED -#define MICROPY_HW_LED1_PIN (GPIO_AD_B0_05) +// Todo: think about replacing the define with searching in the generated pins? +#define MICROPY_HW_LED1_PIN (pin_GPIO_AD_B0_05) #define MICROPY_HW_LED_ON(pin) (mp_hal_pin_low(pin)) #define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_high(pin)) diff --git a/ports/mimxrt/boards/MIMXRT1020_EVK/mpconfigboard.mk b/ports/mimxrt/boards/MIMXRT1020_EVK/mpconfigboard.mk index f3b168952..0f5bb967a 100644 --- a/ports/mimxrt/boards/MIMXRT1020_EVK/mpconfigboard.mk +++ b/ports/mimxrt/boards/MIMXRT1020_EVK/mpconfigboard.mk @@ -2,6 +2,24 @@ MCU_SERIES = MIMXRT1021 MCU_VARIANT = MIMXRT1021DAG5A JLINK_PATH ?= /media/RT1020-EVK/ +JLINK_COMMANDER_SCRIPT = $(BUILD)/script.jlink + + +ifdef JLINK_IP +JLINK_CONNECTION_SETTINGS = -IP $(JLINK_IP) +else +JLINK_CONNECTION_SETTINGS = +endif + + +deploy_jlink: $(BUILD)/firmware.hex + $(ECHO) "ExitOnError 1" > $(JLINK_COMMANDER_SCRIPT) + $(ECHO) "speed auto" >> $(JLINK_COMMANDER_SCRIPT) + $(ECHO) "r" >> $(JLINK_COMMANDER_SCRIPT) + $(ECHO) "st" >> $(JLINK_COMMANDER_SCRIPT) + $(ECHO) "loadfile \"$(realpath $(BUILD)/firmware.hex)\"" >> $(JLINK_COMMANDER_SCRIPT) + $(ECHO) "qc" >> $(JLINK_COMMANDER_SCRIPT) + $(JLINK_PATH)JLinkExe -device $(MCU_VARIANT) -if SWD $(JLINK_CONNECTION_SETTINGS) -CommanderScript $(JLINK_COMMANDER_SCRIPT) deploy: $(BUILD)/firmware.bin cp $< $(JLINK_PATH) diff --git a/ports/mimxrt/boards/MIMXRT1020_EVK/pins.c b/ports/mimxrt/boards/MIMXRT1020_EVK/pins.c deleted file mode 100644 index 946b6efca..000000000 --- a/ports/mimxrt/boards/MIMXRT1020_EVK/pins.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the MicroPython project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2020 Philipp Ebensberger - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "pin.h" - -static pin_af_obj_t GPIO_AD_B0_05_af[] = { - PIN_AF(GPIO1_IO05, PIN_AF_MODE_ALT5, GPIO1, 0x10B0U), -}; - -pin_obj_t GPIO_AD_B0_05 = PIN(GPIO_AD_B0_05, GPIO1, 5, GPIO_AD_B0_05_af); diff --git a/ports/mimxrt/boards/MIMXRT1020_EVK/pins.csv b/ports/mimxrt/boards/MIMXRT1020_EVK/pins.csv new file mode 100644 index 000000000..8420bbd82 --- /dev/null +++ b/ports/mimxrt/boards/MIMXRT1020_EVK/pins.csv @@ -0,0 +1,33 @@ +D0,GPIO_AD_B1_09 +D1,GPIO_AD_B1_08 +D2,GPIO_AD_B0_09 +D3,GPIO_AD_B0_07 +D4,GPIO_AD_B0_05 +D5,GPIO_AD_B0_06 +D6,GPIO_AD_B0_14 +D7,GPIO_AD_B1_06 +D8,GPIO_AD_B1_07 +D9,GPIO_AD_B0_15 +D10,GPIO_AD_B0_11 +D11,GPIO_AD_B0_12 +D12,GPIO_AD_B0_13 +D13,GPIO_AD_B0_10 +D14,GPIO_SD_B1_03 +D15,GPIO_SD_B1_02 +A0,GPIO_AD_B1_10 +A1,GPIO_AD_B1_11 +A2,GPIO_AD_B1_12 +A3,GPIO_AD_B1_13 +A4,GPIO_AD_B1_15 +A5,GPIO_AD_B1_14 +RX,GPIO_AD_B1_09 +TX,GPIO_AD_B1_08 +SDA,GPIO_AD_B1_15 +SCL,GPIO_AD_B1_14 +I2C_SCL,GPIO_SD_B1_02 +I2C_SDA,GPIO_SD_B1_03 +SCK,GPIO_AD_B0_10 +SDI,GPIO_AD_B0_13 +SDO,GPIO_AD_B0_12 +CS,GPIO_AD_B0_11 +LED_GREEN,GPIO_AD_B0_05
\ No newline at end of file diff --git a/ports/mimxrt/boards/MIMXRT1020_EVK/pins.h b/ports/mimxrt/boards/MIMXRT1020_EVK/pins.h deleted file mode 100644 index 158929911..000000000 --- a/ports/mimxrt/boards/MIMXRT1020_EVK/pins.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the MicroPython project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2020 Philipp Ebensberger - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -// NOTE: pins.h shall only be included in in pin.h -// hence no include guards are needed since they will be provided by pin.h - -extern pin_obj_t GPIO_AD_B0_05; diff --git a/ports/mimxrt/boards/MIMXRT1021_af.csv b/ports/mimxrt/boards/MIMXRT1021_af.csv new file mode 100644 index 000000000..668b415f0 --- /dev/null +++ b/ports/mimxrt/boards/MIMXRT1021_af.csv @@ -0,0 +1,94 @@ +Pad,ALT0, ALT1, ALT2, ALT3, ALT4, ALT5, ALT6, ALT7, ALT8, ALT9,ADC,ACMP,Default +GPIO_AD_B0_00,JTAG_TMS,,,,,GPIO1_IO00,USBPHY1_TSTI_TX_EN,GPT1_COMPARE1,,,,,ALT0 +GPIO_AD_B0_01,JTAG_TCK,,,,,GPIO1_IO01,USBPHY1_TSTI_TX_HIZ,GPT1_CAPTURE2,,,,,ALT0 +GPIO_AD_B0_02,JTAG_MOD,,,,,GPIO1_IO02,USBPHY1_TSTI_TX_LS_MODE,GPT1_CAPTURE1,,,,,ALT0 +GPIO_AD_B0_03,JTAG_TDI,USDHC2_CD_B,WDOG1_B,SAI1_MCLK,USDHC1_WP,GPIO1_IO03,USB_OTG1_OC,CCM_PMIC_RDY,,,,,ALT0 +GPIO_AD_B0_04,JTAG_TDO,FLEXCAN1_TX,USDHC1_WP,TMR2_TIMER0,ENET_MDIO,GPIO1_IO04,USB_OTG1_PWR,EWM_OUT_B,,,,,ALT0 +GPIO_AD_B0_05,JTAG_TRSTB,FLEXCAN1_RX,USDHC1_CD_B,TMR2_TIMER1,ENET_MDC,GPIO1_IO05,USB_OTG1_ID,ARM_NMI,,,,,ALT0 +GPIO_AD_B0_06,PIT_TRIGGER0,MQS_RIGHT,LPUART1_TXD,TMR2_TIMER2,FLEXPWM2_PWMA3,GPIO1_IO06,REF_32K_OUT,,,,,,ALT5 +GPIO_AD_B0_07,PIT_TRIGGER1,MQS_LEFT,LPUART1_RXD,TMR2_TIMER3,FLEXPWM2_PWMB3,GPIO1_IO07,REF_24M_OUT,,,,,,ALT5 +GPIO_AD_B0_08,ENET_TX_CLK,LPI2C3_SCL,LPUART1_CTS_B,KPP_COL0,ENET_REF_CLK,GPIO1_IO08,ARM_CM7_TXEV,,,,,ACMP1_IN4,ALT5 +GPIO_AD_B0_09,ENET_RX_DATA1,LPI2C3_SDA,LPUART1_RTS_B,KPP_ROW0,,GPIO1_IO09,ARM_CM7_RXEV,,,,,ACMP2_IN4,ALT5 +GPIO_AD_B0_10,ENET_RX_DATA0,LPSPI1_SCK,LPUART5_TXD,KPP_COL1,FLEXPWM2_PWMA2,GPIO1_IO10,ARM_TRACE_CLK,,,,,ACMP3_IN4,ALT5 +GPIO_AD_B0_11,ENET_RX_EN,LPSPI1_PCS0,LPUART5_RXD,KPP_ROW1,FLEXPWM2_PWMB2,GPIO1_IO11,ARM_TRACE_SWO,,,,,ACMP4_IN4,ALT5 +GPIO_AD_B0_12,ENET_RX_ER,LPSPI1_SDO,LPUART3_CTS_B,KPP_COL2,FLEXPWM2_PWMA1,GPIO1_IO12,ARM_TRACE0,SNVS_VIO_5_CTL,,,ADC1_IN0,,ALT5 +GPIO_AD_B0_13,ENET_TX_EN,LPSPI1_SDI,LPUART3_RTS_B,KPP_ROW2,FLEXPWM2_PWMB1,GPIO1_IO13,,SNVS_VIO_5_B,,,ADC2_IN0,,ALT5 +GPIO_AD_B0_14,ENET_TX_DATA0,FLEXCAN2_TX,LPUART3_TXD,KPP_COL3,FLEXPWM2_PWMA0,GPIO1_IO14,,WDOG1_ANY,,,"ADC1_IN1,ADC2_IN1","ACMP1_IN0,ACMP2_IN0,ACMP3_IN0,ACMP4_IN0",ALT5 +GPIO_AD_B0_15,ENET_TX_DATA1,FLEXCAN2_RX,LPUART3_RXD,KPP_ROW3,FLEXPWM2_PWMB0,GPIO1_IO15,,,,,"ADC1_IN2,ADC2_IN2","ACMP1_IN1,ACMP2_IN1,ACMP3_IN1,ACMP4_IN1",ALT5 +GPIO_AD_B1_00,SEMC_RDY,FLEXSPI_A_DATA3,FLEXCAN2_TX,SAI1_MCLK,FLEXIO1_D15,GPIO1_IO16,ENET_1588_EVENT2_OUT,KPP_COL4,,,,ACMP1_IN2,ALT5 +GPIO_AD_B1_01,SEMC_CSX0,FLEXSPI_A_SCLK,FLEXCAN2_RX,SAI1_TX_BCLK,FLEXIO1_D14,GPIO1_IO17,ENET_1588_EVENT2_IN,KPP_ROW4,,,ADC1_IN3,ACMP2_IN2,ALT5 +GPIO_AD_B1_02,SEMC_CSX1,FLEXSPI_A_DATA0,LPSPI4_SCK,SAI1_TX_SYNC,FLEXIO1_D13,GPIO1_IO18,ENET_1588_EVENT3_OUT,KPP_COL5,,,ADC2_IN3,ACMP3_IN2,ALT5 +GPIO_AD_B1_03,SEMC_CSX2,FLEXSPI_A_DATA2,LPSPI4_PCS0,SAI1_TX_DATA0,FLEXIO1_D12,GPIO1_IO19,ENET_1588_EVENT3_IN,KPP_ROW5,,,ADC1_IN4,ACMP4_IN2,ALT5 +GPIO_AD_B1_04,SEMC_CSX3,FLEXSPI_A_DATA1,LPSPI4_SDO,SAI1_RX_SYNC,FLEXIO1_D11,GPIO1_IO20,LPSPI1_PCS1,KPP_COL6,,,ADC2_IN4,ACMP1_IN3,ALT5 +GPIO_AD_B1_05,USDHC1_WP,FLEXSPI_A_SS0_B,LPSPI4_SDI,SAI1_RX_DATA0,FLEXIO1_D10,GPIO1_IO21,LPSPI1_PCS2,KPP_ROW6,,,"ADC1_IN5,ADC2_IN5",ACMP2_IN3,ALT5 +GPIO_AD_B1_06,USDHC1_RESET_B,FLEXPWM1_PWMA0,LPUART2_CTS_B,SAI1_RX_BCLK,FLEXIO1_D09,GPIO1_IO22,LPSPI1_PCS3,KPP_COL7,,,"ADC1_IN6,ADC2_IN6",ACMP3_IN3,ALT5 +GPIO_AD_B1_07,USDHC1_VSELECT,FLEXPWM1_PWMB0,LPUART2_RTS_B,SAI1_TX_DATA1,FLEXIO1_D08,GPIO1_IO23,LPSPI3_PCS3,KPP_ROW7,,,"ADC1_IN7,ADC2_IN7",ACMP4_IN3,ALT5 +GPIO_AD_B1_08,LPI2C2_SCL,FLEXPWM1_PWMA1,LPUART2_TXD,SAI1_TX_DATA2,FLEXIO1_D07,GPIO1_IO24,LPSPI3_PCS2,XBAR_INOUT12,,,"ADC1_IN8,ADC2_IN8",ACMP1_IN5,ALT5 +GPIO_AD_B1_09,LPI2C2_SDA,FLEXPWM1_PWMB1,LPUART2_RXD,SAI1_TX_DATA3,FLEXIO1_D06,GPIO1_IO25,LPSPI3_PCS1,XBAR_INOUT13,,,"ADC1_IN9,ADC2_IN9",ACMP2_IN5,ALT5 +GPIO_AD_B1_10,USB_OTG1_PWR,FLEXPWM1_PWMA2,LPUART4_TXD,USDHC1_CD_B,FLEXIO1_D05,GPIO1_IO26,GPT2_CAPTURE1,,,,"ADC1_IN10,ADC2_IN10",ACMP3_IN5,ALT5 +GPIO_AD_B1_11,USB_OTG1_ID,FLEXPWM1_PWMB2,LPUART4_RXD,USDHC1_WP,FLEXIO1_D04,GPIO1_IO27,GPT2_COMPARE1,,,,"ADC1_IN11,ADC2_IN11",ACMP4_IN5,ALT5 +GPIO_AD_B1_12,USB_OTG1_OC,ACMP1_OUT,LPSPI3_SCK,USDHC2_CD_B,FLEXIO1_D03,GPIO1_IO28,FLEXPWM1_PWMA3,,,,"ADC1_IN12,ADC2_IN12","ACMP1_IN6,ACMP1_OUT",ALT5 +GPIO_AD_B1_13,LPI2C1_HREQ,ACMP2_OUT,LPSPI3_PCS0,USDHC2_WP,FLEXIO1_D02,GPIO1_IO29,FLEXPWM1_PWMB3,,,,"ADC1_IN13,ADC2_IN13","ACMP2_IN6,ACMP2_OUT",ALT5 +GPIO_AD_B1_14,LPI2C1_SCL,ACMP3_OUT,LPSPI3_SDO,ENET_1588_EVENT0_OUT,FLEXIO1_D01,GPIO1_IO30,,,,,"ADC1_IN14,ADC2_IN14","ACMP3_IN6,ACMP3_OUT",ALT5 +GPIO_AD_B1_15,LPI2C1_SDA,ACMP4_OUT,LPSPI3_SDI,ENET_1588_EVENT0_IN,FLEXIO1_D00,GPIO1_IO31,,,,,"ADC1_IN15,ADC2_IN15","ACMP4_IN6,ACMP4_OUT",ALT5 +GPIO_EMC_00,SEMC_DA00,TMR2_TIMER0,LPUART4_CTS_B,SPDIF_SR_CLK,LPSPI2_SCK,GPIO2_IO00,FLEXCAN1_TX,PIT_TRIGGER2,,,,,ALT5 +GPIO_EMC_01,SEMC_DA01,TMR2_TIMER1,LPUART4_RTS_B,SPDIF_OUT,LPSPI2_PCS0,GPIO2_IO01,FLEXCAN1_RX,PIT_TRIGGER3,,,,,ALT5 +GPIO_EMC_02,SEMC_DA02,TMR2_TIMER2,LPUART4_TXD,SPDIF_LOCK,LPSPI2_SDO,GPIO2_IO02,LPI2C1_SCL,,,,,,ALT5 +GPIO_EMC_03,SEMC_DA03,TMR2_TIMER3,LPUART4_RXD,SPDIF_EXT_CLK,LPSPI2_SDI,GPIO2_IO03,LPI2C1_SDA,,,,,,ALT5 +GPIO_EMC_04,SEMC_DA04,XBAR_INOUT04,SPDIF_OUT,SAI2_TX_BCLK,FLEXIO1_D16,GPIO2_IO04,USBPHY1_TSTO_PLL_CLK20DIV,,,,,,ALT5 +GPIO_EMC_05,SEMC_DA05,XBAR_INOUT05,SPDIF_IN,SAI2_TX_SYNC,FLEXIO1_D17,GPIO2_IO05,USBPHY1_TSTI_TX_HS_MODE,,,,,,ALT5 +GPIO_EMC_06,SEMC_DA06,XBAR_INOUT06,LPUART3_TXD,SAI2_TX_DATA,FLEXIO1_D18,GPIO2_IO06,USBPHY1_TSTI_TX_DN,,,,,,ALT5 +GPIO_EMC_07,SEMC_DA07,XBAR_INOUT07,LPUART3_RXD,SAI2_RX_SYNC,FLEXIO1_D19,GPIO2_IO07,USBPHY1_TSTO_RX_SQUELCH,,,,,,ALT5 +GPIO_EMC_08,SEMC_DM0,XBAR_INOUT08,FLEXCAN2_TX,SAI2_RX_DATA,FLEXIO1_D20,GPIO2_IO08,USBPHY1_TSTO_RX_DISCON_DET,,,,,,ALT5 +GPIO_EMC_09,SEMC_WE,XBAR_INOUT09,FLEXCAN2_RX,SAI2_RX_BCLK,FLEXIO1_D21,GPIO2_IO09,USBPHY1_TSTO_RX_HS_RXD,,,,,,ALT5 +GPIO_EMC_10,SEMC_CAS,XBAR_INOUT10,LPI2C4_SDA,SAI1_TX_SYNC,LPSPI2_SCK,GPIO2_IO10,FLEXPWM2_PWMX0,,,,,,ALT5 +GPIO_EMC_11,SEMC_RAS,XBAR_INOUT11,LPI2C4_SCL,SAI1_TX_BCLK,LPSPI2_PCS0,GPIO2_IO11,FLEXPWM2_PWMX1,,,,,,ALT5 +GPIO_EMC_12,SEMC_CS0,XBAR_INOUT12,LPUART6_TXD,SAI1_TX_DATA0,LPSPI2_SDO,GPIO2_IO12,FLEXPWM2_PWMX2,,,,,,ALT5 +GPIO_EMC_13,SEMC_BA0,XBAR_INOUT13,LPUART6_RXD,SAI1_RX_DATA0,LPSPI2_SDI,GPIO2_IO13,FLEXPWM2_PWMX3,CCM_PMIC_RDY,,,,,ALT5 +GPIO_EMC_14,SEMC_BA1,XBAR_INOUT14,LPUART6_CTS_B,SAI1_RX_BCLK,LPSPI2_PCS1,GPIO2_IO14,FLEXCAN1_TX,,,,,,ALT5 +GPIO_EMC_15,SEMC_ADDR10,XBAR_INOUT15,LPUART6_RTS_B,SAI1_RX_SYNC,WDOG1_B,GPIO2_IO15,FLEXCAN1_RX,,,,,,ALT5 +GPIO_EMC_16,SEMC_ADDR00,,MQS_RIGHT,SAI2_MCLK,,GPIO2_IO16,SRC_BOOT_MODE0,,,,,,ALT5 +GPIO_EMC_17,SEMC_ADDR01,,MQS_LEFT,SAI3_MCLK,,GPIO2_IO17,SRC_BOOT_MODE1,,,,,,ALT5 +GPIO_EMC_18,SEMC_ADDR02,XBAR_INOUT16,LPI2C2_SDA,SAI1_RX_SYNC,FLEXIO1_D22,GPIO2_IO18,SRC_BT_CFG0,,,,,,ALT5 +GPIO_EMC_19,SEMC_ADDR03,XBAR_INOUT17,LPI2C2_SCL,SAI1_RX_BCLK,FLEXIO1_D23,GPIO2_IO19,SRC_BT_CFG1,,,,,,ALT5 +GPIO_EMC_20,SEMC_ADDR04,FLEXPWM1_PWMA3,LPUART2_CTS_B,SAI1_MCLK,FLEXIO1_D24,GPIO2_IO20,SRC_BT_CFG2,,,,,,ALT5 +GPIO_EMC_21,SEMC_ADDR05,FLEXPWM1_PWMB3,LPUART2_RTS_B,SAI1_RX_DATA0,FLEXIO1_D25,GPIO2_IO21,SRC_BT_CFG3,,,,,,ALT5 +GPIO_EMC_22,SEMC_ADDR06,FLEXPWM1_PWMA2,LPUART2_TXD,SAI1_TX_DATA3,FLEXIO1_D26,GPIO2_IO22,SRC_BT_CFG4,,,,,,ALT5 +GPIO_EMC_23,SEMC_ADDR07,FLEXPWM1_PWMB2,LPUART2_RXD,SAI1_TX_DATA2,FLEXIO1_D27,GPIO2_IO23,SRC_BT_CFG5,,,,,,ALT5 +GPIO_EMC_24,SEMC_ADDR08,FLEXPWM1_PWMA1,LPUART8_CTS_B,SAI1_TX_DATA1,FLEXIO1_D28,GPIO2_IO24,SRC_BT_CFG6,,,,,,ALT5 +GPIO_EMC_25,SEMC_ADDR09,FLEXPWM1_PWMB1,LPUART8_RTS_B,SAI1_TX_DATA0,FLEXIO1_D29,GPIO2_IO25,SRC_BT_CFG7,,,,,,ALT5 +GPIO_EMC_26,SEMC_ADDR11,FLEXPWM1_PWMA0,LPUART8_TXD,SAI1_TX_BCLK,FLEXIO1_D30,GPIO2_IO26,SRC_BT_CFG8,,,,,,ALT5 +GPIO_EMC_27,SEMC_ADDR12,FLEXPWM1_PWMB0,LPUART8_RXD,SAI1_TX_SYNC,FLEXIO1_D31,GPIO2_IO27,SRC_BT_CFG9,,,,,,ALT5 +GPIO_EMC_28,SEMC_DQS,FLEXPWM2_PWMA3,XBAR_INOUT18,SAI3_MCLK,EWM_OUT_B,GPIO2_IO28,GPT2_CAPTURE2,FLEXPWM1_PWMX0,,,,,ALT5 +GPIO_EMC_29,SEMC_CKE,FLEXPWM2_PWMB3,XBAR_INOUT19,SAI3_RX_BCLK,WDOG2_RST_B_DEB,GPIO2_IO29,GPT2_COMPARE2,FLEXPWM1_PWMX1,,,,,ALT5 +GPIO_EMC_30,SEMC_CLK,FLEXPWM2_PWMA2,LPUART4_CTS_B,SAI3_RX_SYNC,WDOG1_RST_B_DEB,GPIO2_IO30,GPT2_COMPARE3,FLEXPWM1_PWMX2,,,,,ALT5 +GPIO_EMC_31,SEMC_DM1,FLEXPWM2_PWMB2,LPUART4_RTS_B,SAI3_RX_DATA,WDOG2_B,GPIO2_IO31,GPT2_CLK,FLEXPWM1_PWMX3,,,,,ALT5 +GPIO_EMC_32,SEMC_DA08,TMR1_TIMER0,LPUART4_TXD,SAI3_TX_DATA,LPSPI4_SCK,GPIO3_IO00,USBPHY1_TSTO_RX_FS_RXD,REF_24M_OUT,,,,,ALT5 +GPIO_EMC_33,SEMC_DA09,TMR1_TIMER1,LPUART4_RXD,SAI3_TX_BCLK,LPSPI4_PCS0,GPIO3_IO01,USBPHY1_TSTI_TX_DP,SRC_TESTER_ACK,,,,,ALT5 +GPIO_EMC_34,SEMC_DA10,TMR1_TIMER2,LPUART7_TXD,SAI3_TX_SYNC,LPSPI4_SDO,GPIO3_IO02,ENET_CRS,,,,,,ALT5 +GPIO_EMC_35,SEMC_DA11,TMR1_TIMER3,LPUART7_RXD,USDHC2_WP,LPSPI4_SDI,GPIO3_IO03,ENET_COL,,,,,,ALT5 +GPIO_EMC_36,SEMC_DA12,FLEXPWM2_PWMA1,LPUART5_CTS_B,CCM_PMIC_RDY,LPSPI4_PCS1,GPIO3_IO04,ENET_RX_CLK,USDHC1_WP,,,,,ALT5 +GPIO_EMC_37,SEMC_DA13,FLEXPWM2_PWMB1,LPUART5_RTS_B,MQS_RIGHT,LPSPI4_PCS2,GPIO3_IO05,ENET_RX_DATA3,USDHC1_VSELECT,,,,,ALT5 +GPIO_EMC_38,SEMC_DA14,FLEXPWM2_PWMA0,LPUART5_TXD,MQS_LEFT,LPSPI4_PCS3,GPIO3_IO06,ENET_RX_DATA2,USDHC1_CD_B,,,,,ALT5 +GPIO_EMC_39,SEMC_DA15,FLEXPWM2_PWMB0,LPUART5_RXD,USB_OTG1_OC,WDOG1_B,GPIO3_IO07,ENET_TX_ER,GPT1_CLK,,,,,ALT5 +GPIO_EMC_40,SEMC_CSX0,XBAR_INOUT18,SPDIF_OUT,USB_OTG1_ID,ENET_MDIO,GPIO3_IO08,ENET_TX_DATA3,GPT1_COMPARE3,,,,,ALT5 +GPIO_EMC_41,SEMC_RDY,XBAR_INOUT19,SPDIF_IN,USB_OTG1_PWR,ENET_MDC,GPIO3_IO09,ENET_TX_DATA2,GPT1_COMPARE2,,,,,ALT5 +GPIO_SD_B0_00,USDHC1_DATA2,TMR1_TIMER0,SAI1_MCLK,SAI2_MCLK,LPI2C3_SCL,GPIO3_IO13,FLEXSPI_A_SS1_B,XBAR_INOUT14,,,,,ALT5 +GPIO_SD_B0_01,USDHC1_DATA3,TMR1_TIMER1,REF_24M_OUT,SAI2_RX_SYNC,LPI2C3_SDA,GPIO3_IO14,FLEXSPI_B_SS1_B,XBAR_INOUT15,,,,,ALT5 +GPIO_SD_B0_02,USDHC1_CMD,TMR1_TIMER2,LPUART7_CTS_B,SAI2_RX_BCLK,LPSPI1_SCK,GPIO3_IO15,ENET_MDIO,XBAR_INOUT16,,,,,ALT5 +GPIO_SD_B0_03,USDHC1_CLK,TMR1_TIMER3,LPUART7_RTS_B,SAI2_RX_DATA,LPSPI1_PCS0,GPIO3_IO16,ENET_MDC,,,,,,ALT5 +GPIO_SD_B0_04,USDHC1_DATA0,FLEXCAN2_TX,LPUART7_TXD,SAI2_TX_DATA,LPSPI1_SDO,GPIO3_IO17,FLEXSPI_B_SS0_B,,,,,,ALT5 +GPIO_SD_B0_05,USDHC1_DATA1,FLEXCAN2_RX,LPUART7_RXD,SAI2_TX_BCLK,LPSPI1_SDI,GPIO3_IO18,FLEXSPI_B_DQS,,,,,,ALT5 +GPIO_SD_B0_06,USDHC1_CD_B,USDHC1_RESET_B,REF_32K_OUT,SAI2_TX_SYNC,WDOG1_B,GPIO3_IO19,XBAR_INOUT17,,,,,,ALT5 +GPIO_SD_B1_00,USDHC2_DATA2,FLEXSPI_B_DATA3,LPUART6_TXD,XBAR_INOUT10,FLEXCAN1_TX,GPIO3_IO20,,,,,,,ALT5 +GPIO_SD_B1_01,USDHC2_DATA3,FLEXSPI_B_SCLK,LPUART6_RXD,FLEXSPI_A_SS1_B,FLEXCAN1_RX,GPIO3_IO21,,,,,,,ALT5 +GPIO_SD_B1_02,USDHC2_CMD,FLEXSPI_B_DATA0,LPUART8_TXD,LPI2C4_SCL,ENET_1588_EVENT1_OUT,GPIO3_IO22,CCM_CLKO1,,,,,,ALT5 +GPIO_SD_B1_03,USDHC2_CLK,FLEXSPI_B_DATA2,LPUART8_RXD,LPI2C4_SDA,ENET_1588_EVENT1_IN,GPIO3_IO23,CCM_CLKO2,,,,,,ALT5 +GPIO_SD_B1_04,USDHC2_DATA0,FLEXSPI_B_DATA1,ENET_TX_CLK,ENET_REF_CLK,EWM_OUT_B,GPIO3_IO24,CCM_WAIT,,,,,,ALT5 +GPIO_SD_B1_05,USDHC2_DATA1,FLEXSPI_A_DQS,ENET_RX_DATA1,SAI3_MCLK,FLEXSPI_B_SS0_B,GPIO3_IO25,CCM_PMIC_RDY,,,,,,ALT5 +GPIO_SD_B1_06,USDHC2_CD_B,FLEXSPI_A_DATA3,ENET_RX_DATA0,SAI3_TX_BCLK,LPSPI2_PCS0,GPIO3_IO26,CCM_STOP,,,,,,ALT5 +GPIO_SD_B1_07,USDHC2_RESET_B,FLEXSPI_A_SCLK,ENET_RX_EN,SAI3_TX_SYNC,LPSPI2_SCK,GPIO3_IO27,,,,,,,ALT5 +GPIO_SD_B1_08,USDHC2_DATA4,FLEXSPI_A_DATA0,ENET_RX_ER,SAI3_TX_DATA,LPSPI2_SDO,GPIO3_IO28,,,,,,,ALT5 +GPIO_SD_B1_09,USDHC2_DATA5,FLEXSPI_A_DATA2,ENET_TX_EN,SAI3_RX_BCLK,LPSPI2_SDI,GPIO3_IO29,CCM_REF_EN_B,,,,,,ALT5 +GPIO_SD_B1_10,USDHC2_DATA6,FLEXSPI_A_DATA1,ENET_TX_DATA0,SAI3_RX_SYNC,LPSPI2_PCS2,GPIO3_IO30,SRC_SYSTEM_RESET,,,,,,ALT5 +GPIO_SD_B1_11,USDHC2_DATA7,FLEXSPI_A_SS0_B,ENET_TX_DATA1,SAI3_RX_DATA,LPSPI2_PCS3,GPIO3_IO31,SRC_EARLY_RESET,,,,,,ALT5 diff --git a/ports/mimxrt/boards/MIMXRT1050_EVK/mpconfigboard.h b/ports/mimxrt/boards/MIMXRT1050_EVK/mpconfigboard.h index 5a733bbd9..2337496d2 100644 --- a/ports/mimxrt/boards/MIMXRT1050_EVK/mpconfigboard.h +++ b/ports/mimxrt/boards/MIMXRT1050_EVK/mpconfigboard.h @@ -4,6 +4,6 @@ #define BOARD_FLASH_SIZE (64 * 1024 * 1024) // MIMXRT1050_EVK has 1 user LED -#define MICROPY_HW_LED1_PIN (GPIO_AD_B0_09) +#define MICROPY_HW_LED1_PIN (pin_GPIO_AD_B0_09) #define MICROPY_HW_LED_ON(pin) (mp_hal_pin_low(pin)) #define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_high(pin)) diff --git a/ports/mimxrt/boards/MIMXRT1050_EVK/pins.c b/ports/mimxrt/boards/MIMXRT1050_EVK/pins.c deleted file mode 100644 index d5da9c6f9..000000000 --- a/ports/mimxrt/boards/MIMXRT1050_EVK/pins.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the MicroPython project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2020 NXP - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "pin.h" - -static pin_af_obj_t GPIO_AD_B0_09_af[] = { - PIN_AF(GPIO1_IO09, PIN_AF_MODE_ALT5, GPIO1, 0x10B0U), -}; - -pin_obj_t GPIO_AD_B0_09 = PIN(GPIO_AD_B0_09, GPIO1, 9, GPIO_AD_B0_09_af); diff --git a/ports/mimxrt/boards/MIMXRT1050_EVK/pins.csv b/ports/mimxrt/boards/MIMXRT1050_EVK/pins.csv new file mode 100644 index 000000000..afd63d4f9 --- /dev/null +++ b/ports/mimxrt/boards/MIMXRT1050_EVK/pins.csv @@ -0,0 +1,51 @@ +D0,GPIO_AD_B1_07 +D1,GPIO_AD_B1_06 +D2,GPIO_AD_B0_11 +D3,GPIO_AD_B1_08 +D4,GPIO_AD_B0_09 +D5,GPIO_AD_B0_10 +D6,GPIO_AD_B1_02 +D7,GPIO_AD_B1_03 +D8,GPIO_AD_B0_03 +D9,GPIO_AD_B0_02 +D10,GPIO_SD_B0_01 +D11,GPIO_SD_B0_02 +D12,GPIO_SD_B0_03 +D13,GPIO_SD_B0_00 +D14,GPIO_AD_B1_01 +D15,GPIO_AD_B1_00 +A0,GPIO_AD_B1_10 +A1,GPIO_AD_B1_11 +A2,GPIO_AD_B1_04 +A3,GPIO_AD_B1_05 +A4,GPIO_AD_B1_01 +A5,GPIO_AD_B1_00 +RX,GPIO_AD_B1_07 +TX,GPIO_AD_B1_06 +SCL,GPIO_AD_B1_00 +SDA,GPIO_AD_B1_01 +SCK,GPIO_SD_B0_00 +SDI,GPIO_SD_B0_03 +SDO,GPIO_SD_B0_02 +CS,GPIO_SD_B0_01 +LED_GREEN,GPIO_AD_B0_09 +GPIO_AD_B1_07,GPIO_AD_B1_07 +GPIO_AD_B1_06,GPIO_AD_B1_06 +GPIO_AD_B0_11,GPIO_AD_B0_11 +GPIO_AD_B1_08,GPIO_AD_B1_08 +GPIO_AD_B0_09,GPIO_AD_B0_09 +GPIO_AD_B0_10,GPIO_AD_B0_10 +GPIO_AD_B1_02,GPIO_AD_B1_02 +GPIO_AD_B1_03,GPIO_AD_B1_03 +GPIO_AD_B0_03,GPIO_AD_B0_03 +GPIO_AD_B0_02,GPIO_AD_B0_02 +GPIO_SD_B0_01,GPIO_SD_B0_01 +GPIO_SD_B0_02,GPIO_SD_B0_02 +GPIO_SD_B0_03,GPIO_SD_B0_03 +GPIO_SD_B0_00,GPIO_SD_B0_00 +GPIO_AD_B1_01,GPIO_AD_B1_01 +GPIO_AD_B1_00,GPIO_AD_B1_00 +GPIO_AD_B1_10,GPIO_AD_B1_10 +GPIO_AD_B1_11,GPIO_AD_B1_11 +GPIO_AD_B1_04,GPIO_AD_B1_04 +GPIO_AD_B1_05,GPIO_AD_B1_05 diff --git a/ports/mimxrt/boards/MIMXRT1050_EVK/pins.h b/ports/mimxrt/boards/MIMXRT1050_EVK/pins.h deleted file mode 100644 index baef51c6c..000000000 --- a/ports/mimxrt/boards/MIMXRT1050_EVK/pins.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the MicroPython project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2020 NXP - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -// NOTE: pins.h shall only be included in in pin.h -// hence no include guards are needed since they will be provided by pin.h - -extern pin_obj_t GPIO_AD_B0_09; diff --git a/ports/mimxrt/boards/MIMXRT1052_af.csv b/ports/mimxrt/boards/MIMXRT1052_af.csv new file mode 100644 index 000000000..754bf4ab7 --- /dev/null +++ b/ports/mimxrt/boards/MIMXRT1052_af.csv @@ -0,0 +1,125 @@ +Pad,ALT0, ALT1, ALT2, ALT3, ALT4, ALT5, ALT6, ALT7, ALT8, ALT9,ADC,ACMP,Default +GPIO_AD_B0_00,FLEXPWM2_PWM3_A,XBAR_INOUT14,REF_CLK_32K,USB_OTG2_ID,LPI2C1_SCLS,GPIO1_IO00,USDHC1_RESET_B,LPSPI3_SCK,,,,ACMP1_IN4,ALT5 +GPIO_AD_B0_01,FLEXPWM2_PWM3_B,XBAR_INOUT15,REF_CLK_24M,USB_OTG1_ID,LPI2C1_SDAS,GPIO1_IO01,EWM_OUT_B,LPSPI3_SOUT,,,,ACMP2_IN4,ALT5 +GPIO_AD_B0_02,FLEXCAN2_TX,XBAR_INOUT16,LPUART6_TXD,USB_OTG1_PWR,FLEXPWM1_PWM0_X,GPIO1_IO02,LPI2C1_HREQ,LPSPI3_SIN,,,,ACMP3_IN4,ALT5 +GPIO_AD_B0_03,FLEXCAN2_RX,XBAR_INOUT17,LPUART6_RXD,USB_OTG1_OC,FLEXPWM1_PWM1_X,GPIO1_IO03,REF_CLK_24M,LPSPI3_PCS0,,,,ACMP4_IN4,ALT5 +GPIO_AD_B0_04,SRC_BOOT_MODE0,MQS_RIGHT,ENET_TX_DATA3,SAI2_TX_SYNC,CSI_DATA09,GPIO1_IO04,PIT_TRIGGER0,LPSPI3_PCS1,,,,,ALT0 +GPIO_AD_B0_05,SRC_BOOT_MODE1,MQS_LEFT,ENET_TX_DATA2,SAI2_TX_BCLK,CSI_DATA08,GPIO1_IO05,XBAR_INOUT17,LPSPI3_PCS2,,,,,ALT0 +GPIO_AD_B0_06,"JTAG_TMS,SWD_DIO",GPT2_COMPARE1,ENET_RX_CLK,SAI2_RX_BCLK,CSI_DATA07,GPIO1_IO06,XBAR_INOUT18,LPSPI3_PCS3,,,,,ALT0 +GPIO_AD_B0_07,"JTAG_TCK,SWD_CLK",GPT2_COMPARE2,ENET_TX_ER,SAI2_RX_SYNC,CSI_DATA06,GPIO1_IO07,XBAR_INOUT19,ENET_1588_EVENT3_OUT,,,,,ALT0 +GPIO_AD_B0_08,JTAG_MOD,GPT2_COMPARE3,ENET_RX_DATA3,SAI2_RX_DATA,CSI_DATA05,GPIO1_IO08,XBAR_INOUT20,ENET_1588_EVENT3_IN,,,,,ALT0 +GPIO_AD_B0_09,JTAG_TDI,FLEXPWM2_PWM3_A,ENET_RX_DATA2,SAI2_TX_DATA,CSI_DATA04,GPIO1_IO09,XBAR_INOUT21,GPT2_CLK,,,,,ALT0 +GPIO_AD_B0_10,JTAG_TDO,FLEXPWM1_PWM3_A,ENET_CRS,SAI2_MCLK,CSI_DATA03,GPIO1_IO10,XBAR_INOUT22,ENET_1588_EVENT0_OUT,,,,,ALT0 +GPIO_AD_B0_11,JTAG_TRSTB,FLEXPWM1_PWM3_B,ENET_COL,WDOG1_B,CSI_DATA02,GPIO1_IO11,XBAR_INOUT23,ENET_1588_EVENT0_IN,,,,,ALT0 +GPIO_AD_B0_12,LPI2C4_SCL,CCM_PMIC_READY,LPUART1_TXD,WDOG2_B,FLEXPWM1_PWM2_X,GPIO1_IO12,ENET_1588_EVENT1_OUT,,,,ADC1_IN1,,ALT5 +GPIO_AD_B0_13,LPI2C4_SDA,GPT1_CLK,LPUART1_RXD,EWM_OUT_B,FLEXPWM1_PWM3_X,GPIO1_IO13,ENET_1588_EVENT1_IN,REF_CLK_24M,,,ADC1_IN2,ACMP1_IN2,ALT5 +GPIO_AD_B0_14,USB_OTG2_OC,XBAR_INOUT24,LPUART1_CTS_B,ENET_1588_EVENT0_OUT,CSI_VSYNC,GPIO1_IO14,FLEXCAN2_TX,WDOG1_ANY,,,ADC1_IN3,ACMP2_IN2,ALT5 +GPIO_AD_B0_15,USB_OTG2_PWR,XBAR_INOUT25,LPUART1_RTS_B,ENET_1588_EVENT0_IN,CSI_HSYNC,GPIO1_IO15,FLEXCAN2_RX,WDOG1_RST_B_DEB,,,ADC1_IN4,ACMP3_IN2,ALT5 +GPIO_AD_B1_00,USB_OTG2_ID,TMR3_TIMER0,LPUART2_CTS_B,LPI2C1_SCL,WDOG1_B,GPIO1_IO16,USDHC1_WP,KPP_ROW7,,,"ADC1_IN5,ADC2_IN5",ACMP4_IN2,ALT5 +GPIO_AD_B1_01,USB_OTG1_PWR,TMR3_TIMER1,LPUART2_RTS_B,LPI2C1_SDA,CCM_PMIC_READY,GPIO1_IO17,USDHC1_VSELECT,KPP_COL7,,,"ADC1_IN6,ADC2_IN6","ACMP1_IN0,ACMP2_IN0,ACMP3_IN0,ACMP4_IN0",ALT5 +GPIO_AD_B1_02,USB_OTG1_ID,TMR3_TIMER2,LPUART2_TXD,SPDIF_OUT,ENET_1588_EVENT2_OUT,GPIO1_IO18,USDHC1_CD_B,KPP_ROW6,,,"ADC1_IN7,ADC2_IN7",ACMP1_IN3,ALT5 +GPIO_AD_B1_03,USB_OTG1_OC,TMR3_TIMER3,LPUART2_RXD,SPDIF_IN,ENET_1588_EVENT2_IN,GPIO1_IO19,USDHC2_CD_B,KPP_COL6,,,"ADC1_IN8,ADC2_IN8",ACMP2_IN3,ALT5 +GPIO_AD_B1_04,FLEXSPI_B_DATA3,ENET_MDC,LPUART3_CTS_B,SPDIF_SR_CLK,CSI_PIXCLK,GPIO1_IO20,USDHC2_DATA0,KPP_ROW5,,,"ADC1_IN9,ADC2_IN9",ACMP3_IN3,ALT5 +GPIO_AD_B1_05,FLEXSPI_B_DATA2,ENET_MDIO,LPUART3_RTS_B,SPDIF_OUT,CSI_MCLK,GPIO1_IO21,USDHC2_DATA1,KPP_COL5,,,"ADC1_IN10,ADC2_IN10",ACMP4_IN3,ALT5 +GPIO_AD_B1_06,FLEXSPI_B_DATA1,LPI2C3_SDA,LPUART3_TXD,SPDIF_LOCK,CSI_VSYNC,GPIO1_IO22,USDHC2_DATA2,KPP_ROW4,,,"ADC1_IN11,ADC2_IN11","ACMP1_IN1,ACMP2_IN1,ACMP3_IN1,ACMP4_IN1",ALT5 +GPIO_AD_B1_07,FLEXSPI_B_DATA0,LPI2C3_SCL,LPUART3_RXD,SPDIF_EXT_CLK,CSI_HSYNC,GPIO1_IO23,USDHC2_DATA3,KPP_COL4,,,"ADC1_IN12,ADC2_IN12",ACMP1_IN5,ALT5 +GPIO_AD_B1_08,FLEXSPI_A_SS1_B,FLEXPWM4_PWM0_A,FLEXCAN1_TX,CCM_PMIC_READY,CSI_DATA09,GPIO1_IO24,USDHC2_CMD,KPP_ROW3,,,"ADC1_IN13,ADC2_IN13",ACMP2_IN5,ALT5 +GPIO_AD_B1_09,FLEXSPI_A_DQS,FLEXPWM4_PWM1_A,FLEXCAN1_RX,SAI1_MCLK,CSI_DATA08,GPIO1_IO25,USDHC2_CLK,KPP_COL3,,,"ADC1_IN14,ADC2_IN14",ACMP3_IN5,ALT5 +GPIO_AD_B1_10,FLEXSPI_A_DATA3,WDOG1_B,LPUART8_TXD,SAI1_RX_SYNC,CSI_DATA07,GPIO1_IO26,USDHC2_WP,KPP_ROW2,,,"ADC1_IN15,ADC2_IN15",ACMP4_IN5,ALT5 +GPIO_AD_B1_11,FLEXSPI_A_DATA2,EWM_OUT_B,LPUART8_RXD,SAI1_RX_BCLK,CSI_DATA06,GPIO1_IO27,USDHC2_RESET_B,KPP_COL2,,,"ADC1_IN0,ADC2_IN0",ACMP1_IN6,ALT5 +GPIO_AD_B1_12,FLEXSPI_A_DATA1,ACMP1_OUT,LPSPI3_PCS0,SAI1_RX_DATA0,CSI_DATA05,GPIO1_IO28,USDHC2_DATA4,KPP_ROW1,,,ADC2_IN1,"ACMP1_OUT,ACMP2_IN6",ALT5 +GPIO_AD_B1_13,FLEXSPI_A_DATA0,ACMP2_OUT,LPSPI3_SIN,SAI1_TX_DATA0,CSI_DATA04,GPIO1_IO29,USDHC2_DATA5,KPP_COL1,,,ADC2_IN2,"ACMP2_OUT,ACMP3_IN6",ALT5 +GPIO_AD_B1_14,FLEXSPI_A_SCLK,ACMP3_OUT,LPSPI3_SOUT,SAI1_TX_BCLK,CSI_DATA03,GPIO1_IO30,USDHC2_DATA6,KPP_ROW0,,,ADC2_IN3,"ACMP3_OUT,ACMP4_IN6",ALT5 +GPIO_AD_B1_15,FLEXSPI_A_SS0_B,ACMP4_OUT,LPSPI3_SCK,SAI1_TX_SYNC,CSI_DATA02,GPIO1_IO31,USDHC2_DATA7,KPP_COL0,,,ADC2_IN4,ACMP4_OUT,ALT5 +GPIO_B0_00,LCD_CLK,TMR1_TIMER0,MQS_RIGHT,LPSPI4_PCS0,FLEXIO2_D00,GPIO2_IO00,SEMC_CSX1,,,,,,ALT5 +GPIO_B0_01,LCD_ENABLE,TMR1_TIMER1,MQS_LEFT,LPSPI4_SIN,FLEXIO2_D01,GPIO2_IO01,SEMC_CSX2,,,,,,ALT5 +GPIO_B0_02,LCD_HSYNC,TMR1_TIMER2,FLEXCAN1_TX,LPSPI4_SOUT,FLEXIO2_D02,GPIO2_IO02,SEMC_CSX3,,,,,,ALT5 +GPIO_B0_03,LCD_VSYNC,TMR2_TIMER0,FLEXCAN1_RX,LPSPI4_SCK,FLEXIO2_D03,GPIO2_IO03,WDOG2_RST_B_DEB,,,,,,ALT5 +GPIO_B0_04,LCD_DATA00,TMR2_TIMER1,LPI2C2_SCL,ARM_TRACE0,FLEXIO2_D04,GPIO2_IO04,SRC_BT_CFG00,,,,,,ALT5 +GPIO_B0_05,LCD_DATA01,TMR2_TIMER2,LPI2C2_SDA,ARM_TRACE1,FLEXIO2_D05,GPIO2_IO05,SRC_BT_CFG01,,,,,,ALT5 +GPIO_B0_06,LCD_DATA02,TMR3_TIMER0,FLEXPWM2_PWM0_A,ARM_TRACE2,FLEXIO2_D06,GPIO2_IO06,SRC_BT_CFG02,,,,,,ALT5 +GPIO_B0_07,LCD_DATA03,TMR3_TIMER1,FLEXPWM2_PWM0_B,ARM_TRACE3,FLEXIO2_D07,GPIO2_IO07,SRC_BT_CFG03,,,,,,ALT5 +GPIO_B0_08,LCD_DATA04,TMR3_TIMER2,FLEXPWM2_PWM1_A,LPUART3_TXD,FLEXIO2_D08,GPIO2_IO08,SRC_BT_CFG04,,,,,,ALT5 +GPIO_B0_09,LCD_DATA05,TMR4_TIMER0,FLEXPWM2_PWM1_B,LPUART3_RXD,FLEXIO2_D09,GPIO2_IO09,SRC_BT_CFG05,,,,,,ALT5 +GPIO_B0_10,LCD_DATA06,TMR4_TIMER1,FLEXPWM2_PWM2_A,"SAI1_TX_DATA3,SAI1_RX_DATA1",FLEXIO2_D10,GPIO2_IO10,SRC_BT_CFG06,,,,,,ALT5 +GPIO_B0_11,LCD_DATA07,TMR4_TIMER2,FLEXPWM2_PWM2_B,"SAI1_TX_DATA2,SAI1_RX_DATA2",FLEXIO2_D11,GPIO2_IO11,SRC_BT_CFG07,,,,,,ALT5 +GPIO_B0_12,LCD_DATA08,XBAR_INOUT10,ARM_TRACE_CLK,"SAI1_TX_DATA1,SAI1_RX_DATA3",FLEXIO2_D12,GPIO2_IO12,SRC_BT_CFG08,,,,,,ALT5 +GPIO_B0_13,LCD_DATA09,XBAR_INOUT11,ARM_TRACE_SWO,SAI1_MCLK,FLEXIO2_D13,GPIO2_IO13,SRC_BT_CFG09,,,,,,ALT5 +GPIO_B0_14,LCD_DATA10,XBAR_INOUT12,ARM_CM7_EVENT0,SAI1_RX_SYNC,FLEXIO2_D14,GPIO2_IO14,SRC_BT_CFG10,,,,,,ALT5 +GPIO_B0_15,LCD_DATA11,XBAR_INOUT13,ARM_CM7_EVENT1,SAI1_RX_BCLK,FLEXIO2_D15,GPIO2_IO15,SRC_BT_CFG11,,,,,,ALT5 +GPIO_B1_00,LCD_DATA12,XBAR_INOUT14,LPUART4_TXD,SAI1_RX_DATA0,FLEXIO2_D16,GPIO2_IO16,FLEXPWM1_PWM3_A,,,,,,ALT5 +GPIO_B1_01,LCD_DATA13,XBAR_INOUT15,LPUART4_RXD,SAI1_TX_DATA0,FLEXIO2_D17,GPIO2_IO17,FLEXPWM1_PWM3_B,,,,,,ALT5 +GPIO_B1_02,LCD_DATA14,XBAR_INOUT16,LPSPI4_PCS2,SAI1_TX_BCLK,FLEXIO2_D18,GPIO2_IO18,FLEXPWM2_PWM3_A,,,,,,ALT5 +GPIO_B1_03,LCD_DATA15,XBAR_INOUT17,LPSPI4_PCS1,SAI1_TX_SYNC,FLEXIO2_D19,GPIO2_IO19,FLEXPWM2_PWM3_B,,,,,,ALT5 +GPIO_B1_04,LCD_DATA16,LPSPI4_PCS0,CSI_DATA15,ENET_RX_DATA0,FLEXIO2_D20,GPIO2_IO20,,,,,,,ALT5 +GPIO_B1_05,LCD_DATA17,LPSPI4_SIN,CSI_DATA14,ENET_RX_DATA1,FLEXIO2_D21,GPIO2_IO21,,,,,,,ALT5 +GPIO_B1_06,LCD_DATA18,LPSPI4_SOUT,CSI_DATA13,ENET_RX_EN,FLEXIO2_D22,GPIO2_IO22,,,,,,,ALT5 +GPIO_B1_07,LCD_DATA19,LPSPI4_SCK,CSI_DATA12,ENET_TX_DATA0,FLEXIO2_D23,GPIO2_IO23,,,,,,,ALT5 +GPIO_B1_08,LCD_DATA20,TMR1_TIMER3,CSI_DATA11,ENET_TX_DATA1,FLEXIO2_D24,GPIO2_IO24,FLEXCAN2_TX,,,,,,ALT5 +GPIO_B1_09,LCD_DATA21,TMR2_TIMER3,CSI_DATA10,ENET_TX_EN,FLEXIO2_D25,GPIO2_IO25,FLEXCAN2_RX,,,,,,ALT5 +GPIO_B1_10,LCD_DATA22,TMR3_TIMER3,CSI_DATA00,ENET_TX_CLK,FLEXIO2_D26,GPIO2_IO26,ENET_REF_CLK,,,,,,ALT5 +GPIO_B1_11,LCD_DATA23,TMR4_TIMER3,CSI_DATA01,ENET_RX_ER,FLEXIO2_D27,GPIO2_IO27,LPSPI4_PCS3,,,,,,ALT5 +GPIO_B1_12,,LPUART5_TXD,CSI_PIXCLK,ENET_1588_EVENT0_IN,FLEXIO2_D28,GPIO2_IO28,USDHC1_CD_B,,,,,,ALT5 +GPIO_B1_13,WDOG1_B,LPUART5_RXD,CSI_VSYNC,ENET_1588_EVENT0_OUT,FLEXIO2_D29,GPIO2_IO29,USDHC1_WP,,,,,,ALT5 +GPIO_B1_14,ENET_MDC,FLEXPWM4_PWM2_A,CSI_HSYNC,XBAR_INOUT02,FLEXIO2_D30,GPIO2_IO30,USDHC1_VSELECT,,,,,,ALT5 +GPIO_B1_15,ENET_MDIO,FLEXPWM4_PWM3_A,CSI_MCLK,XBAR_INOUT03,FLEXIO2_D31,GPIO2_IO31,USDHC1_RESET_B,,,,,,ALT5 +GPIO_EMC_00,SEMC_DATA00,FLEXPWM4_PWM0_A,LPSPI2_SCK,XBAR_INOUT02,FLEXIO1_D00,GPIO4_IO0,USB_PHY1_TSTI_TX_LS_MODE,,,,,,ALT5 +GPIO_EMC_01,SEMC_DATA01,FLEXPWM4_PWM0_B,LPSPI2_PCS0,XBAR_INOUT03,FLEXIO1_D01,GPIO4_IO1,USB_PHY1_TSTI_TX_HS_MODE,,,,,,ALT5 +GPIO_EMC_02,SEMC_DATA02,FLEXPWM4_PWM1_A,LPSPI2_SOUT,XBAR_INOUT04,FLEXIO1_D02,GPIO4_IO2,USB_PHY1_TSTI_TX_DN,,,,,,ALT5 +GPIO_EMC_03,SEMC_DATA03,FLEXPWM4_PWM1_B,LPSPI2_SIN,XBAR_INOUT05,FLEXIO1_D03,GPIO4_IO3,USB_PHY1_TSTO_RX_SQUELCH,,,,,,ALT5 +GPIO_EMC_04,SEMC_DATA04,FLEXPWM4_PWM2_A,SAI2_TX_DATA,XBAR_INOUT06,FLEXIO1_D04,GPIO4_IO4,USB_PHY1_TSTO_RX_DISCON_DET,,,,,,ALT5 +GPIO_EMC_05,SEMC_DATA05,FLEXPWM4_PWM2_B,SAI2_TX_SYNC,XBAR_INOUT07,FLEXIO1_D05,GPIO4_IO5,USB_PHY1_TSTO_RX_HS_RXD,,,,,,ALT5 +GPIO_EMC_06,SEMC_DATA06,FLEXPWM2_PWM0_A,SAI2_TX_BCLK,XBAR_INOUT08,FLEXIO1_D06,GPIO4_IO6,USB_PHY2_TSTO_RX_FS_RXD,,,,,,ALT5 +GPIO_EMC_07,SEMC_DATA07,FLEXPWM2_PWM0_B,SAI2_MCLK,XBAR_INOUT09,FLEXIO1_D07,GPIO4_IO7,USB_PHY1_TSTO_RX_FS_RXD,,,,,,ALT5 +GPIO_EMC_08,SEMC_DM0,FLEXPWM2_PWM1_A,SAI2_RX_DATA,XBAR_INOUT17,FLEXIO1_D08,GPIO4_IO8,USB_PHY1_TSTI_TX_DP,,,,,,ALT5 +GPIO_EMC_09,SEMC_ADDR00,FLEXPWM2_PWM1_B,SAI2_RX_SYNC,FLEXCAN2_TX,FLEXIO1_D09,GPIO4_IO9,USB_PHY1_TSTI_TX_EN,,,,,,ALT5 +GPIO_EMC_10,SEMC_ADDR01,FLEXPWM2_PWM2_A,SAI2_RX_BCLK,FLEXCAN2_RX,FLEXIO1_D10,GPIO4_IO10,USB_PHY1_TSTI_TX_HIZ,,,,,,ALT5 +GPIO_EMC_11,SEMC_ADDR02,FLEXPWM2_PWM2_B,LPI2C4_SDA,USDHC2_RESET_B,FLEXIO1_D11,GPIO4_IO11,USB_PHY2_TSTO_RX_HS_RXD,,,,,,ALT5 +GPIO_EMC_12,SEMC_ADDR03,XBAR_INOUT24,LPI2C4_SCL,USDHC1_WP,FLEXPWM1_PWM3_A,GPIO4_IO12,USB_PHY1_TSTO_PLL_CLK20DIV,,,,,,ALT5 +GPIO_EMC_13,SEMC_ADDR04,XBAR_INOUT25,LPUART3_TXD,MQS_RIGHT,FLEXPWM1_PWM3_B,GPIO4_IO13,USB_PHY2_TSTO_PLL_CLK20DIV,,,,,,ALT5 +GPIO_EMC_14,SEMC_ADDR05,XBAR_INOUT19,LPUART3_RXD,MQS_LEFT,LPSPI2_PCS1,GPIO4_IO14,USB_PHY2_TSTO_RX_SQUELCH,,,,,,ALT5 +GPIO_EMC_15,SEMC_ADDR06,XBAR_INOUT20,LPUART3_CTS_B,SPDIF_OUT,TMR3_TIMER0,GPIO4_IO15,USB_PHY2_TSTO_RX_DISCON_DET,,,,,,ALT5 +GPIO_EMC_16,SEMC_ADDR07,XBAR_INOUT21,LPUART3_RTS_B,SPDIF_IN,TMR3_TIMER1,GPIO4_IO16,,,,,,,ALT5 +GPIO_EMC_17,SEMC_ADDR08,FLEXPWM4_PWM3_A,LPUART4_CTS_B,FLEXCAN1_TX,TMR3_TIMER2,GPIO4_IO17,,,,,,,ALT5 +GPIO_EMC_18,SEMC_ADDR09,FLEXPWM4_PWM3_B,LPUART4_RTS_B,FLEXCAN1_RX,TMR3_TIMER3,GPIO4_IO18,SNVS_VIO_5_CTL,,,,,,ALT5 +GPIO_EMC_19,SEMC_ADDR11,FLEXPWM2_PWM3_A,LPUART4_TXD,ENET_RX_DATA1,TMR2_TIMER0,GPIO4_IO19,SNVS_VIO_5_B,,,,,,ALT5 +GPIO_EMC_20,SEMC_ADDR12,FLEXPWM2_PWM3_B,LPUART4_RXD,ENET_RX_DATA0,TMR2_TIMER1,GPIO4_IO20,,,,,,,ALT5 +GPIO_EMC_21,SEMC_BA0,FLEXPWM3_PWM3_A,LPI2C3_SDA,ENET_TX_DATA1,TMR2_TIMER2,GPIO4_IO21,,,,,,,ALT5 +GPIO_EMC_22,SEMC_BA1,FLEXPWM3_PWM3_B,LPI2C3_SCL,ENET_TX_DATA0,TMR2_TIMER3,GPIO4_IO22,,,,,,,ALT5 +GPIO_EMC_23,SEMC_ADDR10,FLEXPWM1_PWM0_A,LPUART5_TXD,ENET_RX_EN,GPT1_CAPTURE2,GPIO4_IO23,,,,,,,ALT5 +GPIO_EMC_24,SEMC_CAS,FLEXPWM1_PWM0_B,LPUART5_RXD,ENET_TX_EN,GPT1_CAPTURE1,GPIO4_IO24,,,,,,,ALT5 +GPIO_EMC_25,SEMC_RAS,FLEXPWM1_PWM1_A,LPUART6_TXD,ENET_TX_CLK,ENET_REF_CLK,GPIO4_IO25,,,,,,,ALT5 +GPIO_EMC_26,SEMC_CLK,FLEXPWM1_PWM1_B,LPUART6_RXD,ENET_RX_ER,FLEXIO1_D12,GPIO4_IO26,,,,,,,ALT5 +GPIO_EMC_27,SEMC_CKE,FLEXPWM1_PWM2_A,LPUART5_RTS_B,LPSPI1_SCK,FLEXIO1_D13,GPIO4_IO27,,,,,,,ALT5 +GPIO_EMC_28,SEMC_WE,FLEXPWM1_PWM2_B,LPUART5_CTS_B,LPSPI1_SOUT,FLEXIO1_D14,GPIO4_IO28,,,,,,,ALT5 +GPIO_EMC_29,SEMC_CS0,FLEXPWM3_PWM0_A,LPUART6_RTS_B,LPSPI1_SIN,FLEXIO1_D15,GPIO4_IO29,,,,,,,ALT5 +GPIO_EMC_30,SEMC_DATA08,FLEXPWM3_PWM0_B,LPUART6_CTS_B,LPSPI1_PCS0,CSI_DATA23,GPIO4_IO30,,,,,,,ALT5 +GPIO_EMC_31,SEMC_DATA09,FLEXPWM3_PWM1_A,LPUART7_TXD,LPSPI1_PCS1,CSI_DATA22,GPIO4_IO31,,,,,,,ALT5 +GPIO_EMC_32,SEMC_DATA10,FLEXPWM3_PWM1_B,LPUART7_RXD,CCM_PMIC_READY,CSI_DATA21,GPIO3_IO18,,,,,,,ALT5 +GPIO_EMC_33,SEMC_DATA11,FLEXPWM3_PWM2_A,USDHC1_RESET_B,SAI3_RX_DATA,CSI_DATA20,GPIO3_IO19,,,,,,,ALT5 +GPIO_EMC_34,SEMC_DATA12,FLEXPWM3_PWM2_B,USDHC1_VSELECT,SAI3_RX_SYNC,CSI_DATA19,GPIO3_IO20,,,,,,,ALT5 +GPIO_EMC_35,SEMC_DATA13,XBAR_INOUT18,GPT1_COMPARE1,SAI3_RX_BCLK,CSI_DATA18,GPIO3_IO21,USDHC1_CD_B,,,,,,ALT5 +GPIO_EMC_36,SEMC_DATA14,XBAR_INOUT22,GPT1_COMPARE2,SAI3_TX_DATA,CSI_DATA17,GPIO3_IO22,USDHC1_WP,,,,,,ALT5 +GPIO_EMC_37,SEMC_DATA15,XBAR_INOUT23,GPT1_COMPARE3,SAI3_MCLK,CSI_DATA16,GPIO3_IO23,USDHC2_WP,,,,,,ALT5 +GPIO_EMC_38,SEMC_DM1,FLEXPWM1_PWM3_A,LPUART8_TXD,SAI3_TX_BCLK,CSI_FIELD,GPIO3_IO24,USDHC2_VSELECT,,,,,,ALT5 +GPIO_EMC_39,SEMC_DQS,FLEXPWM1_PWM3_B,LPUART8_RXD,SAI3_TX_SYNC,WDOG1_B,GPIO3_IO25,USDHC2_CD_B,,,,,,ALT5 +GPIO_EMC_40,SEMC_RDY,GPT2_CAPTURE2,LPSPI1_PCS2,USB_OTG2_OC,ENET_MDC,GPIO3_IO26,USDHC2_RESET_B,,,,,,ALT5 +GPIO_EMC_41,SEMC_CSX0,GPT2_CAPTURE1,LPSPI1_PCS3,USB_OTG2_PWR,ENET_MDIO,GPIO3_IO27,USDHC1_VSELECT,,,,,,ALT5 +GPIO_SD_B0_00,USDHC1_CMD,FLEXPWM1_PWM0_A,LPI2C3_SCL,XBAR_INOUT04,LPSPI1_SCK,GPIO3_IO12,FLEXSPI_A_SS1_B,,,,,,ALT5 +GPIO_SD_B0_01,USDHC1_CLK,FLEXPWM1_PWM0_B,LPI2C3_SDA,XBAR_INOUT05,LPSPI1_PCS0,GPIO3_IO13,FLEXSPI_B_SS1_B,,,,,,ALT5 +GPIO_SD_B0_02,USDHC1_DATA0,FLEXPWM1_PWM1_A,LPUART8_CTS_B,XBAR_INOUT06,LPSPI1_SOUT,GPIO3_IO14,,,,,,,ALT5 +GPIO_SD_B0_03,USDHC1_DATA1,FLEXPWM1_PWM1_B,LPUART8_RTS_B,XBAR_INOUT07,LPSPI1_SIN,GPIO3_IO15,,,,,,,ALT5 +GPIO_SD_B0_04,USDHC1_DATA2,FLEXPWM1_PWM2_A,LPUART8_TXD,XBAR_INOUT08,FLEXSPI_B_SS0_B,GPIO3_IO16,CCM_CLKO1,,,,,,ALT5 +GPIO_SD_B0_05,USDHC1_DATA3,FLEXPWM1_PWM2_B,LPUART8_RXD,XBAR_INOUT09,FLEXSPI_B_DQS,GPIO3_IO17,CCM_CLKO2,,,,,,ALT5 +GPIO_SD_B1_00,USDHC2_DATA3,FLEXSPI_B_DATA3,FLEXPWM1_PWM3_A,"SAI1_TX_DATA3,SAI1_RX_DATA1",LPUART4_TXD,GPIO3_IO00,,,,,,,ALT5 +GPIO_SD_B1_01,USDHC2_DATA2,FLEXSPI_B_DATA2,FLEXPWM1_PWM3_B,"SAI1_TX_DATA2,SAI1_RX_DATA2",LPUART4_RXD,GPIO3_IO01,,,,,,,ALT5 +GPIO_SD_B1_02,USDHC2_DATA1,FLEXSPI_B_DATA1,FLEXPWM2_PWM3_A,"SAI1_TX_DATA1,SAI1_RX_DATA3",FLEXCAN1_TX,GPIO3_IO02,CCM_WAIT,,,,,,ALT5 +GPIO_SD_B1_03,USDHC2_DATA0,FLEXSPI_B_DATA0,FLEXPWM2_PWM3_B,SAI1_MCLK,FLEXCAN1_RX,GPIO3_IO03,CCM_PMIC_READY,,,,,,ALT5 +GPIO_SD_B1_04,USDHC2_CLK,FLEXSPI_B_SCLK,LPI2C1_SCL,SAI1_RX_SYNC,FLEXSPI_A_SS1_B,GPIO3_IO04,CCM_STOP,,,,,,ALT5 +GPIO_SD_B1_05,USDHC2_CMD,FLEXSPI_A_DQS,LPI2C1_SDA,SAI1_RX_BCLK,FLEXSPI_B_SS0_B,GPIO3_IO05,,,,,,,ALT5 +GPIO_SD_B1_06,USDHC2_RESET_B,FLEXSPI_A_SS0_B,LPUART7_CTS_B,SAI1_RX_DATA0,LPSPI2_PCS0,GPIO3_IO06,,,,,,,ALT5 +GPIO_SD_B1_07,SEMC_CSX1,FLEXSPI_A_SCLK,LPUART7_RTS_B,SAI1_TX_DATA0,LPSPI2_SCK,GPIO3_IO07,CCM_REF_EN_B,,,,,,ALT5 +GPIO_SD_B1_08,USDHC2_DATA4,FLEXSPI_A_DATA0,LPUART7_TXD,SAI1_TX_BCLK,LPSPI2_SOUT,GPIO3_IO08,SEMC_CSX2,,,,,,ALT5 +GPIO_SD_B1_09,USDHC2_DATA5,FLEXSPI_A_DATA1,LPUART7_RXD,SAI1_TX_SYNC,LPSPI2_SIN,GPIO3_IO09,,,,,,,ALT5 +GPIO_SD_B1_10,USDHC2_DATA6,FLEXSPI_A_DATA2,LPUART2_RXD,LPI2C2_SDA,LPSPI2_PCS2,GPIO3_IO10,,,,,,,ALT5 +GPIO_SD_B1_11,USDHC2_DATA7,FLEXSPI_A_DATA3,LPUART2_TXD,LPI2C2_SCL,LPSPI2_PCS3,GPIO3_IO11,,,,,,,ALT5 diff --git a/ports/mimxrt/boards/MIMXRT1060_EVK/mpconfigboard.h b/ports/mimxrt/boards/MIMXRT1060_EVK/mpconfigboard.h index 8bd2a5791..c9e6d8bf2 100644 --- a/ports/mimxrt/boards/MIMXRT1060_EVK/mpconfigboard.h +++ b/ports/mimxrt/boards/MIMXRT1060_EVK/mpconfigboard.h @@ -4,6 +4,6 @@ #define BOARD_FLASH_SIZE (8 * 1024 * 1024) // MIMXRT1060_EVK has 1 user LED -#define MICROPY_HW_LED1_PIN (GPIO_AD_B0_09) +#define MICROPY_HW_LED1_PIN (pin_GPIO_AD_B0_09) #define MICROPY_HW_LED_ON(pin) (mp_hal_pin_low(pin)) #define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_high(pin)) diff --git a/ports/mimxrt/boards/MIMXRT1060_EVK/mpconfigboard.mk b/ports/mimxrt/boards/MIMXRT1060_EVK/mpconfigboard.mk index b34169801..32f87046b 100644 --- a/ports/mimxrt/boards/MIMXRT1060_EVK/mpconfigboard.mk +++ b/ports/mimxrt/boards/MIMXRT1060_EVK/mpconfigboard.mk @@ -2,6 +2,25 @@ MCU_SERIES = MIMXRT1062 MCU_VARIANT = MIMXRT1062DVJ6A JLINK_PATH ?= /media/RT1060-EVK/ +JLINK_COMMANDER_SCRIPT = $(BUILD)/script.jlink + + +ifdef JLINK_IP +JLINK_CONNECTION_SETTINGS = -IP $(JLINK_IP) +else +JLINK_CONNECTION_SETTINGS = -USB +endif + + +deploy_jlink: $(BUILD)/firmware.hex + $(Q)$(TOUCH) $(JLINK_COMMANDER_SCRIPT) + $(ECHO) "ExitOnError 1" > $(JLINK_COMMANDER_SCRIPT) + $(ECHO) "speed auto" >> $(JLINK_COMMANDER_SCRIPT) + $(ECHO) "r" >> $(JLINK_COMMANDER_SCRIPT) + $(ECHO) "st" >> $(JLINK_COMMANDER_SCRIPT) + $(ECHO) "loadfile \"$(realpath $(BUILD)/firmware.hex)\"" >> $(JLINK_COMMANDER_SCRIPT) + $(ECHO) "qc" >> $(JLINK_COMMANDER_SCRIPT) + $(JLINK_PATH)JLinkExe -device $(MCU_VARIANT) -if SWD $(JLINK_CONNECTION_SETTINGS) -CommanderScript $(JLINK_COMMANDER_SCRIPT) deploy: $(BUILD)/firmware.bin cp $< $(JLINK_PATH) diff --git a/ports/mimxrt/boards/MIMXRT1060_EVK/pins.c b/ports/mimxrt/boards/MIMXRT1060_EVK/pins.c deleted file mode 100644 index d5da9c6f9..000000000 --- a/ports/mimxrt/boards/MIMXRT1060_EVK/pins.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the MicroPython project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2020 NXP - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "pin.h" - -static pin_af_obj_t GPIO_AD_B0_09_af[] = { - PIN_AF(GPIO1_IO09, PIN_AF_MODE_ALT5, GPIO1, 0x10B0U), -}; - -pin_obj_t GPIO_AD_B0_09 = PIN(GPIO_AD_B0_09, GPIO1, 9, GPIO_AD_B0_09_af); diff --git a/ports/mimxrt/boards/MIMXRT1060_EVK/pins.csv b/ports/mimxrt/boards/MIMXRT1060_EVK/pins.csv new file mode 100644 index 000000000..afd63d4f9 --- /dev/null +++ b/ports/mimxrt/boards/MIMXRT1060_EVK/pins.csv @@ -0,0 +1,51 @@ +D0,GPIO_AD_B1_07 +D1,GPIO_AD_B1_06 +D2,GPIO_AD_B0_11 +D3,GPIO_AD_B1_08 +D4,GPIO_AD_B0_09 +D5,GPIO_AD_B0_10 +D6,GPIO_AD_B1_02 +D7,GPIO_AD_B1_03 +D8,GPIO_AD_B0_03 +D9,GPIO_AD_B0_02 +D10,GPIO_SD_B0_01 +D11,GPIO_SD_B0_02 +D12,GPIO_SD_B0_03 +D13,GPIO_SD_B0_00 +D14,GPIO_AD_B1_01 +D15,GPIO_AD_B1_00 +A0,GPIO_AD_B1_10 +A1,GPIO_AD_B1_11 +A2,GPIO_AD_B1_04 +A3,GPIO_AD_B1_05 +A4,GPIO_AD_B1_01 +A5,GPIO_AD_B1_00 +RX,GPIO_AD_B1_07 +TX,GPIO_AD_B1_06 +SCL,GPIO_AD_B1_00 +SDA,GPIO_AD_B1_01 +SCK,GPIO_SD_B0_00 +SDI,GPIO_SD_B0_03 +SDO,GPIO_SD_B0_02 +CS,GPIO_SD_B0_01 +LED_GREEN,GPIO_AD_B0_09 +GPIO_AD_B1_07,GPIO_AD_B1_07 +GPIO_AD_B1_06,GPIO_AD_B1_06 +GPIO_AD_B0_11,GPIO_AD_B0_11 +GPIO_AD_B1_08,GPIO_AD_B1_08 +GPIO_AD_B0_09,GPIO_AD_B0_09 +GPIO_AD_B0_10,GPIO_AD_B0_10 +GPIO_AD_B1_02,GPIO_AD_B1_02 +GPIO_AD_B1_03,GPIO_AD_B1_03 +GPIO_AD_B0_03,GPIO_AD_B0_03 +GPIO_AD_B0_02,GPIO_AD_B0_02 +GPIO_SD_B0_01,GPIO_SD_B0_01 +GPIO_SD_B0_02,GPIO_SD_B0_02 +GPIO_SD_B0_03,GPIO_SD_B0_03 +GPIO_SD_B0_00,GPIO_SD_B0_00 +GPIO_AD_B1_01,GPIO_AD_B1_01 +GPIO_AD_B1_00,GPIO_AD_B1_00 +GPIO_AD_B1_10,GPIO_AD_B1_10 +GPIO_AD_B1_11,GPIO_AD_B1_11 +GPIO_AD_B1_04,GPIO_AD_B1_04 +GPIO_AD_B1_05,GPIO_AD_B1_05 diff --git a/ports/mimxrt/boards/MIMXRT1060_EVK/pins.h b/ports/mimxrt/boards/MIMXRT1060_EVK/pins.h deleted file mode 100644 index baef51c6c..000000000 --- a/ports/mimxrt/boards/MIMXRT1060_EVK/pins.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the MicroPython project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2020 NXP - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -// NOTE: pins.h shall only be included in in pin.h -// hence no include guards are needed since they will be provided by pin.h - -extern pin_obj_t GPIO_AD_B0_09; diff --git a/ports/mimxrt/boards/MIMXRT1062_af.csv b/ports/mimxrt/boards/MIMXRT1062_af.csv new file mode 100644 index 000000000..9b83efedd --- /dev/null +++ b/ports/mimxrt/boards/MIMXRT1062_af.csv @@ -0,0 +1,125 @@ +Pad,ALT0, ALT1, ALT2, ALT3, ALT4, ALT5, ALT6, ALT7, ALT8, ALT9,ADC,ACMP,Default +GPIO_AD_B0_00,FLEXPWM2_PWM3_A,XBAR_INOUT14,REF_CLK_32K,USB_OTG2_ID,LPI2C1_SCLS,GPIO1_IO00,USDHC1_RESET_B,LPSPI3_SCK,,,,ACMP1_IN4,ALT5 +GPIO_AD_B0_01,FLEXPWM2_PWM3_B,XBAR_INOUT15,REF_CLK_24M,USB_OTG1_ID,LPI2C1_SDAS,GPIO1_IO01,EWM_OUT_B,LPSPI3_SOUT,,,,ACMP2_IN4,ALT5 +GPIO_AD_B0_02,FLEXCAN2_TX,XBAR_INOUT16,LPUART6_TXD,USB_OTG1_PWR,FLEXPWM1_PWM0_X,GPIO1_IO02,LPI2C1_HREQ,LPSPI3_SIN,,,,ACMP3_IN4,ALT5 +GPIO_AD_B0_03,FLEXCAN2_RX,XBAR_INOUT17,LPUART6_RXD,USB_OTG1_OC,FLEXPWM1_PWM1_X,GPIO1_IO03,REF_CLK_24M,LPSPI3_PCS0,,,,ACMP4_IN4,ALT5 +GPIO_AD_B0_04,SRC_BOOT_MODE0,MQS_RIGHT,ENET_TX_DATA3,SAI2_TX_SYNC,CSI_DATA09,GPIO1_IO04,PIT_TRIGGER0,LPSPI3_PCS1,,,,,ALT0 +GPIO_AD_B0_05,SRC_BOOT_MODE1,MQS_LEFT,ENET_TX_DATA2,SAI2_TX_BCLK,CSI_DATA08,GPIO1_IO05,XBAR_INOUT17,LPSPI3_PCS2,,,,,ALT0 +GPIO_AD_B0_06,"JTAG_TMS,SWD_DIO",GPT2_COMPARE1,ENET_RX_CLK,SAI2_RX_BCLK,CSI_DATA07,GPIO1_IO06,XBAR_INOUT18,LPSPI3_PCS3,,,,,ALT0 +GPIO_AD_B0_07,"JTAG_TCK,SWD_CLK",GPT2_COMPARE2,ENET_TX_ER,SAI2_RX_SYNC,CSI_DATA06,GPIO1_IO07,XBAR_INOUT19,ENET_1588_EVENT3_OUT,,,,,ALT0 +GPIO_AD_B0_08,JTAG_MOD,GPT2_COMPARE3,ENET_RX_DATA3,SAI2_RX_DATA,CSI_DATA05,GPIO1_IO08,XBAR_INOUT20,ENET_1588_EVENT3_IN,,,,,ALT0 +GPIO_AD_B0_09,JTAG_TDI,FLEXPWM2_PWM3_A,ENET_RX_DATA2,SAI2_TX_DATA,CSI_DATA04,GPIO1_IO09,XBAR_INOUT21,GPT2_CLK,,,,,ALT0 +GPIO_AD_B0_10,JTAG_TDO,FLEXPWM1_PWM3_A,ENET_CRS,SAI2_MCLK,CSI_DATA03,GPIO1_IO10,XBAR_INOUT22,ENET_1588_EVENT0_OUT,FLEXCAN3_TX,,,,ALT0 +GPIO_AD_B0_11,JTAG_TRSTB,FLEXPWM1_PWM3_B,ENET_COL,WDOG1_B,CSI_DATA02,GPIO1_IO11,XBAR_INOUT23,ENET_1588_EVENT0_IN,FLEXCAN3_RX,,,,ALT0 +GPIO_AD_B0_12,LPI2C4_SCL,CCM_PMIC_READY,LPUART1_TXD,WDOG2_B,FLEXPWM1_PWM2_X,GPIO1_IO12,ENET_1588_EVENT1_OUT,,,,ADC1_IN1,,ALT5 +GPIO_AD_B0_13,LPI2C4_SDA,GPT1_CLK,LPUART1_RXD,EWM_OUT_B,FLEXPWM1_PWM3_X,GPIO1_IO13,ENET_1588_EVENT1_IN,REF_CLK_24M,,,ADC1_IN2,ACMP1_IN2,ALT5 +GPIO_AD_B0_14,USB_OTG2_OC,XBAR_INOUT24,LPUART1_CTS_B,ENET_1588_EVENT0_OUT,CSI_VSYNC,GPIO1_IO14,FLEXCAN2_TX,WDOG1_ANY,FLEXCAN3_TX,,ADC1_IN3,ACMP2_IN2,ALT5 +GPIO_AD_B0_15,USB_OTG2_PWR,XBAR_INOUT25,LPUART1_RTS_B,ENET_1588_EVENT0_IN,CSI_HSYNC,GPIO1_IO15,FLEXCAN2_RX,WDOG1_RESET_B_DEB,FLEXCAN3_RX,,ADC1_IN4,ACMP3_IN2,ALT5 +GPIO_AD_B1_00,USB_OTG2_ID,TMR3_TIMER0,LPUART2_CTS_B,LPI2C1_SCL,WDOG1_B,GPIO1_IO16,USDHC1_WP,KPP_ROW7,ENET2_1588_EVENT0_OUT,FLEXIO3_D00,"ADC1_IN5,ADC2_IN5",ACMP4_IN2,ALT5 +GPIO_AD_B1_01,USB_OTG1_PWR,TMR3_TIMER1,LPUART2_RTS_B,LPI2C1_SDA,CCM_PMIC_READY,GPIO1_IO17,USDHC1_VSELECT,KPP_COL7,ENET2_1588_EVENT0_IN,FLEXIO3_D01,"ADC1_IN6,ADC2_IN6","ACMP1_IN0,ACMP2_IN0,ACMP3_IN0,ACMP4_IN0",ALT5 +GPIO_AD_B1_02,USB_OTG1_ID,TMR3_TIMER2,LPUART2_TXD,SPDIF_OUT,ENET_1588_EVENT2_OUT,GPIO1_IO18,USDHC1_CD_B,KPP_ROW6,GPT2_CLK,FLEXIO3_D02,"ADC1_IN7,ADC2_IN7",ACMP1_IN3,ALT5 +GPIO_AD_B1_03,USB_OTG1_OC,TMR3_TIMER3,LPUART2_RXD,SPDIF_IN,ENET_1588_EVENT2_IN,GPIO1_IO19,USDHC2_CD_B,KPP_COL6,GPT2_CAPTURE1,FLEXIO3_D03,"ADC1_IN8,ADC2_IN8",ACMP2_IN3,ALT5 +GPIO_AD_B1_04,FLEXSPI_B_DATA3,ENET_MDC,LPUART3_CTS_B,SPDIF_SR_CLK,CSI_PIXCLK,GPIO1_IO20,USDHC2_DATA0,KPP_ROW5,GPT2_CAPTURE2,FLEXIO3_D04,"ADC1_IN9,ADC2_IN9",ACMP3_IN3,ALT5 +GPIO_AD_B1_05,FLEXSPI_B_DATA2,ENET_MDIO,LPUART3_RTS_B,SPDIF_OUT,CSI_MCLK,GPIO1_IO21,USDHC2_DATA1,KPP_COL5,GPT2_COMPARE1,FLEXIO3_D05,"ADC1_IN10,ADC2_IN10",ACMP4_IN3,ALT5 +GPIO_AD_B1_06,FLEXSPI_B_DATA1,LPI2C3_SDA,LPUART3_TXD,SPDIF_LOCK,CSI_VSYNC,GPIO1_IO22,USDHC2_DATA2,KPP_ROW4,GPT2_COMPARE2,FLEXIO3_D06,"ADC1_IN11,ADC2_IN11","ACMP1_IN1,ACMP2_IN1,ACMP3_IN1,ACMP4_IN1",ALT5 +GPIO_AD_B1_07,FLEXSPI_B_DATA0,LPI2C3_SCL,LPUART3_RXD,SPDIF_EXT_CLK,CSI_HSYNC,GPIO1_IO23,USDHC2_DATA3,KPP_COL4,GPT2_COMPARE3,FLEXIO3_D07,"ADC1_IN12,ADC2_IN12",ACMP1_IN5,ALT5 +GPIO_AD_B1_08,FLEXSPI_A_SS1_B,FLEXPWM4_PWM0_A,FLEXCAN1_TX,CCM_PMIC_READY,CSI_DATA09,GPIO1_IO24,USDHC2_CMD,KPP_ROW3,,FLEXIO3_D08,"ADC1_IN13,ADC2_IN13",ACMP2_IN5,ALT5 +GPIO_AD_B1_09,FLEXSPI_A_DQS,FLEXPWM4_PWM1_A,FLEXCAN1_RX,SAI1_MCLK,CSI_DATA08,GPIO1_IO25,USDHC2_CLK,KPP_COL3,,FLEXIO3_D09,"ADC1_IN14,ADC2_IN14",ACMP3_IN5,ALT5 +GPIO_AD_B1_10,FLEXSPI_A_DATA3,WDOG1_B,LPUART8_TXD,SAI1_RX_SYNC,CSI_DATA07,GPIO1_IO26,USDHC2_WP,KPP_ROW2,ENET2_1588_EVENT1_OUT,FLEXIO3_D10,"ADC1_IN15,ADC2_IN15",ACMP4_IN5,ALT5 +GPIO_AD_B1_11,FLEXSPI_A_DATA2,EWM_OUT_B,LPUART8_RXD,SAI1_RX_BCLK,CSI_DATA06,GPIO1_IO27,USDHC2_RESET_B,KPP_COL2,ENET2_1588_EVENT1_IN,FLEXIO3_D11,ADC2_IN0,ACMP1_IN6,ALT5 +GPIO_AD_B1_12,FLEXSPI_A_DATA1,ACMP_OUT00,LPSPI3_PCS0,SAI1_RX_DATA0,CSI_DATA05,GPIO1_IO28,USDHC2_DATA4,KPP_ROW1,ENET2_1588_EVENT2_OUT,FLEXIO3_D12,ADC2_IN1,"ACMP1_OUT,ACMP2_IN6",ALT5 +GPIO_AD_B1_13,FLEXSPI_A_DATA0,ACMP_OUT01,LPSPI3_SIN,SAI1_TX_DATA0,CSI_DATA04,GPIO1_IO29,USDHC2_DATA5,KPP_COL1,ENET2_1588_EVENT2_IN,FLEXIO3_D13,ADC2_IN2,"ACMP2_OUT,ACMP3_IN6",ALT5 +GPIO_AD_B1_14,FLEXSPI_A_SCLK,ACMP_OUT02,LPSPI3_SOUT,SAI1_TX_BCLK,CSI_DATA03,GPIO1_IO30,USDHC2_DATA6,KPP_ROW0,ENET2_1588_EVENT3_OUT,FLEXIO3_D14,ADC2_IN3,"ACMP3_OUT,ACMP4_IN6",ALT5 +GPIO_AD_B1_15,FLEXSPI_A_SS0_B,ACMP_OUT03,LPSPI3_SCK,SAI1_TX_SYNC,CSI_DATA02,GPIO1_IO31,USDHC2_DATA7,KPP_COL0,ENET2_1588_EVENT3_IN,FLEXIO3_D15,ADC2_IN4,ACMP4_OUT,ALT5 +GPIO_B0_00,LCD_CLK,TMR1_TIMER0,MQS_RIGHT,LPSPI4_PCS0,FLEXIO2_D00,GPIO2_IO00,SEMC_CSX1,,ENET2_MDC,,,,ALT5 +GPIO_B0_01,LCD_ENABLE,TMR1_TIMER1,MQS_LEFT,LPSPI4_SIN,FLEXIO2_D01,GPIO2_IO01,SEMC_CSX2,,ENET2_MDIO,,,,ALT5 +GPIO_B0_02,LCD_HSYNC,TMR1_TIMER2,FLEXCAN1_TX,LPSPI4_SOUT,FLEXIO2_D02,GPIO2_IO02,SEMC_CSX3,,ENET2_1588_EVENT0_OUT,,,,ALT5 +GPIO_B0_03,LCD_VSYNC,TMR2_TIMER0,FLEXCAN1_RX,LPSPI4_SCK,FLEXIO2_D03,GPIO2_IO03,WDOG2_RESET_B_DEB,,ENET2_1588_EVENT0_IN,,,,ALT5 +GPIO_B0_04,LCD_DATA00,TMR2_TIMER1,LPI2C2_SCL,ARM_TRACE0,FLEXIO2_D04,GPIO2_IO04,SRC_BT_CFG00,,ENET2_TDATA3,,,,ALT5 +GPIO_B0_05,LCD_DATA01,TMR2_TIMER2,LPI2C2_SDA,ARM_TRACE1,FLEXIO2_D05,GPIO2_IO05,SRC_BT_CFG01,,ENET2_TDATA2,,,,ALT5 +GPIO_B0_06,LCD_DATA02,TMR3_TIMER0,FLEXPWM2_PWM0_A,ARM_TRACE2,FLEXIO2_D06,GPIO2_IO06,SRC_BT_CFG02,,ENET2_RX_CLK,,,,ALT5 +GPIO_B0_07,LCD_DATA03,TMR3_TIMER1,FLEXPWM2_PWM0_B,ARM_TRACE3,FLEXIO2_D07,GPIO2_IO07,SRC_BT_CFG03,,ENET2_TX_ER,,,,ALT5 +GPIO_B0_08,LCD_DATA04,TMR3_TIMER2,FLEXPWM2_PWM1_A,LPUART3_TXD,FLEXIO2_D08,GPIO2_IO08,SRC_BT_CFG04,,ENET2_RDATA3,,,,ALT5 +GPIO_B0_09,LCD_DATA05,TMR4_TIMER0,FLEXPWM2_PWM1_B,LPUART3_RXD,FLEXIO2_D09,GPIO2_IO09,SRC_BT_CFG05,,ENET2_RDATA2,,,,ALT5 +GPIO_B0_10,LCD_DATA06,TMR4_TIMER1,FLEXPWM2_PWM2_A,"SAI1_TX_DATA3,SAI1_RX_DATA1",FLEXIO2_D10,GPIO2_IO10,SRC_BT_CFG06,,ENET2_CRS,,,,ALT5 +GPIO_B0_11,LCD_DATA07,TMR4_TIMER2,FLEXPWM2_PWM2_B,"SAI1_TX_DATA2,SAI1_RX_DATA2",FLEXIO2_D11,GPIO2_IO11,SRC_BT_CFG07,,ENET2_COL,,,,ALT5 +GPIO_B0_12,LCD_DATA08,XBAR_INOUT10,ARM_TRACE_CLK,"SAI1_TX_DATA1,SAI1_RX_DATA3",FLEXIO2_D12,GPIO2_IO12,SRC_BT_CFG08,,ENET2_TDATA0,,,,ALT5 +GPIO_B0_13,LCD_DATA09,XBAR_INOUT11,ARM_TRACE_SWO,SAI1_MCLK,FLEXIO2_D13,GPIO2_IO13,SRC_BT_CFG09,,ENET2_TDATA1,,,,ALT5 +GPIO_B0_14,LCD_DATA10,XBAR_INOUT12,ARM_TXEV,SAI1_RX_SYNC,FLEXIO2_D14,GPIO2_IO14,SRC_BT_CFG10,,ENET2_TX_EN,,,,ALT5 +GPIO_B0_15,LCD_DATA11,XBAR_INOUT13,ARM_EVENT1,SAI1_RX_DATA0,FLEXIO2_D15,GPIO2_IO15,SRC_BT_CFG11,,ENET2_TX_CLK,ENET2_REF_CLK2,,,ALT5 +GPIO_B1_00,LCD_DATA12,XBAR_INOUT14,LPUART4_TXD,SAI1_RX_DATA0,FLEXIO2_D16,GPIO2_IO16,FLEXPWM1_PWM3_A,,ENET2_RX_ER,FLEXIO3_D16,,,ALT5 +GPIO_B1_01,LCD_DATA13,XBAR_INOUT15,LPUART4_RXD,SAI1_TX_DATA0,FLEXIO2_D17,GPIO2_IO17,FLEXPWM1_PWM3_B,,ENET2_RDATA0,FLEXIO3_D17,,,ALT5 +GPIO_B1_02,LCD_DATA14,XBAR_INOUT16,LPSPI4_PCS2,SAI1_TX_BCLK,FLEXIO2_D18,GPIO2_IO18,FLEXPWM2_PWM3_A,,ENET2_RDATA1,FLEXIO3_D18,,,ALT5 +GPIO_B1_03,LCD_DATA15,XBAR_INOUT17,LPSPI4_PCS1,SAI1_TX_SYNC,FLEXIO2_D19,GPIO2_IO19,FLEXPWM2_PWM3_B,,ENET2_RX_EN,FLEXIO3_D19,,,ALT5 +GPIO_B1_04,LCD_DATA16,LPSPI4_PCS0,CSI_DATA15,ENET_RX_DATA0,FLEXIO2_D20,GPIO2_IO20,,,GPT1_CLK,FLEXIO3_D20,,,ALT5 +GPIO_B1_05,LCD_DATA17,LPSPI4_SIN,CSI_DATA14,ENET_RX_DATA1,FLEXIO2_D21,GPIO2_IO21,,,GPT1_CAPTURE1,FLEXIO3_D21,,,ALT5 +GPIO_B1_06,LCD_DATA18,LPSPI4_SOUT,CSI_DATA13,ENET_RX_EN,FLEXIO2_D22,GPIO2_IO22,,,GPT1_CAPTURE2,FLEXIO3_D22,,,ALT5 +GPIO_B1_07,LCD_DATA19,LPSPI4_SCK,CSI_DATA12,ENET_TX_DATA0,FLEXIO2_D23,GPIO2_IO23,,,GPT1_COMPARE1,FLEXIO3_D23,,,ALT5 +GPIO_B1_08,LCD_DATA20,TMR1_TIMER3,CSI_DATA11,ENET_TX_DATA1,FLEXIO2_D24,GPIO2_IO24,FLEXCAN2_TX,,GPT1_COMPARE2,FLEXIO3_D24,,,ALT5 +GPIO_B1_09,LCD_DATA21,TMR2_TIMER3,CSI_DATA10,ENET_TX_EN,FLEXIO2_D25,GPIO2_IO25,FLEXCAN2_RX,,GPT1_COMPARE3,FLEXIO3_D25,,,ALT5 +GPIO_B1_10,LCD_DATA22,TMR3_TIMER3,CSI_DATA00,ENET_TX_CLK,FLEXIO2_D26,GPIO2_IO26,ENET_REF_CLK,,,FLEXIO3_D26,,,ALT5 +GPIO_B1_11,LCD_DATA23,TMR4_TIMER3,CSI_DATA01,ENET_RX_ER,FLEXIO2_D27,GPIO2_IO27,LPSPI4_PCS3,,,FLEXIO3_D27,,,ALT5 +GPIO_B1_12,,LPUART5_TXD,CSI_PIXCLK,ENET_1588_EVENT0_IN,FLEXIO2_D28,GPIO2_IO28,USDHC1_CD_B,,,FLEXIO3_D28,,,ALT5 +GPIO_B1_13,WDOG1_B,LPUART5_RXD,CSI_VSYNC,ENET_1588_EVENT0_OUT,FLEXIO2_D29,GPIO2_IO29,USDHC1_WP,,SEMC_DQS4,FLEXIO3_D29,,,ALT5 +GPIO_B1_14,ENET_MDC,FLEXPWM4_PWM2_A,CSI_HSYNC,XBAR_INOUT02,FLEXIO2_D30,GPIO2_IO30,USDHC1_VSELECT,,ENET2_TDATA0,FLEXIO3_D30,,,ALT5 +GPIO_B1_15,ENET_MDIO,FLEXPWM4_PWM3_A,CSI_MCLK,XBAR_INOUT03,FLEXIO2_D31,GPIO2_IO31,USDHC1_RESET_B,,ENET2_TDATA1,FLEXIO3_D31,,,ALT5 +GPIO_EMC_00,SEMC_DATA00,FLEXPWM4_PWM0_A,LPSPI2_SCK,XBAR_INOUT02,FLEXIO1_D00,GPIO4_IO0,USB_PHY1_TSTI_TX_LS_MODE,,,,,,ALT5 +GPIO_EMC_01,SEMC_DATA01,FLEXPWM4_PWM0_B,LPSPI2_PCS0,XBAR_INOUT03,FLEXIO1_D01,GPIO4_IO1,USB_PHY1_TSTI_TX_HS_MODE,JTAG_DE_B,,,,,ALT5 +GPIO_EMC_02,SEMC_DATA02,FLEXPWM4_PWM1_A,LPSPI2_SOUT,XBAR_INOUT04,FLEXIO1_D02,GPIO4_IO2,USB_PHY1_TSTI_TX_DN,,,,,,ALT5 +GPIO_EMC_03,SEMC_DATA03,FLEXPWM4_PWM1_B,LPSPI2_SIN,XBAR_INOUT05,FLEXIO1_D03,GPIO4_IO3,USB_PHY1_TSTO_RX_SQUELCH,,,,,,ALT5 +GPIO_EMC_04,SEMC_DATA04,FLEXPWM4_PWM2_A,SAI2_TX_DATA,XBAR_INOUT06,FLEXIO1_D04,GPIO4_IO4,USB_PHY1_TSTO_RX_DISCON_DET,,,,,,ALT5 +GPIO_EMC_05,SEMC_DATA05,FLEXPWM4_PWM2_B,SAI2_TX_SYNC,XBAR_INOUT07,FLEXIO1_D05,GPIO4_IO5,USB_PHY1_TSTO_RX_HS_RXD,,,,,,ALT5 +GPIO_EMC_06,SEMC_DATA06,FLEXPWM2_PWM0_A,SAI2_TX_BCLK,XBAR_INOUT08,FLEXIO1_D06,GPIO4_IO6,USB_PHY2_TSTO_RX_FS_RXD,,,,,,ALT5 +GPIO_EMC_07,SEMC_DATA07,FLEXPWM2_PWM0_B,SAI2_MCLK,XBAR_INOUT09,FLEXIO1_D07,GPIO4_IO7,USB_PHY1_TSTO_RX_HS_RXD,,,,,,ALT5 +GPIO_EMC_08,SEMC_DM0,FLEXPWM2_PWM1_A,SAI2_RX_DATA,XBAR_INOUT17,FLEXIO1_D08,GPIO4_IO8,USB_PHY1_TSTI_TX_DP,,,,,,ALT5 +GPIO_EMC_09,SEMC_ADDR00,FLEXPWM2_PWM1_B,SAI2_RX_SYNC,FLEXCAN2_TX,FLEXIO1_D09,GPIO4_IO9,USB_PHY1_TSTI_TX_EN,,FLEXSPI2_B_SS1_B,,,,ALT5 +GPIO_EMC_10,SEMC_ADDR01,FLEXPWM2_PWM2_A,SAI2_RX_BCLK,FLEXCAN2_RX,FLEXIO1_D10,GPIO4_IO10,USB_PHY1_TSTI_TX_HIZ,,FLEXSPI2_B_SS0_B,,,,ALT5 +GPIO_EMC_11,SEMC_ADDR02,FLEXPWM2_PWM2_B,LPI2C4_SDA,USDHC2_RESET_B,FLEXIO1_D11,GPIO4_IO11,USB_PHY2_TSTO_RX_FS_RXD,,FLEXSPI2_B_DQS,,,,ALT5 +GPIO_EMC_12,SEMC_ADDR03,XBAR_INOUT24,LPI2C4_SCL,USDHC1_WP,FLEXPWM1_PWM3_A,GPIO4_IO12,USB_PHY1_TSTO_PLL_CLK20DIV,,FLEXSPI2_B_SCLK,,,,ALT5 +GPIO_EMC_13,SEMC_ADDR04,XBAR_INOUT25,LPUART3_TXD,MQS_RIGHT,FLEXPWM1_PWM3_B,GPIO4_IO13,USB_PHY2_TSTO_RX_FS_20DIV,,FLEXSPI2_B_DATA0,,,,ALT5 +GPIO_EMC_14,SEMC_ADDR05,XBAR_INOUT19,LPUART3_RXD,MQS_LEFT,LPSPI2_PCS1,GPIO4_IO14,USB_PHY2_TSTO_RX_FS_ELCH,,FLEXSPI2_B_DATA1,,,,ALT5 +GPIO_EMC_15,SEMC_ADDR06,XBAR_INOUT20,LPUART3_CTS_B,SPDIF_OUT,TMR3_TIMER0,GPIO4_IO15,USB_PHY2_TSTO_RX_FS_ON_DET,,FLEXSPI2_B_DATA2,,,,ALT5 +GPIO_EMC_16,SEMC_ADDR07,XBAR_INOUT21,LPUART3_RTS_B,SPDIF_IN,TMR3_TIMER1,GPIO4_IO16,,,FLEXSPI2_B_DATA3,,,,ALT5 +GPIO_EMC_17,SEMC_ADDR08,FLEXPWM4_PWM3_A,LPUART4_CTS_B,FLEXCAN1_TX,TMR3_TIMER2,GPIO4_IO17,,,,,,,ALT5 +GPIO_EMC_18,SEMC_ADDR09,FLEXPWM4_PWM3_B,LPUART4_RTS_B,FLEXCAN1_RX,TMR3_TIMER3,GPIO4_IO18,SNVS_VIO_5_CTL,,,,,,ALT5 +GPIO_EMC_19,SEMC_ADDR11,FLEXPWM2_PWM3_A,LPUART4_TXD,ENET_RX_DATA1,TMR2_TIMER0,GPIO4_IO19,SNVS_VIO_5_B,,,,,,ALT5 +GPIO_EMC_20,SEMC_ADDR12,FLEXPWM2_PWM3_B,LPUART4_RXD,ENET_RX_DATA0,TMR2_TIMER1,GPIO4_IO20,,,,,,,ALT5 +GPIO_EMC_21,SEMC_BA0,FLEXPWM3_PWM3_A,LPI2C3_SDA,ENET_TX_DATA1,TMR2_TIMER2,GPIO4_IO21,,,,,,,ALT5 +GPIO_EMC_22,SEMC_BA1,FLEXPWM3_PWM3_B,LPI2C3_SCL,ENET_TX_DATA0,TMR2_TIMER3,GPIO4_IO22,,,FLEXSPI2_A_SS1_B,,,,ALT5 +GPIO_EMC_23,SEMC_ADDR10,FLEXPWM1_PWM0_A,LPUART5_TXD,ENET_RX_EN,GPT1_CAPTURE2,GPIO4_IO23,,,FLEXSPI2_A_DQS,,,,ALT5 +GPIO_EMC_24,SEMC_CAS,FLEXPWM1_PWM0_B,LPUART5_RXD,ENET_TX_EN,GPT1_CAPTURE1,GPIO4_IO24,,,FLEXSPI2_A_SS0_B,,,,ALT5 +GPIO_EMC_25,SEMC_RAS,FLEXPWM1_PWM1_A,LPUART6_TXD,ENET_TX_CLK,ENET_REF_CLK,GPIO4_IO25,,,FLEXSPI2_A_SCLK,,,,ALT5 +GPIO_EMC_26,SEMC_CLK,FLEXPWM1_PWM1_B,LPUART6_RXD,ENET_RX_ER,FLEXIO1_D12,GPIO4_IO26,,,FLEXSPI2_A_DATA0,,,,ALT5 +GPIO_EMC_27,SEMC_CKE,FLEXPWM1_PWM2_A,LPUART5_RTS_B,LPSPI1_SCK,FLEXIO1_D13,GPIO4_IO27,,,FLEXSPI2_A_DATA1,,,,ALT5 +GPIO_EMC_28,SEMC_WE,FLEXPWM1_PWM2_B,LPUART5_CTS_B,LPSPI1_SOUT,FLEXIO1_D14,GPIO4_IO28,,,FLEXSPI2_A_DATA2,,,,ALT5 +GPIO_EMC_29,SEMC_CS0,FLEXPWM3_PWM0_A,LPUART6_RTS_B,LPSPI1_SIN,FLEXIO1_D15,GPIO4_IO29,,,FLEXSPI2_A_DATA3,,,,ALT5 +GPIO_EMC_30,SEMC_DATA08,FLEXPWM3_PWM0_B,LPUART6_CTS_B,LPSPI1_PCS0,CSI_DATA23,GPIO4_IO30,,,ENET2_TDATA0,,,,ALT5 +GPIO_EMC_31,SEMC_DATA09,FLEXPWM3_PWM1_A,LPUART7_TXD,LPSPI1_PCS1,CSI_DATA22,GPIO4_IO31,,,ENET2_TDATA1,,,,ALT5 +GPIO_EMC_32,SEMC_DATA10,FLEXPWM3_PWM1_B,LPUART7_RXD,CCM_PMIC_READY,CSI_DATA21,GPIO3_IO18,,,ENET2_TX_EN,,,,ALT5 +GPIO_EMC_33,SEMC_DATA11,FLEXPWM3_PWM2_A,USDHC1_RESET_B,SAI3_RX_DATA,CSI_DATA20,GPIO3_IO19,,,ENET2_TX_CLK,ENET2_REF_CLK2,,,ALT5 +GPIO_EMC_34,SEMC_DATA12,FLEXPWM3_PWM2_B,USDHC1_VSELECT,SAI3_RX_SYNC,CSI_DATA19,GPIO3_IO20,,,ENET2_RX_ER,,,,ALT5 +GPIO_EMC_35,SEMC_DATA13,XBAR_INOUT18,GPT1_COMPARE1,SAI3_RX_BCLK,CSI_DATA18,GPIO3_IO21,USDHC1_CD_B,,ENET2_RDATA0,,,,ALT5 +GPIO_EMC_36,SEMC_DATA14,XBAR_INOUT22,GPT1_COMPARE2,SAI3_TX_DATA,CSI_DATA17,GPIO3_IO22,USDHC1_WP,,ENET2_RDATA1,FLEXCAN3_TX,,,ALT5 +GPIO_EMC_37,SEMC_DATA15,XBAR_INOUT23,GPT1_COMPARE3,SAI3_MCLK,CSI_DATA16,GPIO3_IO23,USDHC2_WP,,ENET2_RX_EN,FLEXCAN3_RX,,,ALT5 +GPIO_EMC_38,SEMC_DM1,FLEXPWM1_PWM3_A,LPUART8_TXD,SAI3_TX_BCLK,CSI_FIELD,GPIO3_IO24,USDHC2_VSELECT,,ENET2_MDC,,,,ALT5 +GPIO_EMC_39,SEMC_DQS,FLEXPWM1_PWM3_B,LPUART8_RXD,SAI3_TX_SYNC,WDOG1_B,GPIO3_IO25,USDHC2_CD_B,,ENET2_MDIO,,,,ALT5 +GPIO_EMC_40,SEMC_RDY,GPT2_CAPTURE2,LPSPI1_PCS2,USB_OTG2_OC,ENET_MDC,GPIO3_IO26,USDHC2_RESET_B,,,,,,ALT5 +GPIO_EMC_41,SEMC_CSX0,GPT2_CAPTURE1,LPSPI1_PCS3,USB_OTG2_PWR,ENET_MDIO,GPIO3_IO27,USDHC1_VSELECT,,,,,,ALT5 +GPIO_SD_B0_00,USDHC1_CMD,FLEXPWM1_PWM0_A,LPI2C3_SCL,XBAR_INOUT04,LPSPI1_SCK,GPIO3_IO12,FLEXSPI_A_SS1_B,,ENET2_TX_EN,,,,ALT5 +GPIO_SD_B0_01,USDHC1_CLK,FLEXPWM1_PWM0_B,LPI2C3_SDA,XBAR_INOUT05,LPSPI1_PCS0,GPIO3_IO13,FLEXSPI_B_SS1_B,,ENET2_TX_CLK,ENET2_REF_CLK2,,,ALT5 +GPIO_SD_B0_02,USDHC1_DATA0,FLEXPWM1_PWM1_A,LPUART8_CTS_B,XBAR_INOUT06,LPSPI1_SOUT,GPIO3_IO14,,,ENET2_RX_ER,,,,ALT5 +GPIO_SD_B0_03,USDHC1_DATA1,FLEXPWM1_PWM1_B,LPUART8_RTS_B,XBAR_INOUT07,LPSPI1_SIN,GPIO3_IO15,,,ENET2_RDATA0,,,,ALT5 +GPIO_SD_B0_04,USDHC1_DATA2,FLEXPWM1_PWM2_A,LPUART8_TXD,XBAR_INOUT08,FLEXSPI_B_SS0_B,GPIO3_IO16,CCM_CLKO1,,ENET2_RDATA1,,,,ALT5 +GPIO_SD_B0_05,USDHC1_DATA3,FLEXPWM1_PWM2_B,LPUART8_RXD,XBAR_INOUT09,FLEXSPI_B_DQS,GPIO3_IO17,CCM_CLKO2,,ENET2_RX_EN,,,,ALT5 +GPIO_SD_B1_00,USDHC2_DATA3,FLEXSPI_B_DATA3,FLEXPWM1_PWM3_A,"SAI1_TX_DATA3,SAI1_RX_DATA1",LPUART4_TXD,GPIO3_IO00,,,SAI3_RX_DATA,,,,ALT5 +GPIO_SD_B1_01,USDHC2_DATA2,FLEXSPI_B_DATA2,FLEXPWM1_PWM3_B,"SAI1_TX_DATA2,SAI1_RX_DATA2",LPUART4_RXD,GPIO3_IO01,,,SAI3_TX_DATA,,,,ALT5 +GPIO_SD_B1_02,USDHC2_DATA1,FLEXSPI_B_DATA1,FLEXPWM2_PWM3_A,"SAI1_TX_DATA1,SAI1_RX_DATA3",FLEXCAN1_TX,GPIO3_IO02,CCM_WAIT,,SAI3_TX_SYNC,,,,ALT5 +GPIO_SD_B1_03,USDHC2_DATA0,FLEXSPI_B_DATA0,FLEXPWM2_PWM3_B,SAI1_MCLK,FLEXCAN1_RX,GPIO3_IO03,CCM_PMIC_READY,,SAI3_TX_BCLK,,,,ALT5 +GPIO_SD_B1_04,USDHC2_CLK,FLEXSPI_B_SCLK,LPI2C1_SCL,SAI1_RX_SYNC,FLEXSPI_A_SS1_B,GPIO3_IO04,CCM_STOP,,SAI3_MCLK,,,,ALT5 +GPIO_SD_B1_05,USDHC2_CMD,FLEXSPI_A_DQS,LPI2C1_SDA,SAI1_RX_BCLK,FLEXSPI_B_SS0_B,GPIO3_IO05,,,SAI3_RX_SYNC,,,,ALT5 +GPIO_SD_B1_06,USDHC2_RESET_B,FLEXSPI_A_SS0_B,LPUART7_CTS_B,SAI1_RX_DATA0,LPSPI2_PCS0,GPIO3_IO06,,,SAI3_RX_BCLK,,,,ALT5 +GPIO_SD_B1_07,SEMC_CSX1,FLEXSPI_A_SCLK,LPUART7_RTS_B,SAI1_TX_DATA0,LPSPI2_SCK,GPIO3_IO07,,,,,,,ALT5 +GPIO_SD_B1_08,USDHC2_DATA4,FLEXSPI_A_DATA0,LPUART7_TXD,SAI1_TX_BCLK,LPSPI2_SOUT,GPIO3_IO08,SEMC_CSX2,,,,,,ALT5 +GPIO_SD_B1_09,USDHC2_DATA5,FLEXSPI_A_DATA1,LPUART7_RXD,SAI1_TX_SYNC,LPSPI2_SIN,GPIO3_IO09,,,,,,,ALT5 +GPIO_SD_B1_10,USDHC2_DATA6,FLEXSPI_A_DATA2,LPUART2_RXD,LPI2C2_SDA,LPSPI2_PCS2,GPIO3_IO10,,,,,,,ALT5 +GPIO_SD_B1_11,USDHC2_DATA7,FLEXSPI_A_DATA3,LPUART2_TXD,LPI2C2_SCL,LPSPI2_PCS3,GPIO3_IO11,,,,,,,ALT5 diff --git a/ports/mimxrt/boards/MIMXRT1064_EVK/mpconfigboard.h b/ports/mimxrt/boards/MIMXRT1064_EVK/mpconfigboard.h index e05c8824d..3eddb4102 100644 --- a/ports/mimxrt/boards/MIMXRT1064_EVK/mpconfigboard.h +++ b/ports/mimxrt/boards/MIMXRT1064_EVK/mpconfigboard.h @@ -3,6 +3,6 @@ // MIMXRT1064_EVK has 1 user LED -#define MICROPY_HW_LED1_PIN (GPIO_AD_B0_09) +#define MICROPY_HW_LED1_PIN (pin_GPIO_AD_B0_09) #define MICROPY_HW_LED_ON(pin) (mp_hal_pin_low(pin)) #define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_high(pin)) diff --git a/ports/mimxrt/boards/MIMXRT1064_EVK/pins.c b/ports/mimxrt/boards/MIMXRT1064_EVK/pins.c deleted file mode 100644 index d5da9c6f9..000000000 --- a/ports/mimxrt/boards/MIMXRT1064_EVK/pins.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the MicroPython project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2020 NXP - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "pin.h" - -static pin_af_obj_t GPIO_AD_B0_09_af[] = { - PIN_AF(GPIO1_IO09, PIN_AF_MODE_ALT5, GPIO1, 0x10B0U), -}; - -pin_obj_t GPIO_AD_B0_09 = PIN(GPIO_AD_B0_09, GPIO1, 9, GPIO_AD_B0_09_af); diff --git a/ports/mimxrt/boards/MIMXRT1064_EVK/pins.csv b/ports/mimxrt/boards/MIMXRT1064_EVK/pins.csv new file mode 100644 index 000000000..afd63d4f9 --- /dev/null +++ b/ports/mimxrt/boards/MIMXRT1064_EVK/pins.csv @@ -0,0 +1,51 @@ +D0,GPIO_AD_B1_07 +D1,GPIO_AD_B1_06 +D2,GPIO_AD_B0_11 +D3,GPIO_AD_B1_08 +D4,GPIO_AD_B0_09 +D5,GPIO_AD_B0_10 +D6,GPIO_AD_B1_02 +D7,GPIO_AD_B1_03 +D8,GPIO_AD_B0_03 +D9,GPIO_AD_B0_02 +D10,GPIO_SD_B0_01 +D11,GPIO_SD_B0_02 +D12,GPIO_SD_B0_03 +D13,GPIO_SD_B0_00 +D14,GPIO_AD_B1_01 +D15,GPIO_AD_B1_00 +A0,GPIO_AD_B1_10 +A1,GPIO_AD_B1_11 +A2,GPIO_AD_B1_04 +A3,GPIO_AD_B1_05 +A4,GPIO_AD_B1_01 +A5,GPIO_AD_B1_00 +RX,GPIO_AD_B1_07 +TX,GPIO_AD_B1_06 +SCL,GPIO_AD_B1_00 +SDA,GPIO_AD_B1_01 +SCK,GPIO_SD_B0_00 +SDI,GPIO_SD_B0_03 +SDO,GPIO_SD_B0_02 +CS,GPIO_SD_B0_01 +LED_GREEN,GPIO_AD_B0_09 +GPIO_AD_B1_07,GPIO_AD_B1_07 +GPIO_AD_B1_06,GPIO_AD_B1_06 +GPIO_AD_B0_11,GPIO_AD_B0_11 +GPIO_AD_B1_08,GPIO_AD_B1_08 +GPIO_AD_B0_09,GPIO_AD_B0_09 +GPIO_AD_B0_10,GPIO_AD_B0_10 +GPIO_AD_B1_02,GPIO_AD_B1_02 +GPIO_AD_B1_03,GPIO_AD_B1_03 +GPIO_AD_B0_03,GPIO_AD_B0_03 +GPIO_AD_B0_02,GPIO_AD_B0_02 +GPIO_SD_B0_01,GPIO_SD_B0_01 +GPIO_SD_B0_02,GPIO_SD_B0_02 +GPIO_SD_B0_03,GPIO_SD_B0_03 +GPIO_SD_B0_00,GPIO_SD_B0_00 +GPIO_AD_B1_01,GPIO_AD_B1_01 +GPIO_AD_B1_00,GPIO_AD_B1_00 +GPIO_AD_B1_10,GPIO_AD_B1_10 +GPIO_AD_B1_11,GPIO_AD_B1_11 +GPIO_AD_B1_04,GPIO_AD_B1_04 +GPIO_AD_B1_05,GPIO_AD_B1_05 diff --git a/ports/mimxrt/boards/MIMXRT1064_EVK/pins.h b/ports/mimxrt/boards/MIMXRT1064_EVK/pins.h deleted file mode 100644 index baef51c6c..000000000 --- a/ports/mimxrt/boards/MIMXRT1064_EVK/pins.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the MicroPython project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2020 NXP - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -// NOTE: pins.h shall only be included in in pin.h -// hence no include guards are needed since they will be provided by pin.h - -extern pin_obj_t GPIO_AD_B0_09; diff --git a/ports/mimxrt/boards/MIMXRT1064_af.csv b/ports/mimxrt/boards/MIMXRT1064_af.csv new file mode 100644 index 000000000..074a3f69a --- /dev/null +++ b/ports/mimxrt/boards/MIMXRT1064_af.csv @@ -0,0 +1,125 @@ +Pad,ALT0, ALT1, ALT2, ALT3, ALT4, ALT5, ALT6, ALT7, ALT8, ALT9,ADC,ACMP,Default +GPIO_AD_B0_00,FLEXPWM2_PWM3_A,XBAR_INOUT14,REF_CLK_32K,USB_OTG2_ID,LPI2C1_SCLS,GPIO1_IO00,USDHC1_RESET_B,LPSPI3_SCK,,,,ACMP1_IN4,ALT5 +GPIO_AD_B0_01,FLEXPWM2_PWM3_B,XBAR_INOUT15,REF_CLK_24M,USB_OTG1_ID,LPI2C1_SDAS,GPIO1_IO01,EWM_OUT_B,LPSPI3_SOUT,,,,ACMP2_IN4,ALT5 +GPIO_AD_B0_02,FLEXCAN2_TX,XBAR_INOUT16,LPUART6_TXD,USB_OTG1_PWR,FLEXPWM1_PWM0_X,GPIO1_IO02,LPI2C1_HREQ,LPSPI3_SIN,,,,ACMP3_IN4,ALT5 +GPIO_AD_B0_03,FLEXCAN2_RX,XBAR_INOUT17,LPUART6_RXD,USB_OTG1_OC,FLEXPWM1_PWM1_X,GPIO1_IO03,REF_CLK_24M,LPSPI3_PCS0,,,,ACMP4_IN4,ALT5 +GPIO_AD_B0_04,SRC_BOOT_MODE0,MQS_RIGHT,ENET_TX_DATA3,SAI2_TX_SYNC,CSI_DATA09,GPIO1_IO04,PIT_TRIGGER0,LPSPI3_PCS1,,,,,ALT0 +GPIO_AD_B0_05,SRC_BOOT_MODE1,MQS_LEFT,ENET_TX_DATA2,SAI2_TX_BCLK,CSI_DATA08,GPIO1_IO05,XBAR_INOUT17,LPSPI3_PCS2,,,,,ALT0 +GPIO_AD_B0_06,"JTAG_TMS,SWD_DIO",GPT2_COMPARE1,ENET_RX_CLK,SAI2_RX_BCLK,CSI_DATA07,GPIO1_IO06,XBAR_INOUT18,LPSPI3_PCS3,,,,,ALT0 +GPIO_AD_B0_07,"JTAG_TCK,SWD_CLK",GPT2_COMPARE2,ENET_TX_ER,SAI2_RX_SYNC,CSI_DATA06,GPIO1_IO07,XBAR_INOUT19,ENET_1588_EVENT3_OUT,,,,,ALT0 +GPIO_AD_B0_08,JTAG_MOD,GPT2_COMPARE3,ENET_RX_DATA3,SAI2_RX_DATA,CSI_DATA05,GPIO1_IO08,XBAR_INOUT20,ENET_1588_EVENT3_IN,,,,,ALT0 +GPIO_AD_B0_09,JTAG_TDI,FLEXPWM2_PWM3_A,ENET_RX_DATA2,SAI2_TX_DATA,CSI_DATA04,GPIO1_IO09,XBAR_INOUT21,GPT2_CLK,,SEMC_DQS4,,,ALT0 +GPIO_AD_B0_10,JTAG_TDO,FLEXPWM1_PWM3_A,ENET_CRS,SAI2_MCLK,CSI_DATA03,GPIO1_IO10,XBAR_INOUT22,ENET_1588_EVENT0_OUT,FLEXCAN3_TX,ARM_TRACE_SWO,,,ALT0 +GPIO_AD_B0_11,JTAG_TRSTB,FLEXPWM1_PWM3_B,ENET_COL,WDOG1_B,CSI_DATA02,GPIO1_IO11,XBAR_INOUT23,ENET_1588_EVENT0_IN,FLEXCAN3_RX,SEMC_CLK6,,,ALT0 +GPIO_AD_B0_12,LPI2C4_SCL,CCM_PMIC_READY,LPUART1_TXD,WDOG2_B,FLEXPWM1_PWM2_X,GPIO1_IO12,ENET_1588_EVENT1_OUT,NMI_GLUE_NMI,,,ADC1_IN1,,ALT5 +GPIO_AD_B0_13,LPI2C4_SDA,GPT1_CLK,LPUART1_RXD,EWM_OUT_B,FLEXPWM1_PWM3_X,GPIO1_IO13,ENET_1588_EVENT1_IN,REF_CLK_24M,,,ADC1_IN2,ACMP1_IN2,ALT5 +GPIO_AD_B0_14,USB_OTG2_OC,XBAR_INOUT24,LPUART1_CTS_B,ENET_1588_EVENT0_OUT,CSI_VSYNC,GPIO1_IO14,FLEXCAN2_TX,WDOG1_ANY,FLEXCAN3_TX,,ADC1_IN3,ACMP2_IN2,ALT5 +GPIO_AD_B0_15,USB_OTG2_PWR,XBAR_INOUT25,LPUART1_RTS_B,ENET_1588_EVENT0_IN,CSI_HSYNC,GPIO1_IO15,FLEXCAN2_RX,WDOG1_RESET_B_DEB,FLEXCAN3_RX,,ADC1_IN4,ACMP3_IN2,ALT5 +GPIO_AD_B1_00,USB_OTG2_ID,TMR3_TIMER0,LPUART2_CTS_B,LPI2C1_SCL,WDOG1_B,GPIO1_IO16,USDHC1_WP,KPP_ROW7,ENET2_1588_EVENT0_OUT,FLEXIO3_D00,"ADC1_IN5,ADC2_IN5",ACMP4_IN2,ALT5 +GPIO_AD_B1_01,USB_OTG1_PWR,TMR3_TIMER1,LPUART2_RTS_B,LPI2C1_SDA,CCM_PMIC_READY,GPIO1_IO17,USDHC1_VSELECT,KPP_COL7,ENET2_1588_EVENT0_IN,FLEXIO3_D01,"ADC1_IN6,ADC2_IN6","ACMP1_IN0,ACMP2_IN0,ACMP3_IN0,ACMP4_IN0",ALT5 +GPIO_AD_B1_02,USB_OTG1_ID,TMR3_TIMER2,LPUART2_TXD,SPDIF_OUT,ENET_1588_EVENT2_OUT,GPIO1_IO18,USDHC1_CD_B,KPP_ROW6,GPT2_CLK,FLEXIO3_D02,"ADC1_IN7,ADC2_IN7",ACMP1_IN3,ALT5 +GPIO_AD_B1_03,USB_OTG1_OC,TMR3_TIMER3,LPUART2_RXD,SPDIF_IN,ENET_1588_EVENT2_IN,GPIO1_IO19,USDHC2_CD_B,KPP_COL6,GPT2_CAPTURE1,FLEXIO3_D03,"ADC1_IN8,ADC2_IN8",ACMP2_IN3,ALT5 +GPIO_AD_B1_04,FLEXSPI_B_DATA3,ENET_MDC,LPUART3_CTS_B,SPDIF_SR_CLK,CSI_PIXCLK,GPIO1_IO20,USDHC2_DATA0,KPP_ROW5,GPT2_CAPTURE2,FLEXIO3_D04,"ADC1_IN9,ADC2_IN9",ACMP3_IN3,ALT5 +GPIO_AD_B1_05,FLEXSPI_B_DATA2,ENET_MDIO,LPUART3_RTS_B,SPDIF_OUT,CSI_MCLK,GPIO1_IO21,USDHC2_DATA1,KPP_COL5,GPT2_COMPARE1,FLEXIO3_D05,"ADC1_IN10,ADC2_IN10",ACMP4_IN3,ALT5 +GPIO_AD_B1_06,FLEXSPI_B_DATA1,LPI2C3_SDA,LPUART3_TXD,SPDIF_LOCK,CSI_VSYNC,GPIO1_IO22,USDHC2_DATA2,KPP_ROW4,GPT2_COMPARE2,FLEXIO3_D06,"ADC1_IN11,ADC2_IN11","ACMP1_IN1,ACMP2_IN1,ACMP3_IN1,ACMP4_IN1",ALT5 +GPIO_AD_B1_07,FLEXSPI_B_DATA0,LPI2C3_SCL,LPUART3_RXD,SPDIF_EXT_CLK,CSI_HSYNC,GPIO1_IO23,USDHC2_DATA3,KPP_COL4,GPT2_COMPARE3,FLEXIO3_D07,"ADC1_IN12,ADC2_IN12",ACMP1_IN5,ALT5 +GPIO_AD_B1_08,FLEXSPI_A_SS1_B,FLEXPWM4_PWM0_A,FLEXCAN1_TX,CCM_PMIC_READY,CSI_DATA09,GPIO1_IO24,USDHC2_CMD,KPP_ROW3,,FLEXIO3_D08,"ADC1_IN13,ADC2_IN13",ACMP2_IN5,ALT5 +GPIO_AD_B1_09,FLEXSPI_A_DQS,FLEXPWM4_PWM1_A,FLEXCAN1_RX,SAI1_MCLK,CSI_DATA08,GPIO1_IO25,USDHC2_CLK,KPP_COL3,,FLEXIO3_D09,"ADC1_IN14,ADC2_IN14",ACMP3_IN5,ALT5 +GPIO_AD_B1_10,FLEXSPI_A_DATA3,WDOG1_B,LPUART8_TXD,SAI1_RX_SYNC,CSI_DATA07,GPIO1_IO26,USDHC2_WP,KPP_ROW2,ENET2_1588_EVENT1_OUT,FLEXIO3_D10,"ADC1_IN15,ADC2_IN15",ACMP4_IN5,ALT5 +GPIO_AD_B1_11,FLEXSPI_A_DATA2,EWM_OUT_B,LPUART8_RXD,SAI1_RX_BCLK,CSI_DATA06,GPIO1_IO27,USDHC2_RESET_B,KPP_COL2,ENET2_1588_EVENT1_IN,FLEXIO3_D11,"ADC1_IN0,ADC2_IN0",ACMP1_IN6,ALT5 +GPIO_AD_B1_12,FLEXSPI_A_DATA1,ACMP_OUT00,LPSPI3_PCS0,SAI1_RX_DATA0,CSI_DATA05,GPIO1_IO28,USDHC2_DATA4,KPP_ROW1,ENET2_1588_EVENT2_OUT,FLEXIO3_D12,ADC2_IN1,"ACMP1_OUT,ACMP2_IN6",ALT5 +GPIO_AD_B1_13,FLEXSPI_A_DATA0,ACMP_OUT01,LPSPI3_SIN,SAI1_TX_DATA0,CSI_DATA04,GPIO1_IO29,USDHC2_DATA5,KPP_COL1,ENET2_1588_EVENT2_IN,FLEXIO3_D13,ADC2_IN2,"ACMP2_OUT,ACMP3_IN6",ALT5 +GPIO_AD_B1_14,FLEXSPI_A_SCLK,ACMP_OUT02,LPSPI3_SOUT,SAI1_TX_BCLK,CSI_DATA03,GPIO1_IO30,USDHC2_DATA6,KPP_ROW0,ENET2_1588_EVENT3_OUT,FLEXIO3_D14,ADC2_IN3,"ACMP3_OUT,ACMP4_IN6",ALT5 +GPIO_AD_B1_15,FLEXSPI_A_SS0_B,AMCP_OUT03,LPSPI3_SCK,SAI1_TX_SYNC,CSI_DATA02,GPIO1_IO31,USDHC2_DATA7,KPP_COL0,ENET2_1588_EVENT3_IN,FLEXIO3_D15,ADC2_IN4,ACMP4_OUT,ALT5 +GPIO_B0_00,LCD_CLK,TMR1_TIMER0,MQS_RIGHT,LPSPI4_PCS0,FLEXIO2_D00,GPIO2_IO00,SEMC_CSX1,,ENET2_MDC,,,,ALT5 +GPIO_B0_01,LCD_ENABLE,TMR1_TIMER1,MQS_LEFT,LPSPI4_SIN,FLEXIO2_D01,GPIO2_IO01,SEMC_CSX2,,ENET2_MDIO,,,,ALT5 +GPIO_B0_02,LCD_HSYNC,TMR1_TIMER2,FLEXCAN1_TX,LPSPI4_SOUT,FLEXIO2_D02,GPIO2_IO02,SEMC_CSX3,,ENET2_1588_EVENT0_OUT,,,,ALT5 +GPIO_B0_03,LCD_VSYNC,TMR2_TIMER0,FLEXCAN1_RX,LPSPI4_SCK,FLEXIO2_D03,GPIO2_IO03,WDOG2_RESET_B_DEB,,ENET2_1588_EVENT0_IN,,,,ALT5 +GPIO_B0_04,LCD_DATA00,TMR2_TIMER1,LPI2C2_SCL,ARM_TRACE0,FLEXIO2_D04,GPIO2_IO04,SRC_BT_CFG00,,ENET2_TDATA3,,,,ALT5 +GPIO_B0_05,LCD_DATA01,TMR2_TIMER2,LPI2C2_SDA,ARM_TRACE1,FLEXIO2_D05,GPIO2_IO05,SRC_BT_CFG01,,ENET2_TDATA2,,,,ALT5 +GPIO_B0_06,LCD_DATA02,TMR3_TIMER0,FLEXPWM2_PWM0_A,ARM_TRACE2,FLEXIO2_D06,GPIO2_IO06,SRC_BT_CFG02,,ENET2_RX_CLK,,,,ALT5 +GPIO_B0_07,LCD_DATA03,TMR3_TIMER1,FLEXPWM2_PWM0_B,ARM_TRACE3,FLEXIO2_D07,GPIO2_IO07,SRC_BT_CFG03,,ENET2_TX_ER,,,,ALT5 +GPIO_B0_08,LCD_DATA04,TMR3_TIMER2,FLEXPWM2_PWM1_A,LPUART3_TXD,FLEXIO2_D08,GPIO2_IO08,SRC_BT_CFG04,,ENET2_RDATA3,,,,ALT5 +GPIO_B0_09,LCD_DATA05,TMR4_TIMER0,FLEXPWM2_PWM1_B,LPUART3_RXD,FLEXIO2_D09,GPIO2_IO09,SRC_BT_CFG05,,ENET2_RDATA2,,,,ALT5 +GPIO_B0_10,LCD_DATA06,TMR4_TIMER1,FLEXPWM2_PWM2_A,"SAI1_TX_DATA3,SAI1_RX_DATA1",FLEXIO2_D10,GPIO2_IO10,SRC_BT_CFG06,,ENET2_CRS,,,,ALT5 +GPIO_B0_11,LCD_DATA07,TMR4_TIMER2,FLEXPWM2_PWM2_B,"SAI1_TX_DATA2,SAI1_RX_DATA2",FLEXIO2_D11,GPIO2_IO11,SRC_BT_CFG07,,ENET2_COL,,,,ALT5 +GPIO_B0_12,LCD_DATA08,XBAR_INOUT10,ARM_TRACE_CLK,"SAI1_TX_DATA1,SAI1_RX_DATA3",FLEXIO2_D12,GPIO2_IO12,SRC_BT_CFG08,,ENET2_TDATA0,,,,ALT5 +GPIO_B0_13,LCD_DATA09,XBAR_INOUT11,ARM_TRACE_SWO,SAI1_MCLK,FLEXIO2_D13,GPIO2_IO13,SRC_BT_CFG09,,ENET2_TDATA1,,,,ALT5 +GPIO_B0_14,LCD_DATA10,XBAR_INOUT12,ARM_EVENT0,SAI1_RX_SYNC,FLEXIO2_D14,GPIO2_IO14,SRC_BT_CFG10,,ENET2_TX_EN,ENET2_REF_CLK2,,,ALT5 +GPIO_B0_15,LCD_DATA11,XBAR_INOUT13,ARM_EVENT1,SAI1_RX_BCLK,FLEXIO2_D15,GPIO2_IO15,SRC_BT_CFG11,,ENET2_TX_CLK,ENET2_REF_CLK2,,,ALT5 +GPIO_B1_00,LCD_DATA12,XBAR_INOUT14,LPUART4_TXD,SAI1_RX_DATA0,FLEXIO2_D16,GPIO2_IO16,FLEXPWM1_PWM3_A,,ENET2_RX_ER,FLEXIO3_D16,,,ALT5 +GPIO_B1_01,LCD_DATA13,XBAR_INOUT15,LPUART4_RXD,SAI1_TX_DATA0,FLEXIO2_D17,GPIO2_IO17,FLEXPWM1_PWM3_B,,ENET2_RDATA0,FLEXIO3_D17,,,ALT5 +GPIO_B1_02,LCD_DATA14,XBAR_INOUT16,LPSPI4_PCS2,SAI1_TX_BCLK,FLEXIO2_D18,GPIO2_IO18,FLEXPWM2_PWM3_A,,ENET2_RDATA1,FLEXIO3_D18,,,ALT5 +GPIO_B1_03,LCD_DATA15,XBAR_INOUT17,LPSPI4_PCS1,SAI1_TX_SYNC,FLEXIO2_D19,GPIO2_IO19,FLEXPWM2_PWM3_B,,ENET2_RX_EN,FLEXIO3_D19,,,ALT5 +GPIO_B1_04,LCD_DATA16,LPSPI4_PCS0,CSI_DATA15,ENET_RX_DATA0,FLEXIO2_D20,GPIO2_IO20,,,GPT1_CLK,FLEXIO3_D20,,,ALT5 +GPIO_B1_05,LCD_DATA17,LPSPI4_SIN,CSI_DATA14,ENET_RX_DATA1,FLEXIO2_D21,GPIO2_IO21,,,GPT1_CAPTURE1,FLEXIO3_D21,,,ALT5 +GPIO_B1_06,LCD_DATA18,LPSPI4_SOUT,CSI_DATA13,ENET_RX_EN,FLEXIO2_D22,GPIO2_IO22,,,GPT1_CAPTURE2,FLEXIO3_D22,,,ALT5 +GPIO_B1_07,LCD_DATA19,LPSPI4_SCK,CSI_DATA12,ENET_TX_DATA0,FLEXIO2_D23,GPIO2_IO23,,,GPT1_COMPARE1,FLEXIO3_D23,,,ALT5 +GPIO_B1_08,LCD_DATA20,TMR1_TIMER3,CSI_DATA11,ENET_TX_DATA1,FLEXIO2_D24,GPIO2_IO24,FLEXCAN2_TX,,GPT1_COMPARE2,FLEXIO3_D24,,,ALT5 +GPIO_B1_09,LCD_DATA21,TMR2_TIMER3,CSI_DATA10,ENET_TX_EN,FLEXIO2_D25,GPIO2_IO25,FLEXCAN2_RX,,GPT1_COMPARE3,FLEXIO3_D25,,,ALT5 +GPIO_B1_10,LCD_DATA22,TMR3_TIMER3,CSI_DATA00,ENET_TX_CLK,FLEXIO2_D26,GPIO2_IO26,ENET_REF_CLK,,,FLEXIO3_D26,,,ALT5 +GPIO_B1_11,LCD_DATA23,TMR4_TIMER3,CSI_DATA01,ENET_RX_ER,FLEXIO2_D27,GPIO2_IO27,LPSPI4_PCS3,,,FLEXIO3_D27,,,ALT5 +GPIO_B1_12,,LPUART5_TXD,CSI_PIXCLK,ENET_1588_EVENT0_IN,FLEXIO2_D28,GPIO2_IO28,USDHC1_CD_B,,,FLEXIO3_D28,,,ALT5 +GPIO_B1_13,WDOG1_B,LPUART5_RXD,CSI_VSYNC,ENET_1588_EVENT0_OUT,FLEXIO2_D29,GPIO2_IO29,USDHC1_WP,,,FLEXIO3_D29,,,ALT5 +GPIO_B1_14,ENET_MDC,FLEXPWM4_PWM2_A,CSI_HSYNC,XBAR_INOUT02,FLEXIO2_D30,GPIO2_IO30,USDHC1_VSELECT,,ENET2_TDATA0,FLEXIO3_D30,,,ALT5 +GPIO_B1_15,ENET_MDIO,FLEXPWM4_PWM3_A,CSI_MCLK,XBAR_INOUT03,FLEXIO2_D31,GPIO2_IO31,USDHC1_RESET_B,,ENET2_TDATA1,FLEXIO3_D31,,,ALT5 +GPIO_EMC_00,SEMC_DATA00,FLEXPWM4_PWM0_A,LPSPI2_SCK,XBAR_INOUT02,FLEXIO1_D00,GPIO4_IO0,USB_PHY1_TSTI_TX_LS_MODE,,,,,,ALT5 +GPIO_EMC_01,SEMC_DATA01,FLEXPWM4_PWM0_B,LPSPI2_PCS0,XBAR_INOUT03,FLEXIO1_D01,GPIO4_IO1,USB_PHY1_TSTI_TX_HS_MODE,JTAG_DE_B,,,,,ALT5 +GPIO_EMC_02,SEMC_DATA02,FLEXPWM4_PWM1_A,LPSPI2_SOUT,XBAR_INOUT04,FLEXIO1_D02,GPIO4_IO2,USB_PHY1_TSTI_TX_DN,,,,,,ALT5 +GPIO_EMC_03,SEMC_DATA03,FLEXPWM4_PWM1_B,LPSPI2_SIN,XBAR_INOUT05,FLEXIO1_D03,GPIO4_IO3,USB_PHY1_TSTO_RX_SQUELCH,,,,,,ALT5 +GPIO_EMC_04,SEMC_DATA04,FLEXPWM4_PWM2_A,SAI2_TX_DATA,XBAR_INOUT06,FLEXIO1_D04,GPIO4_IO4,USB_PHY1_TSTO_RX_DISCON_DET,,,,,,ALT5 +GPIO_EMC_05,SEMC_DATA05,FLEXPWM4_PWM2_B,SAI2_TX_SYNC,XBAR_INOUT07,FLEXIO1_D05,GPIO4_IO5,USB_PHY1_TSTO_RX_HS_RXD,,,,,,ALT5 +GPIO_EMC_06,SEMC_DATA06,FLEXPWM2_PWM0_A,SAI2_TX_BCLK,XBAR_INOUT08,FLEXIO1_D06,GPIO4_IO6,USB_PHY2_TSTO_RX_FS_RXD,,,,,,ALT5 +GPIO_EMC_07,SEMC_DATA07,FLEXPWM2_PWM0_B,SAI2_MCLK,XBAR_INOUT09,FLEXIO1_D07,GPIO4_IO7,USB_PHY1_TSTO_RX_HS_RXD,,,,,,ALT5 +GPIO_EMC_08,SEMC_DM0,FLEXPWM2_PWM1_A,SAI2_RX_DATA,XBAR_INOUT17,FLEXIO1_D08,GPIO4_IO8,USB_PHY1_TSTO_RX_HS_,,,,,,ALT5 +GPIO_EMC_09,SEMC_ADDR00,FLEXPWM2_PWM1_B,SAI2_RX_SYNC,FLEXCAN2_TX,FLEXIO1_D09,GPIO4_IO9,USB_PHY1_TSTI_TX_EN,,FLEXSPI2_B_SS1_B,,,,ALT5 +GPIO_EMC_10,SEMC_ADDR01,FLEXPWM2_PWM2_A,SAI2_RX_BCLK,FLEXCAN2_RX,FLEXIO1_D10,GPIO4_IO10,USB_PHY1_TSTI_TX_HIZ,,FLEXSPI2_B_SS0_B,,,,ALT5 +GPIO_EMC_11,SEMC_ADDR02,FLEXPWM2_PWM2_B,LPI2C4_SDA,USDHC2_RESET_B,FLEXIO1_D11,GPIO4_IO11,USB_PHY2_TSTO_RX_HS_RXD,,FLEXSPI2_B_DQS,,,,ALT5 +GPIO_EMC_12,SEMC_ADDR03,XBAR_INOUT24,LPI2C4_SCL,USDHC1_WP,FLEXPWM1_PWM3_A,GPIO4_IO12,USB_PHY1_TSTO_PLL_CLK20DIV,,FLEXSPI2_B_SCLK,,,,ALT5 +GPIO_EMC_13,SEMC_ADDR04,XBAR_INOUT25,LPUART3_TXD,MQS_RIGHT,FLEXPWM1_PWM3_B,GPIO4_IO13,USB_PHY2_TSTO_PLL_CLK20DIV,,FLEXSPI2_B_DATA0,,,,ALT5 +GPIO_EMC_14,SEMC_ADDR05,XBAR_INOUT19,LPUART3_RXD,MQS_LEFT,LPSPI2_PCS1,GPIO4_IO14,USB_PHY2_TSTO_RX_SQUELCH,,FLEXSPI2_B_DATA1,,,,ALT5 +GPIO_EMC_15,SEMC_ADDR06,XBAR_INOUT20,LPUART3_CTS_B,SPDIF_OUT,TMR3_TIMER0,GPIO4_IO15,USB_PHY2_TSTO_RX_DISCON_DET,,FLEXSPI2_B_DATA2,,,,ALT5 +GPIO_EMC_16,SEMC_ADDR07,XBAR_INOUT21,LPUART3_RTS_B,SPDIF_IN,TMR3_TIMER1,GPIO4_IO16,,,FLEXSPI2_B_DATA3,,,,ALT5 +GPIO_EMC_17,SEMC_ADDR08,FLEXPWM4_PWM3_A,LPUART4_CTS_B,FLEXCAN1_TX,TMR3_TIMER2,GPIO4_IO17,,,,,,,ALT5 +GPIO_EMC_18,SEMC_ADDR09,FLEXPWM4_PWM3_B,LPUART4_RTS_B,FLEXCAN1_RX,TMR3_TIMER3,GPIO4_IO18,SNVS_VIO_5_CTL,,,,,,ALT5 +GPIO_EMC_19,SEMC_ADDR11,FLEXPWM2_PWM3_A,LPUART4_TXD,ENET_RX_DATA1,TMR2_TIMER0,GPIO4_IO19,SNVS_VIO_5_B,,,,,,ALT5 +GPIO_EMC_20,SEMC_ADDR12,FLEXPWM2_PWM3_B,LPUART4_RXD,ENET_RX_DATA0,TMR2_TIMER1,GPIO4_IO20,,,,,,,ALT5 +GPIO_EMC_21,SEMC_BA0,FLEXPWM3_PWM3_A,LPI2C3_SDA,ENET_TX_DATA1,TMR2_TIMER2,GPIO4_IO21,,,,,,,ALT5 +GPIO_EMC_22,SEMC_BA1,FLEXPWM3_PWM3_B,LPI2C3_SCL,ENET_TX_DATA0,TMR2_TIMER3,GPIO4_IO22,,,FLEXSPI2_A_SS1_B,,,,ALT5 +GPIO_EMC_23,SEMC_ADDR10,FLEXPWM1_PWM0_A,LPUART5_TXD,ENET_RX_EN,GPT1_CAPTURE2,GPIO4_IO23,,,FLEXSPI2_A_DQS,,,,ALT5 +GPIO_EMC_24,SEMC_CAS,FLEXPWM1_PWM0_B,LPUART5_RXD,ENET_TX_EN,GPT1_CAPTURE1,GPIO4_IO24,,,FLEXSPI2_A_SS0_B,,,,ALT5 +GPIO_EMC_25,SEMC_RAS,FLEXPWM1_PWM1_A,LPUART6_TXD,ENET_TX_CLK,ENET_REF_CLK,GPIO4_IO25,,,FLEXSPI2_A_SCLK,,,,ALT5 +GPIO_EMC_26,SEMC_CLK,FLEXPWM1_PWM1_B,LPUART6_RXD,ENET_RX_ER,FLEXIO1_D12,GPIO4_IO26,,,FLEXSPI2_A_DATA0,,,,ALT5 +GPIO_EMC_27,SEMC_CKE,FLEXPWM1_PWM2_A,LPUART5_RTS_B,LPSPI1_SCK,FLEXIO1_D13,GPIO4_IO27,,,FLEXSPI2_A_DATA1,,,,ALT5 +GPIO_EMC_28,SEMC_WE,FLEXPWM1_PWM2_B,LPUART5_CTS_B,LPSPI1_SOUT,FLEXIO1_D14,GPIO4_IO28,,,FLEXSPI2_A_DATA2,,,,ALT5 +GPIO_EMC_29,SEMC_CS0,FLEXPWM3_PWM0_A,LPUART6_RTS_B,LPSPI1_SIN,FLEXIO1_D15,GPIO4_IO29,,,FLEXSPI2_A_DATA3,,,,ALT5 +GPIO_EMC_30,SEMC_DATA08,FLEXPWM3_PWM0_B,LPUART6_CTS_B,LPSPI1_PCS0,CSI_DATA23,GPIO4_IO30,,,ENET2_TDATA0,,,,ALT5 +GPIO_EMC_31,SEMC_DATA09,FLEXPWM3_PWM1_A,LPUART7_TXD,LPSPI1_PCS1,CSI_DATA22,GPIO4_IO31,,,ENET2_TDATA1,,,,ALT5 +GPIO_EMC_32,SEMC_DATA10,FLEXPWM3_PWM1_B,LPUART7_RXD,CCM_PMIC_READY,CSI_DATA21,GPIO3_IO18,,,ENET2_TX_EN,,,,ALT5 +GPIO_EMC_33,SEMC_DATA11,FLEXPWM3_PWM2_A,USDHC1_RESET_B,SAI3_RX_DATA,CSI_DATA20,GPIO3_IO19,,,ENET2_TX_CLK,ENET2_REF_CLK2,,,ALT5 +GPIO_EMC_34,SEMC_DATA12,FLEXPWM3_PWM2_B,USDHC1_VSELECT,SAI3_RX_SYNC,CSI_DATA19,GPIO3_IO20,,,ENET2_RX_ER,,,,ALT5 +GPIO_EMC_35,SEMC_DATA13,XBAR_INOUT18,GPT1_COMPARE1,SAI3_RX_BCLK,CSI_DATA18,GPIO3_IO21,USDHC1_CD_B,,ENET2_RDATA0,,,,ALT5 +GPIO_EMC_36,SEMC_DATA14,XBAR_INOUT22,GPT1_COMPARE2,SAI3_TX_DATA,CSI_DATA17,GPIO3_IO22,USDHC1_WP,,ENET2_RDATA1,FLEXCAN3_TX,,,ALT5 +GPIO_EMC_37,SEMC_DATA15,XBAR_INOUT23,GPT1_COMPARE3,SAI3_MCLK,CSI_DATA16,GPIO3_IO23,USDHC2_WP,,ENET2_RX_EN,FLEXCAN3_RX,,,ALT5 +GPIO_EMC_38,SEMC_DM1,FLEXPWM1_PWM3_A,LPUART8_TXD,SAI3_TX_BCLK,CSI_FIELD,GPIO3_IO24,USDHC2_VSELECT,,ENET2_MDC,,,,ALT5 +GPIO_EMC_39,SEMC_DQS,FLEXPWM1_PWM3_B,LPUART8_RXD,SAI3_TX_SYNC,WDOG1_B,GPIO3_IO25,USDHC2_CD_B,,ENET2_MDIO,,,,ALT5 +GPIO_EMC_40,SEMC_RDY,GPT2_CAPTURE2,LPSPI1_PCS2,USB_OTG2_OC,ENET_MDC,GPIO3_IO26,USDHC2_RESET_B,,,SEMC_CLK5,,,ALT5 +GPIO_EMC_41,SEMC_CSX0,GPT2_CAPTURE1,LPSPI1_PCS3,USB_OTG2_PWR,ENET_MDIO,GPIO3_IO27,USDHC1_VSELECT,,,,,,ALT5 +GPIO_SD_B0_00,USDHC1_CMD,FLEXPWM1_PWM0_A,LPI2C3_SCL,XBAR_INOUT04,LPSPI1_SCK,GPIO3_IO12,FLEXSPI_A_SS1_B,,ENET2_TX_EN,SEMC_DQS4,,,ALT5 +GPIO_SD_B0_01,USDHC1_CLK,FLEXPWM1_PWM0_B,LPI2C3_SDA,XBAR_INOUT05,LPSPI1_PCS0,GPIO3_IO13,FLEXSPI_B_SS1_B,,ENET2_TX_CLK,ENET2_REF_CLK2,,,ALT5 +GPIO_SD_B0_02,USDHC1_DATA0,FLEXPWM1_PWM1_A,LPUART8_CTS_B,XBAR_INOUT06,LPSPI1_SOUT,GPIO3_IO14,,,ENET2_RX_ER,SEMC_CLK5,,,ALT5 +GPIO_SD_B0_03,USDHC1_DATA1,FLEXPWM1_PWM1_B,LPUART8_RTS_B,XBAR_INOUT07,LPSPI1_SIN,GPIO3_IO15,,,ENET2_RDATA0,SEMC_CLK6,,,ALT5 +GPIO_SD_B0_04,USDHC1_DATA2,FLEXPWM1_PWM2_A,LPUART8_TXD,XBAR_INOUT08,FLEXSPI_B_SS0_B,GPIO3_IO16,CCM_CLKO1,,ENET2_RDATA1,,,,ALT5 +GPIO_SD_B0_05,USDHC1_DATA3,FLEXPWM1_PWM2_B,LPUART8_RXD,XBAR_INOUT09,FLEXSPI_B_DQS,GPIO3_IO17,CCM_CLKO2,,ENET2_RX_EN,,,,ALT5 +GPIO_SD_B1_00,USDHC2_DATA3,FLEXSPI_B_DATA3,FLEXPWM1_PWM3_A,"SAI1_TX_DATA3,SAI1_RX_DATA1",LPUART4_TXD,GPIO3_IO00,,,SAI3_RX_DATA,,,,ALT5 +GPIO_SD_B1_01,USDHC2_DATA2,FLEXSPI_B_DATA2,FLEXPWM1_PWM3_B,"SAI1_TX_DATA2,SAI1_RX_DATA2",LPUART4_RXD,GPIO3_IO01,,,SAI3_TX_DATA,,,,ALT5 +GPIO_SD_B1_02,USDHC2_DATA1,FLEXSPI_B_DATA1,FLEXPWM2_PWM3_A,"SAI1_TX_DATA1,SAI1_RX_DATA3",FLEXCAN1_TX,GPIO3_IO02,CCM_WAIT,,SAI3_TX_SYNC,,,,ALT5 +GPIO_SD_B1_03,USDHC2_DATA0,FLEXSPI_B_DATA0,FLEXPWM2_PWM3_B,SAI1_MCLK,FLEXCAN1_RX,GPIO3_IO03,CCM_PMIC_READY,,SAI3_TX_BCLK,,,,ALT5 +GPIO_SD_B1_04,USDHC2_CLK,FLEXSPI_B_SCLK,LPI2C1_SCL,SAI1_RX_SYNC,FLEXSPI_A_SS1_B,GPIO3_IO04,CCM_STOP,,SAI3_MCLK,,,,ALT5 +GPIO_SD_B1_05,USDHC2_CMD,FLEXSPI_A_DQS,LPI2C1_SDA,SAI1_RX_BCLK,FLEXSPI_B_SS0_B,GPIO3_IO05,,,SAI3_RX_SYNC,,,,ALT5 +GPIO_SD_B1_06,USDHC2_RESET_B,FLEXSPI_A_SS0_B,LPUART7_CTS_B,SAI1_RX_DATA0,LPSPI2_PCS0,GPIO3_IO06,,,SAI3_RX_BCLK,,,,ALT5 +GPIO_SD_B1_07,SEMC_CSX1,FLEXSPI_A_SCLK,LPUART7_RTS_B,SAI1_TX_DATA0,LPSPI2_SCK,GPIO3_IO07,,,,,,,ALT5 +GPIO_SD_B1_08,USDHC2_DATA4,FLEXSPI_A_DATA0,LPUART7_TXD,SAI1_TX_BCLK,LPSPI2_SOUT,GPIO3_IO08,SEMC_CSX2,,,,,,ALT5 +GPIO_SD_B1_09,USDHC2_DATA5,FLEXSPI_A_DATA1,LPUART7_RXD,SAI1_TX_SYNC,LPSPI2_SIN,GPIO3_IO09,,,,,,,ALT5 +GPIO_SD_B1_10,USDHC2_DATA6,FLEXSPI_A_DATA2,LPUART2_RXD,LPI2C2_SDA,LPSPI2_PCS2,GPIO3_IO10,,,,,,,ALT5 +GPIO_SD_B1_11,USDHC2_DATA7,FLEXSPI_A_DATA3,LPUART2_TXD,LPI2C2_SCL,LPSPI2_PCS3,GPIO3_IO11,,,,,,,ALT5 diff --git a/ports/mimxrt/boards/TEENSY40/mpconfigboard.h b/ports/mimxrt/boards/TEENSY40/mpconfigboard.h index 7d5647857..e3d7c6a12 100644 --- a/ports/mimxrt/boards/TEENSY40/mpconfigboard.h +++ b/ports/mimxrt/boards/TEENSY40/mpconfigboard.h @@ -4,6 +4,6 @@ #define BOARD_FLASH_SIZE (2 * 1024 * 1024) // Teensy 4.0 has 1 board LED -#define MICROPY_HW_LED1_PIN (GPIO_B0_03) +#define MICROPY_HW_LED1_PIN (pin_GPIO_B0_03) #define MICROPY_HW_LED_ON(pin) (mp_hal_pin_high(pin)) #define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_low(pin)) diff --git a/ports/mimxrt/boards/TEENSY40/pins.c b/ports/mimxrt/boards/TEENSY40/pins.c deleted file mode 100644 index c7bfc102d..000000000 --- a/ports/mimxrt/boards/TEENSY40/pins.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the MicroPython project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2020 Philipp Ebensberger - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "pin.h" - -static pin_af_obj_t GPIO_B0_03_af[] = { - PIN_AF(GPIO2_IO03, PIN_AF_MODE_ALT5, GPIO2, 0x10B0U), -}; - -pin_obj_t GPIO_B0_03 = PIN(GPIO_B0_03, GPIO2, 3, GPIO_B0_03_af); diff --git a/ports/mimxrt/boards/TEENSY40/pins.csv b/ports/mimxrt/boards/TEENSY40/pins.csv new file mode 100644 index 000000000..c9d7c9856 --- /dev/null +++ b/ports/mimxrt/boards/TEENSY40/pins.csv @@ -0,0 +1,55 @@ +D0,GPIO_AD_B0_03 +D1,GPIO_AD_B0_02 +D2,GPIO_EMC_04 +D3,GPIO_EMC_05 +D4,GPIO_EMC_06 +D5,GPIO_EMC_08 +D6,GPIO_B0_10 +D7,GPIO_B1_01 +D8,GPIO_B1_00 +D9,GPIO_B0_11 +D10,GPIO_B0_00 +D11,GPIO_B0_02 +D12,GPIO_B0_01 +D13,GPIO_B0_03 +D14,GPIO_AD_B1_02 +D15,GPIO_AD_B1_03 +D16,GPIO_AD_B1_07 +D17,GPIO_AD_B1_06 +D18,GPIO_AD_B1_01 +D19,GPIO_AD_B1_00 +D20,GPIO_AD_B1_10 +D21,GPIO_AD_B1_11 +D22,GPIO_AD_B1_08 +D23,GPIO_AD_B1_09 +D24,GPIO_AD_B0_12 +D25,GPIO_AD_B0_13 +D26,GPIO_AD_B1_14 +D27,GPIO_AD_B1_15 +D28,GPIO_EMC_32 +D29,GPIO_EMC_31 +D30,GPIO_EMC_37 +D31,GPIO_EMC_36 +D32,GPIO_B0_12 +D33,GPIO_EMC_07 +DAT1,GPIO_AD_B0_03 +DAT0,GPIO_AD_B0_02 +CLK,GPIO_AD_B0_01 +CMD,GPIO_ASD_B0_00 +DAT3,GPIO_SD_B0_05 +DAT2,GPIO_SD_B0_04 +A0,GPIO_AD_B1_02 +A1,GPIO_AD_B1_03 +A2,GPIO_AD_B1_07 +A3,GPIO_AD_B1_06 +A4,GPIO_AD_B1_01 +A5,GPIO_AD_B1_00 +A6,GPIO_AD_B1_10 +A7,GPIO_AD_B1_11 +A8,GPIO_AD_B1_08 +A9,GPIO_AD_B1_09 +A10,GPIO_AD_B0_12 +A11,GPIO_AD_B0_13 +A12,GPIO_AD_B1_14 +A13,GPIO_AD_B1_15 +LED,GPIO_B0_03
\ No newline at end of file diff --git a/ports/mimxrt/boards/TEENSY40/pins.h b/ports/mimxrt/boards/TEENSY40/pins.h deleted file mode 100644 index c0b6dcdfa..000000000 --- a/ports/mimxrt/boards/TEENSY40/pins.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the MicroPython project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2020 Philipp Ebensberger - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -// NOTE: pins.h shall only be included in in pin.h -// hence no include guards are needed since they will be provided by pin.h - -extern pin_obj_t GPIO_B0_03; diff --git a/ports/mimxrt/boards/make-pins.py b/ports/mimxrt/boards/make-pins.py new file mode 100644 index 000000000..5e5b81e31 --- /dev/null +++ b/ports/mimxrt/boards/make-pins.py @@ -0,0 +1,259 @@ +#!/usr/bin/env python +"""Creates the pin file for the MIMXRT10xx.""" + +from __future__ import print_function + +import argparse +import sys +import csv + +SUPPORTED_AFS = {"GPIO"} +MAX_AF = 10 # AF0 .. AF9 + + +def parse_pad(pad_str): + """Parses a string and returns a (port, gpio_bit) tuple.""" + if len(pad_str) < 4: + raise ValueError("Expecting pad name to be at least 4 characters") + if pad_str[:4] != "GPIO": + raise ValueError("Expecting pad name to start with GPIO") + return pad_str + + +def af_supported(af_str): + for supported_af in SUPPORTED_AFS: + if af_str.startswith(supported_af): + return True + else: + return False + + +class Pin(object): + """Holds the information associated with a pin.""" + + def __init__(self, pad, gpio, pin, idx=0): + self.idx = idx + self.name = pad + self.pad = pad + self.gpio = gpio + self.pin = pin + self.alt_fn = [] + self.adc_channel = 0 + self.board_pin = False + + def set_is_board_pin(self): + self.board_pin = True + + def is_board_pin(self): + return self.board_pin + + def parse_adc(self, adc_str): + pass + + def parse_af(self, af_idx, af_strs_in): + pass + + def add_af(self, af): + self.alt_fn.append(af) + + def print_pin_af(self): + if self.alt_fn: + print( + "static const machine_pin_af_obj_t pin_{0}_af[{1}] = {{".format( + self.name, len(self.alt_fn) + ) + ) + for af in self.alt_fn: + af.print() + print("};") + else: + raise ValueError("Pin '{}' has no alternative functions".format(self.name)) + + def print(self): + if self.alt_fn: + self.print_pin_af() + print( + "const machine_pin_obj_t pin_{0} = PIN({0}, {1}, {2}, pin_{3});\n".format( + self.name, self.gpio, int(self.pin), self.name + "_af" + ) + ) + else: + raise ValueError("Pin '{}' has no alternative functions".format(self.name)) + + def print_header(self, hdr_file): + pass + + +class AlternateFunction(object): + """Holds the information associated with a pins alternate function.""" + + def __init__(self, idx, af_str): + self.idx = idx + self.af_str = af_str + self.instance = self.af_str.split("_")[0] + + def print(self): + """Prints the C representation of this AF.""" + print( + " PIN_AF({0}, PIN_AF_MODE_ALT{1}, {2}, {3}),".format( + self.af_str, self.idx, self.instance, "0x10B0U" + ) + ) + + +class NamedPin(object): + def __init__(self, name, pad, idx): + self.name = name + self.pad = pad + self.idx = idx + + +class Pins(object): + def __init__(self): + self.cpu_pins = [] + self.board_pins = [] + + def find_pin_by_num(self, pin_num): + for pin in self.cpu_pins: + if pin.pin_num == pin_num: + return pin + + def find_pin_by_name(self, pad): + for pin in self.cpu_pins: + if pin.pad == pad: + return pin + + def parse_board_file(self, filename): + with open(filename, "r") as csvfile: + rows = csv.reader(csvfile) + for row in rows: + pin = self.find_pin_by_name(row[1]) + if pin and row[0]: # Only add board pins that have a name + self.board_pins.append(NamedPin(row[0], pin.pad, pin.idx)) + + def parse_af_file(self, filename, pad_col, af_start_col): + af_end_col = af_start_col + MAX_AF + with open(filename, "r") as csvfile: + rows = csv.reader(csvfile) + header = next(rows) + for idx, row in enumerate(rows): + pad = row[pad_col] + gpio, pin = row[6].split("_") + pin_number = pin.lstrip("IO") + + pin = Pin(pad, gpio, pin_number, idx=idx) + + # Parse alternate functions + af_idx = 0 + for af_idx, af in enumerate(row[af_start_col:af_end_col]): + if af and af_supported(af): + pin.add_af(AlternateFunction(af_idx, af)) + + self.cpu_pins.append(pin) + + @staticmethod + def print_named(label, pins): + print("") + print( + "STATIC const mp_rom_map_elem_t pin_{:s}_pins_locals_dict_table[] = {{".format(label) + ) + for pin in pins: + print( + " {{ MP_ROM_QSTR(MP_QSTR_{}), MP_ROM_PTR(&pin_{}) }},".format(pin.name, pin.pad) + ) + print("};") + print( + "MP_DEFINE_CONST_DICT(machine_pin_{:s}_pins_locals_dict, pin_{:s}_pins_locals_dict_table);".format( + label, label + ) + ) + + def print(self): + # Print Pin Object declarations + for pin in self.cpu_pins: + pin.print() + + print("") + print("const machine_pin_obj_t* machine_pin_board_pins [] = {") + for pin in self.board_pins: + print(" &pin_{},".format(pin.pad)) + print("};") + print("const uint32_t num_board_pins = {:d};".format(len(self.board_pins))) + # Print Pin mapping dictionaries + self.print_named("cpu", self.cpu_pins) + self.print_named("board", self.board_pins) + print("") + + def print_header(self, hdr_filename): + with open(hdr_filename, "w") as hdr_file: + for pin in self.cpu_pins: + hdr_file.write("extern const machine_pin_obj_t pin_{};\n".format(pin.name)) + hdr_file.write("extern const machine_pin_obj_t* machine_pin_board_pins[];\n") + hdr_file.write("extern const uint32_t num_board_pins;\n") + hdr_file.write("extern const mp_obj_dict_t machine_pin_cpu_pins_locals_dict;\n") + hdr_file.write("extern const mp_obj_dict_t machine_pin_board_pins_locals_dict;\n") + + +def main(): + parser = argparse.ArgumentParser( + prog="make-pins.py", + usage="%(prog)s [options] [command]", + description="Generate board specific pin file", + ) + parser.add_argument( + "-a", + "--af", + dest="af_filename", + help="Specifies the alternate function file for the chip", + default="mimxrt1021_af.csv", + ) + parser.add_argument( + "-b", + "--board", + dest="board_filename", + help="Specifies the board file", + default="MIMXRT1020_EVK/pins.csv", + ) + parser.add_argument( + "-p", + "--prefix", + dest="prefix_filename", + help="Specifies beginning portion of generated pins file", + default="mimxrt_prefix.c", + ) + parser.add_argument( + "-r", + "--hdr", + dest="hdr_filename", + help="Specifies name of generated pin header file", + default="build/pins.h", + ) + + pins = Pins() + + # test code + args = parser.parse_args() + # + + if args.af_filename: + print("// --af {:s}".format(args.af_filename)) + pins.parse_af_file(args.af_filename, 0, 1) + + if args.board_filename: + print("// --board {:s}".format(args.board_filename)) + pins.parse_board_file(args.board_filename) + + if args.hdr_filename: + print("// --hdr {:s}".format(args.hdr_filename)) + + if args.prefix_filename: + print("// --prefix {:s}".format(args.prefix_filename)) + with open(args.prefix_filename, "r") as prefix_file: + print(prefix_file.read()) + + pins.print() + pins.print_header(args.hdr_filename) + + +if __name__ == "__main__": + main() diff --git a/ports/mimxrt/boards/mimxrt_prefix.c b/ports/mimxrt/boards/mimxrt_prefix.c new file mode 100644 index 000000000..59e338976 --- /dev/null +++ b/ports/mimxrt/boards/mimxrt_prefix.c @@ -0,0 +1,26 @@ +#include <stdio.h> + +#include "py/obj.h" +#include "py/mphal.h" +#include "pin.h" + +#define PIN_AF(_name, _af_mode, _instance, _pad_config) \ + { \ + .base = { &machine_pin_af_type }, \ + .name = MP_QSTR_##_name, \ + .af_mode = (uint32_t)(_af_mode), \ + .instance = (void *)(_instance), \ + .pad_config = (uint32_t)(_pad_config), \ + } \ + +#define PIN(_name, _gpio, _pin, _af_list) \ + { \ + .base = { &machine_pin_type }, \ + .name = MP_QSTR_##_name, \ + .gpio = (_gpio), \ + .pin = (uint32_t)(_pin), \ + .muxRegister = (uint32_t)&(IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_##_name]), \ + .configRegister = (uint32_t)&(IOMUXC->SW_PAD_CTL_PAD[kIOMUXC_SW_PAD_CTL_PAD_##_name]), \ + .af_list_len = (size_t)(sizeof((_af_list)) / sizeof(machine_pin_af_obj_t)), \ + .af_list = (_af_list), \ + } \ diff --git a/ports/mimxrt/led.c b/ports/mimxrt/led.c index bec97dd8f..cb9f98546 100644 --- a/ports/mimxrt/led.c +++ b/ports/mimxrt/led.c @@ -44,7 +44,7 @@ const machine_led_obj_t machine_led_obj[NUM_LEDS] = { void led_init(void) { // Turn off LEDs and initialize for (mp_int_t led = 0; led < NUM_LEDS; led++) { - const pin_obj_t *led_pin = machine_led_obj[led].led_pin; + const machine_pin_obj_t *led_pin = machine_led_obj[led].led_pin; gpio_pin_config_t pin_config = { .outputLogic = 1U, @@ -67,7 +67,7 @@ void led_state(machine_led_t led, int state) { return; } - const pin_obj_t *led_pin = machine_led_obj[led - 1].led_pin; + const machine_pin_obj_t *led_pin = machine_led_obj[led - 1].led_pin; if (state == 0) { // turn LED off @@ -83,7 +83,7 @@ void led_toggle(machine_led_t led) { return; } - const pin_obj_t *led_pin = machine_led_obj[led - 1].led_pin; + const machine_pin_obj_t *led_pin = machine_led_obj[led - 1].led_pin; mp_hal_pin_toggle(led_pin); } diff --git a/ports/mimxrt/led.h b/ports/mimxrt/led.h index 35418321d..a0628e90e 100644 --- a/ports/mimxrt/led.h +++ b/ports/mimxrt/led.h @@ -42,7 +42,7 @@ typedef enum { typedef struct _machine_led_obj_t { mp_obj_base_t base; mp_uint_t led_id; - const pin_obj_t *led_pin; + const machine_pin_obj_t *led_pin; } machine_led_obj_t; void led_init(void); diff --git a/ports/mimxrt/machine_pin.c b/ports/mimxrt/machine_pin.c new file mode 100644 index 000000000..583ee4a26 --- /dev/null +++ b/ports/mimxrt/machine_pin.c @@ -0,0 +1,273 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Philipp Ebensberger + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#include <stdint.h> + +#include "fsl_gpio.h" +#include "fsl_iomuxc.h" + +#include "py/runtime.h" +#include "py/mphal.h" +#include "pin.h" +#include "mphalport.h" + +// Local functions +STATIC mp_obj_t machine_pin_obj_init_helper(const machine_pin_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args); + +// Class Methods +STATIC void machine_pin_obj_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind); +STATIC mp_obj_t machine_pin_obj_call(mp_obj_t self_in, mp_uint_t n_args, mp_uint_t n_kw, const mp_obj_t *args); +STATIC mp_obj_t machine_pin_obj_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args); + +// Instance Methods +STATIC mp_obj_t machine_pin_off(mp_obj_t self_in); +STATIC mp_obj_t machine_pin_on(mp_obj_t self_in); +STATIC mp_obj_t machine_pin_value(size_t n_args, const mp_obj_t *args); +STATIC mp_obj_t machine_pin_init(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args); + +// Local data +enum { + PIN_INIT_ARG_MODE = 0, + PIN_INIT_ARG_PULL, + PIN_INIT_ARG_VALUE, + PIN_INIT_ARG_DRIVE, +}; + +// Pin mapping dictionaries +const mp_obj_type_t machine_pin_cpu_pins_obj_type = { + { &mp_type_type }, + .name = MP_QSTR_cpu, + .locals_dict = (mp_obj_t)&machine_pin_cpu_pins_locals_dict, +}; + +const mp_obj_type_t machine_pin_board_pins_obj_type = { + { &mp_type_type }, + .name = MP_QSTR_board, + .locals_dict = (mp_obj_t)&machine_pin_board_pins_locals_dict, +}; + +STATIC mp_obj_t machine_pin_obj_call(mp_obj_t self_in, mp_uint_t n_args, mp_uint_t n_kw, const mp_obj_t *args) { + mp_arg_check_num(n_args, n_kw, 0, 1, false); + machine_pin_obj_t *self = self_in; + + if (n_args == 0) { + return MP_OBJ_NEW_SMALL_INT(mp_hal_pin_read(self)); + } else { + mp_hal_pin_write(self, mp_obj_is_true(args[0])); + return mp_const_none; + } +} + +STATIC mp_obj_t machine_pin_obj_init_helper(const machine_pin_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + static const mp_arg_t allowed_args[] = { + [PIN_INIT_ARG_MODE] { MP_QSTR_mode, MP_ARG_REQUIRED | MP_ARG_INT }, + [PIN_INIT_ARG_PULL] { MP_QSTR_pull, MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE}}, + [PIN_INIT_ARG_VALUE] { MP_QSTR_value, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL}}, + [PIN_INIT_ARG_DRIVE] { MP_QSTR_drive, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = PIN_DRIVE_POWER_3}}, + // TODO: Implement additional arguments + /* + { MP_QSTR_af, MP_ARG_INT, {.u_int = -1}}, // legacy + { MP_QSTR_alt, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1}},*/ + }; + + // Parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + // Get io mode + uint mode = args[PIN_INIT_ARG_MODE].u_int; + if (!IS_GPIO_MODE(mode)) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("invalid pin mode: %d"), mode); + } + + // Handle configuration for GPIO + if ((mode == PIN_MODE_IN) || (mode == PIN_MODE_OUT) || (mode == PIN_MODE_OPEN_DRAIN)) { + gpio_pin_config_t pin_config; + const machine_pin_af_obj_t *af_obj; + uint32_t pad_config = 0UL; + uint8_t pull = PIN_PULL_DISABLED; + + // Generate pin configuration + if ((args[PIN_INIT_ARG_VALUE].u_obj != MP_OBJ_NULL) && (mp_obj_is_true(args[PIN_INIT_ARG_VALUE].u_obj))) { + pin_config.outputLogic = 1U; + } else { + pin_config.outputLogic = 0U; + } + pin_config.direction = mode == PIN_MODE_IN ? kGPIO_DigitalInput : kGPIO_DigitalOutput; + pin_config.interruptMode = kGPIO_NoIntmode; + + af_obj = pin_find_af(self, PIN_AF_MODE_ALT5); // GPIO is always ALT5 + if (af_obj == NULL) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("requested AF %d not available for pin %d"), PIN_AF_MODE_ALT5, mode); + } + + // Generate pad configuration + if (args[PIN_INIT_ARG_PULL].u_obj != mp_const_none) { + pull = (uint8_t)mp_obj_get_int(args[PIN_INIT_ARG_PULL].u_obj); + } + + pad_config |= IOMUXC_SW_PAD_CTL_PAD_SRE(0U); // Slow Slew Rate + pad_config |= IOMUXC_SW_PAD_CTL_PAD_SPEED(0b01); // medium(100MHz) + + if (mode == PIN_MODE_OPEN_DRAIN) { + pad_config |= IOMUXC_SW_PAD_CTL_PAD_ODE(0b1); // Open Drain Enabled + } else { + pad_config |= IOMUXC_SW_PAD_CTL_PAD_ODE(0b0); // Open Drain Disabled + } + + if (pull == PIN_PULL_DISABLED) { + pad_config |= IOMUXC_SW_PAD_CTL_PAD_PKE(0); // Pull/Keeper Disabled + } else if (pull == PIN_PULL_HOLD) { + pad_config |= IOMUXC_SW_PAD_CTL_PAD_PKE(1) | // Pull/Keeper Enabled + IOMUXC_SW_PAD_CTL_PAD_PUE(0); // Keeper selected + } else { + pad_config |= IOMUXC_SW_PAD_CTL_PAD_PKE(1) | // Pull/Keeper Enabled + IOMUXC_SW_PAD_CTL_PAD_PUE(1) | // Pull selected + IOMUXC_SW_PAD_CTL_PAD_PUS(pull); + } + + if (mode == PIN_MODE_IN) { + pad_config |= IOMUXC_SW_PAD_CTL_PAD_DSE(0b000) | // output driver disabled + IOMUXC_SW_PAD_CTL_PAD_HYS(1U); // Hysteresis enabled + } else { + uint drive = args[PIN_INIT_ARG_DRIVE].u_int; + if (!IS_GPIO_DRIVE(drive)) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("invalid drive strength: %d"), drive); + } + + pad_config |= IOMUXC_SW_PAD_CTL_PAD_DSE(drive) | + IOMUXC_SW_PAD_CTL_PAD_HYS(0U); // Hysteresis disabled + } + + // Configure PAD as GPIO + IOMUXC_SetPinMux(self->muxRegister, af_obj->af_mode, 0, 0, self->configRegister, 1U); // Software Input On Field: Input Path is determined by functionality + IOMUXC_SetPinConfig(self->muxRegister, af_obj->af_mode, 0, 0, self->configRegister, pad_config); + GPIO_PinInit(self->gpio, self->pin, &pin_config); + } + + return mp_const_none; +} + +STATIC void machine_pin_obj_print(const mp_print_t *print, mp_obj_t o, mp_print_kind_t kind) { + (void)kind; + const machine_pin_obj_t *self = MP_OBJ_TO_PTR(o); + mp_printf(print, "Pin(%s)", qstr_str(self->name)); +} + +// pin(id, mode, pull, ...) +STATIC mp_obj_t machine_pin_obj_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) { + mp_arg_check_num(n_args, n_kw, 1, MP_OBJ_FUN_ARGS_MAX, true); + + const machine_pin_obj_t *pin = pin_find(args[0]); + + if (n_args > 1 || n_kw > 0) { + // pin mode given, so configure this GPIO + mp_map_t kw_args; + mp_map_init_fixed_table(&kw_args, n_kw, args + n_args); + machine_pin_obj_init_helper(pin, n_args - 1, args + 1, &kw_args); + } + + return (mp_obj_t)pin; +} + +// pin.off() +STATIC mp_obj_t machine_pin_off(mp_obj_t self_in) { + machine_pin_obj_t *self = self_in; + mp_hal_pin_low(self); + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_pin_off_obj, machine_pin_off); + +// pin.on() +STATIC mp_obj_t machine_pin_on(mp_obj_t self_in) { + machine_pin_obj_t *self = self_in; + mp_hal_pin_high(self); + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_pin_on_obj, machine_pin_on); + +// pin.value([value]) +STATIC mp_obj_t machine_pin_value(size_t n_args, const mp_obj_t *args) { + return machine_pin_obj_call(args[0], (n_args - 1), 0, args + 1); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_pin_value_obj, 1, 2, machine_pin_value); + +// pin.init(mode, pull, [kwargs]) +STATIC mp_obj_t machine_pin_init(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) { + return machine_pin_obj_init_helper(args[0], n_args - 1, args + 1, kw_args); +} +MP_DEFINE_CONST_FUN_OBJ_KW(machine_pin_init_obj, 1, machine_pin_init); + +STATIC const mp_rom_map_elem_t machine_pin_locals_dict_table[] = { + // instance methods + { MP_ROM_QSTR(MP_QSTR_off), MP_ROM_PTR(&machine_pin_off_obj) }, + { MP_ROM_QSTR(MP_QSTR_on), MP_ROM_PTR(&machine_pin_on_obj) }, + { MP_ROM_QSTR(MP_QSTR_low), MP_ROM_PTR(&machine_pin_off_obj) }, + { MP_ROM_QSTR(MP_QSTR_high), MP_ROM_PTR(&machine_pin_on_obj) }, + { MP_ROM_QSTR(MP_QSTR_value), MP_ROM_PTR(&machine_pin_value_obj) }, + { MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&machine_pin_init_obj) }, + // class attributes + { MP_ROM_QSTR(MP_QSTR_board), MP_ROM_PTR(&machine_pin_board_pins_obj_type) }, + { MP_ROM_QSTR(MP_QSTR_cpu), MP_ROM_PTR(&machine_pin_cpu_pins_obj_type) }, + // class constants + { MP_ROM_QSTR(MP_QSTR_IN), MP_ROM_INT(PIN_MODE_IN) }, + { MP_ROM_QSTR(MP_QSTR_OUT), MP_ROM_INT(PIN_MODE_OUT) }, + { MP_ROM_QSTR(MP_QSTR_OPEN_DRAIN), MP_ROM_INT(PIN_MODE_OPEN_DRAIN) }, + + { MP_ROM_QSTR(MP_QSTR_PULL_UP), MP_ROM_INT(PIN_PULL_UP_100K) }, + { MP_ROM_QSTR(MP_QSTR_PULL_UP_47K), MP_ROM_INT(PIN_PULL_UP_47K) }, + { MP_ROM_QSTR(MP_QSTR_PULL_UP_22K), MP_ROM_INT(PIN_PULL_UP_22K) }, + { MP_ROM_QSTR(MP_QSTR_PULL_DOWN), MP_ROM_INT(PIN_PULL_DOWN_100K) }, + { MP_ROM_QSTR(MP_QSTR_PULL_HOLD), MP_ROM_INT(PIN_PULL_HOLD) }, + + { MP_ROM_QSTR(MP_QSTR_DRIVER_OFF), MP_ROM_INT(PIN_DRIVE_OFF) }, + { MP_ROM_QSTR(MP_QSTR_POWER_0), MP_ROM_INT(PIN_DRIVE_POWER_0) }, // R0 (150 Ohm @3.3V / 260 Ohm @ 1.8V) + { MP_ROM_QSTR(MP_QSTR_POWER_1), MP_ROM_INT(PIN_DRIVE_POWER_1) }, // R0/2 + { MP_ROM_QSTR(MP_QSTR_POWER_2), MP_ROM_INT(PIN_DRIVE_POWER_2) }, // R0/3 + { MP_ROM_QSTR(MP_QSTR_POWER_3), MP_ROM_INT(PIN_DRIVE_POWER_3) }, // R0/4 + { MP_ROM_QSTR(MP_QSTR_POWER_4), MP_ROM_INT(PIN_DRIVE_POWER_4) }, // R0/5 + { MP_ROM_QSTR(MP_QSTR_POWER_5), MP_ROM_INT(PIN_DRIVE_POWER_5) }, // R0/6 + { MP_ROM_QSTR(MP_QSTR_POWER_6), MP_ROM_INT(PIN_DRIVE_POWER_6) }, // R0/7 + +}; +STATIC MP_DEFINE_CONST_DICT(machine_pin_locals_dict, machine_pin_locals_dict_table); + +const mp_obj_type_t machine_pin_type = { + {&mp_type_type}, + .name = MP_QSTR_Pin, + .print = machine_pin_obj_print, + .call = machine_pin_obj_call, + .make_new = machine_pin_obj_make_new, + .locals_dict = (mp_obj_dict_t *)&machine_pin_locals_dict, +}; + +// FIXME: Create actual pin_af type!!! +const mp_obj_type_t machine_pin_af_type = { + {&mp_type_type}, + .name = MP_QSTR_PinAF, + .print = machine_pin_obj_print, + .make_new = machine_pin_obj_make_new, + .locals_dict = (mp_obj_dict_t *)&machine_pin_locals_dict, +}; diff --git a/ports/mimxrt/modmachine.c b/ports/mimxrt/modmachine.c index a6aab7b4a..1bb6b6a35 100644 --- a/ports/mimxrt/modmachine.c +++ b/ports/mimxrt/modmachine.c @@ -28,6 +28,7 @@ #include "py/runtime.h" #include "extmod/machine_mem.h" #include "led.h" +#include "pin.h" #include CPU_HEADER_H @@ -52,6 +53,7 @@ STATIC const mp_rom_map_elem_t machine_module_globals_table[] = { #if NUM_LEDS { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&machine_led_type) }, #endif + { MP_ROM_QSTR(MP_QSTR_Pin), MP_ROM_PTR(&machine_pin_type) }, }; STATIC MP_DEFINE_CONST_DICT(machine_module_globals, machine_module_globals_table); diff --git a/ports/mimxrt/mphalport.h b/ports/mimxrt/mphalport.h index 993e15156..a6a28ab4a 100644 --- a/ports/mimxrt/mphalport.h +++ b/ports/mimxrt/mphalport.h @@ -29,10 +29,14 @@ #include <stdint.h> #include "ticks.h" +#include "pin.h" +#define mp_hal_pin_obj_t const machine_pin_obj_t * #define mp_hal_pin_high(p) (GPIO_PinWrite(p->gpio, p->pin, 1U)) #define mp_hal_pin_low(p) (GPIO_PinWrite(p->gpio, p->pin, 0U)) +#define mp_hal_pin_write(p, value) (GPIO_PinWrite(p->gpio, p->pin, value)) #define mp_hal_pin_toggle(p) (GPIO_PortToggle(p->gpio, (1 << p->pin))) +#define mp_hal_pin_read(p) (GPIO_PinRead(p->gpio, p->pin)) void mp_hal_set_interrupt_char(int c); diff --git a/ports/mimxrt/pin.c b/ports/mimxrt/pin.c index b30f4be41..7a437661e 100644 --- a/ports/mimxrt/pin.c +++ b/ports/mimxrt/pin.c @@ -24,14 +24,104 @@ * THE SOFTWARE. */ +#include "py/runtime.h" #include "pin.h" -const mp_obj_type_t pin_type = { - .base = {&mp_type_type}, - .name = MP_QSTR_Pin, -}; -const mp_obj_type_t pin_af_type = { - {&mp_type_type}, - .name = MP_QSTR_PinAF, -}; +void pin_init(void) { + return; +} + +uint32_t pin_get_mode(const machine_pin_obj_t *pin) { + uint32_t pin_mode = PIN_MODE_ALT; + uint32_t config_register = *((volatile uint32_t *)pin->configRegister); + uint8_t af_mode = pin_get_af(pin); + + if (af_mode == PIN_AF_MODE_ALT5) { + bool open_drain_enabled = (config_register & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK) >> IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT; + + if (open_drain_enabled) { + pin_mode = PIN_MODE_OPEN_DRAIN; + } else { + // Check pin direction + if ((pin->gpio->GDIR & (1U << pin->pin)) >> pin->pin) { + pin_mode = PIN_MODE_OUT; + } else { + pin_mode = PIN_MODE_IN; + } + } + } + + return pin_mode; +} + +uint32_t pin_get_af(const machine_pin_obj_t *pin) { + uint32_t mux_register = *((volatile uint32_t *)pin->muxRegister); + + // Read configured AF-Mode of pin + return (uint32_t)(mux_register & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) >> IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT; +} + +const machine_pin_obj_t *pin_find(mp_obj_t user_obj) { + const machine_pin_obj_t *pin_obj; + + // If a pin was provided, then use it + if (mp_obj_is_type(user_obj, &machine_pin_type)) { + pin_obj = user_obj; + return pin_obj; + } + + // If pin is SMALL_INT + if (mp_obj_is_small_int(user_obj)) { + uint8_t value = MP_OBJ_SMALL_INT_VALUE(user_obj); + if (value < num_board_pins) { + return machine_pin_board_pins[value]; + } + } + + // See if the pin name matches a board pin + pin_obj = pin_find_named_pin(&machine_pin_board_pins_locals_dict, user_obj); + if (pin_obj) { + return pin_obj; + } + + // See if the pin name matches a cpu pin + pin_obj = pin_find_named_pin(&machine_pin_cpu_pins_locals_dict, user_obj); + if (pin_obj) { + return pin_obj; + } + + mp_raise_ValueError(MP_ERROR_TEXT("Pin doesn't exist")); +} + +const machine_pin_obj_t *pin_find_named_pin(const mp_obj_dict_t *named_pins, mp_obj_t name) { + mp_map_t *named_map = mp_obj_dict_get_map((mp_obj_t)named_pins); + mp_map_elem_t *named_elem = mp_map_lookup(named_map, name, MP_MAP_LOOKUP); + if (named_elem != NULL && named_elem->value != NULL) { + return named_elem->value; + } + return NULL; +} + +const machine_pin_af_obj_t *pin_find_af(const machine_pin_obj_t *pin, uint8_t fn) { + const machine_pin_af_obj_t *af_obj = NULL; + + for (int i = 0; i < pin->af_list_len; ++i) { + af_obj = &pin->af_list[i]; + if (af_obj->af_mode == fn) { + return af_obj; + } + } + + return NULL; +} + +const machine_pin_af_obj_t *pin_find_af_by_index(const machine_pin_obj_t *pin, mp_uint_t af_idx) { + // TODO: Implement pin_find_af_by_index function + return NULL; +} + +const machine_pin_af_obj_t *pin_find_af_by_name(const machine_pin_obj_t *pin, const char *name) { + // TODO: Implement pin_find_af_by_name function + return NULL; +} diff --git a/ports/mimxrt/pin.h b/ports/mimxrt/pin.h index cfb1e6b57..268b505b3 100644 --- a/ports/mimxrt/pin.h +++ b/ports/mimxrt/pin.h @@ -27,12 +27,32 @@ #ifndef MICROPY_INCLUDED_MIMXRT_PIN_H #define MICROPY_INCLUDED_MIMXRT_PIN_H -#include "fsl_gpio.h" +#include <stdint.h> #include "py/obj.h" +#include "fsl_gpio.h" + +// ------------------------------------------------------------------------------------------------------------------ // + +#define IS_GPIO_MODE(MODE) (((MODE) == PIN_MODE_IN) || \ + ((MODE) == PIN_MODE_OUT) || \ + ((MODE) == PIN_MODE_OPEN_DRAIN) || \ + ((MODE) == PIN_MODE_ALT)) + +#define IS_GPIO_DRIVE(DRIVE) (((DRIVE) == PIN_DRIVE_OFF) || \ + ((DRIVE) == PIN_DRIVE_POWER_0) || \ + ((DRIVE) == PIN_DRIVE_POWER_1) || \ + ((DRIVE) == PIN_DRIVE_POWER_2) || \ + ((DRIVE) == PIN_DRIVE_POWER_3) || \ + ((DRIVE) == PIN_DRIVE_POWER_4) || \ + ((DRIVE) == PIN_DRIVE_POWER_5) || \ + ((DRIVE) == PIN_DRIVE_POWER_6)) + +// ------------------------------------------------------------------------------------------------------------------ // enum { PIN_MODE_IN = 0, PIN_MODE_OUT, + PIN_MODE_OPEN_DRAIN, PIN_MODE_ALT, }; @@ -47,13 +67,38 @@ enum { PIN_AF_MODE_ALT8, }; +enum { + PIN_PULL_DOWN_100K = 0, + PIN_PULL_UP_47K, + PIN_PULL_UP_100K, + PIN_PULL_UP_22K, + PIN_PULL_DISABLED, + PIN_PULL_HOLD, +}; + +enum { + PIN_DRIVE_OFF = 0b000, + PIN_DRIVE_POWER_0, // R0 (150 Ohm @3.3V / 260 Ohm @ 1.8V) + PIN_DRIVE_POWER_1, // R0/2 + PIN_DRIVE_POWER_2, // R0/3 + PIN_DRIVE_POWER_3, // R0/4 + PIN_DRIVE_POWER_4, // R0/5 + PIN_DRIVE_POWER_5, // R0/6 + PIN_DRIVE_POWER_6, // R0/7 +}; + + + + +// ------------------------------------------------------------------------------------------------------------------ // + typedef struct { mp_obj_base_t base; qstr name; // port name - uint32_t af_mode; // alternate function + uint8_t af_mode; // alternate function void *instance; // pointer to peripheral instance for alternate function uint32_t pad_config; // pad configuration for alternate function -} pin_af_obj_t; +} machine_pin_af_obj_t; typedef struct { mp_obj_base_t base; @@ -62,39 +107,38 @@ typedef struct { uint32_t pin; // pin number uint32_t muxRegister; uint32_t configRegister; - uint32_t mode; // current pin mode - uint32_t af_mode; // current alternate function mode size_t af_list_len; // length of available alternate functions list - const pin_af_obj_t *af_list; // pointer tolist with alternate functions -} pin_obj_t; - -extern const mp_obj_type_t pin_type; -extern const mp_obj_type_t pin_af_type; - -#define PIN_AF(_name, _af_mode, _instance, _pad_config) \ - { \ - .base = { &pin_af_type }, \ - .name = MP_QSTR_##_name, \ - .af_mode = (uint32_t)(_af_mode), \ - .instance = (void *)(_instance), \ - .pad_config = (uint32_t)(_pad_config), \ - } \ - -#define PIN(_name, _gpio, _pin, _af_list) \ - { \ - .base = { &pin_type }, \ - .name = MP_QSTR_##_name, \ - .gpio = (_gpio), \ - .pin = (uint32_t)(_pin), \ - .muxRegister = (uint32_t)&(IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_##_name]), \ - .configRegister = (uint32_t)&(IOMUXC->SW_PAD_CTL_PAD[kIOMUXC_SW_PAD_CTL_PAD_##_name]), \ - .mode = PIN_MODE_IN, \ - .af_mode = PIN_AF_MODE_ALT5, \ - .af_list_len = (size_t)(sizeof((_af_list)) / sizeof(pin_af_obj_t)), \ - .af_list = (_af_list), \ - } \ + const machine_pin_af_obj_t *af_list; // pointer tolist with alternate functions +} machine_pin_obj_t; + +// ------------------------------------------------------------------------------------------------------------------ // + +extern const mp_obj_type_t machine_pin_type; +extern const mp_obj_type_t machine_pin_af_type; + +// ------------------------------------------------------------------------------------------------------------------ // // Include board specific pins -#include "pins.h" +#include "genhdr/pins.h" // pins.h must included at this location + +extern const machine_pin_obj_t *machine_pin_board_pins[]; +extern const uint32_t num_board_pins; + +extern const mp_obj_type_t machine_pin_board_pins_obj_type; +extern const mp_obj_type_t machine_pin_cpu_pins_obj_type; + +extern const mp_obj_dict_t machine_pin_cpu_pins_locals_dict; +extern const mp_obj_dict_t machine_pin_board_pins_locals_dict; + +// ------------------------------------------------------------------------------------------------------------------ // + +void pin_init(void); +uint32_t pin_get_mode(const machine_pin_obj_t *pin); +uint32_t pin_get_af(const machine_pin_obj_t *pin); +const machine_pin_obj_t *pin_find(mp_obj_t user_obj); +const machine_pin_obj_t *pin_find_named_pin(const mp_obj_dict_t *named_pins, mp_obj_t name); +const machine_pin_af_obj_t *pin_find_af(const machine_pin_obj_t *pin, uint8_t fn); +const machine_pin_af_obj_t *pin_find_af_by_index(const machine_pin_obj_t *pin, mp_uint_t af_idx); +const machine_pin_af_obj_t *pin_find_af_by_name(const machine_pin_obj_t *pin, const char *name); #endif // MICROPY_INCLUDED_MIMXRT_PIN_H diff --git a/ports/mimxrt/tusb_port.c b/ports/mimxrt/tusb_port.c index 0d73b0923..2b1ccabbe 100644 --- a/ports/mimxrt/tusb_port.c +++ b/ports/mimxrt/tusb_port.c @@ -76,7 +76,7 @@ static const uint8_t usbd_desc_cfg[USBD_DESC_LEN] = { static const char *const usbd_desc_str[] = { [USBD_STR_MANUF] = "MicroPython", - [USBD_STR_PRODUCT] = "Board in FS mode", + [USBD_STR_PRODUCT] = "Board in FS mode", // Todo: fix string to indicate that product is running in High Speed mode [USBD_STR_SERIAL] = "000000000000", // TODO [USBD_STR_CDC] = "Board CDC", }; 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