diff options
Diffstat (limited to 'ports/esp8266')
| -rw-r--r-- | ports/esp8266/esppwm.c | 2 | ||||
| -rw-r--r-- | ports/esp8266/hspi_register.h | 2 | ||||
| -rw-r--r-- | ports/esp8266/uart.c | 4 |
3 files changed, 4 insertions, 4 deletions
diff --git a/ports/esp8266/esppwm.c b/ports/esp8266/esppwm.c index 3b705fb94..d7ac44a17 100644 --- a/ports/esp8266/esppwm.c +++ b/ports/esp8266/esppwm.c @@ -165,7 +165,7 @@ pwm_start(void) { } } PWM_DBG("2channel:%d,single[0]:%d,[1]:%d,[2]:%d,[3]:%d\n", *local_channel, local_single[0].h_time, local_single[1].h_time, local_single[2].h_time, local_single[3].h_time); - // step 4: cacl delt time + // step 4: calc delta time for (i = *local_channel - 1; i > 0; i--) { local_single[i].h_time -= local_single[i - 1].h_time; } diff --git a/ports/esp8266/hspi_register.h b/ports/esp8266/hspi_register.h index 50ef2fdca..0d0cf2f74 100644 --- a/ports/esp8266/hspi_register.h +++ b/ports/esp8266/hspi_register.h @@ -79,7 +79,7 @@ #define SPI_MOSI_DELAY_NUM 0x00000007 #define SPI_MOSI_DELAY_NUM_S 23 #define SPI_MOSI_DELAY_MODE 0x00000003 //mode 0 : posedge; data set at positive edge of clk - //mode 1 : negedge + 1 cycle delay, only if freq<10MHz ; data set at negitive edge of clk + //mode 1 : negedge + 1 cycle delay, only if freq<10MHz ; data set at negative edge of clk //mode 2 : Do not use this mode. #define SPI_MOSI_DELAY_MODE_S 21 #define SPI_MISO_DELAY_NUM 0x00000007 diff --git a/ports/esp8266/uart.c b/ports/esp8266/uart.c index 117cd1bf6..f761ecfd7 100644 --- a/ports/esp8266/uart.c +++ b/ports/esp8266/uart.c @@ -3,7 +3,7 @@ * * FileName: uart.c * - * Description: Two UART mode configration and interrupt handler. + * Description: Two UART mode configuration and interrupt handler. * Check your hardware connection while use this mode. * * Modification history: @@ -164,7 +164,7 @@ uart_os_config(int uart) { *******************************************************************************/ static void uart0_rx_intr_handler(void *para) { - /* uart0 and uart1 intr combine togther, when interrupt occur, see reg 0x3ff20020, bit2, bit0 represents + /* uart0 and uart1 intr combine together, when interrupt occur, see reg 0x3ff20020, bit2, bit0 represents * uart1 and uart0 respectively */ |