diff options
Diffstat (limited to 'ports/stm32/powerctrl.c')
| -rw-r--r-- | ports/stm32/powerctrl.c | 20 |
1 files changed, 4 insertions, 16 deletions
diff --git a/ports/stm32/powerctrl.c b/ports/stm32/powerctrl.c index 66fd691a8..d05c37737 100644 --- a/ports/stm32/powerctrl.c +++ b/ports/stm32/powerctrl.c @@ -178,25 +178,13 @@ set_clk: } // Determine the bus clock dividers - if (ahb != 0) { - // Note: AHB freq required to be >= 14.2MHz for USB operation - RCC_ClkInitStruct.AHBCLKDivider = calc_ahb_div(sysclk / ahb); - } else { - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - } + // Note: AHB freq required to be >= 14.2MHz for USB operation + RCC_ClkInitStruct.AHBCLKDivider = calc_ahb_div(sysclk / ahb); #if !defined(STM32H7) ahb = sysclk >> AHBPrescTable[RCC_ClkInitStruct.AHBCLKDivider >> RCC_CFGR_HPRE_Pos]; #endif - if (apb1 != 0) { - RCC_ClkInitStruct.APB1CLKDivider = calc_apb_div(ahb / apb1); - } else { - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - } - if (apb2 != 0) { - RCC_ClkInitStruct.APB2CLKDivider = calc_apb_div(ahb / apb2); - } else { - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - } + RCC_ClkInitStruct.APB1CLKDivider = calc_apb_div(ahb / apb1); + RCC_ClkInitStruct.APB2CLKDivider = calc_apb_div(ahb / apb2); #if MICROPY_HW_CLK_LAST_FREQ // Save the bus dividers for use later |