summaryrefslogtreecommitdiff
path: root/ports/stm32/powerctrlboot.c
diff options
context:
space:
mode:
Diffstat (limited to 'ports/stm32/powerctrlboot.c')
-rw-r--r--ports/stm32/powerctrlboot.c12
1 files changed, 10 insertions, 2 deletions
diff --git a/ports/stm32/powerctrlboot.c b/ports/stm32/powerctrlboot.c
index 220375a51..c7802a558 100644
--- a/ports/stm32/powerctrlboot.c
+++ b/ports/stm32/powerctrlboot.c
@@ -218,13 +218,21 @@ void SystemClock_Config(void) {
// Configure PLL1 for use as system clock.
LL_RCC_PLL1_ConfigDomain_SYS(pll1_source, MICROPY_HW_CLK_PLLM, MICROPY_HW_CLK_PLLN, MICROPY_HW_CLK_PLLP);
- LL_RCC_PLL1_SetQ(MICROPY_HW_CLK_PLLQ);
- LL_RCC_PLL1_SetR(MICROPY_HW_CLK_PLLR);
LL_RCC_PLL1_SetFRACN(MICROPY_HW_CLK_PLLFRAC);
LL_RCC_PLL1_SetVCOInputRange(MICROPY_HW_CLK_PLLVCI_LL);
LL_RCC_PLL1_SetVCOOutputRange(MICROPY_HW_CLK_PLLVCO_LL);
LL_RCC_PLL1P_Enable();
+ #if defined(MICROPY_HW_CLK_PLLQ)
+ LL_RCC_PLL1_SetQ(MICROPY_HW_CLK_PLLQ);
+ LL_RCC_PLL1Q_Enable();
+ #endif
+
+ #if defined(MICROPY_HW_CLK_PLLR)
+ LL_RCC_PLL1_SetR(MICROPY_HW_CLK_PLLR);
+ LL_RCC_PLL1R_Enable();
+ #endif
+
// Enable PLL1.
LL_RCC_PLL1_Enable();
while (!LL_RCC_PLL1_IsReady()) {