diff options
Diffstat (limited to 'ports/stm32/rtc.c')
| -rw-r--r-- | ports/stm32/rtc.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/ports/stm32/rtc.c b/ports/stm32/rtc.c index aacfc3805..874e427cf 100644 --- a/ports/stm32/rtc.c +++ b/ports/stm32/rtc.c @@ -91,6 +91,15 @@ STATIC bool rtc_need_init_finalise = false; #define RCC_BDCR_LSEON RCC_CSR_LSEON #define RCC_BDCR_LSERDY RCC_CSR_LSERDY #define RCC_BDCR_LSEBYP RCC_CSR_LSEBYP +#elif defined(STM32L1) +#define BDCR CR +#define RCC_BDCR_RTCEN RCC_CSR_RTCEN +#define RCC_BDCR_RTCSEL RCC_CSR_RTCSEL +#define RCC_BDCR_RTCSEL_0 RCC_CSR_RTCSEL_0 +#define RCC_BDCR_RTCSEL_1 RCC_CSR_RTCSEL_1 +#define RCC_BDCR_LSEON RCC_CSR_LSEON +#define RCC_BDCR_LSERDY RCC_CSR_LSERDY +#define RCC_BDCR_LSEBYP RCC_CSR_LSEBYP #endif void rtc_init_start(bool force_init) { @@ -664,7 +673,15 @@ mp_obj_t pyb_rtc_wakeup(size_t n_args, const mp_obj_t *args) { wucksel -= 1; } if (div <= 16) { + #if defined(STM32L1) + if (rtc_use_lse) { + wut = LSE_VALUE / div * ms / 1000; + } else { + wut = LSI_VALUE / div * ms / 1000; + } + #else wut = 32768 / div * ms / 1000; + #endif } else { // use 1Hz clock wucksel = 4; |