diff options
Diffstat (limited to 'ports/stm32/uart.c')
| -rw-r--r-- | ports/stm32/uart.c | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/ports/stm32/uart.c b/ports/stm32/uart.c index 83eef705a..e828f2538 100644 --- a/ports/stm32/uart.c +++ b/ports/stm32/uart.c @@ -406,6 +406,53 @@ bool uart_init(pyb_uart_obj_t *uart_obj, uint32_t baudrate) { } */ +uint32_t uart_get_baudrate(pyb_uart_obj_t *self) { + uint32_t uart_clk = 0; + + #if defined(STM32F0) + uart_clk = HAL_RCC_GetPCLK1Freq(); + #elif defined(STM32F7) || defined(STM32H7) + UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED; + UART_GETCLOCKSOURCE(&self->uart, clocksource); + switch (clocksource) { + #if defined(STM32H7) + case UART_CLOCKSOURCE_D2PCLK1: uart_clk = HAL_RCC_GetPCLK1Freq(); break; + case UART_CLOCKSOURCE_D3PCLK1: uart_clk = HAL_RCC_GetPCLK1Freq(); break; + case UART_CLOCKSOURCE_D2PCLK2: uart_clk = HAL_RCC_GetPCLK2Freq(); break; + #else + case UART_CLOCKSOURCE_PCLK1: uart_clk = HAL_RCC_GetPCLK1Freq(); break; + case UART_CLOCKSOURCE_PCLK2: uart_clk = HAL_RCC_GetPCLK2Freq(); break; + case UART_CLOCKSOURCE_SYSCLK: uart_clk = HAL_RCC_GetSysClockFreq(); break; + #endif + #if defined(STM32H7) + case UART_CLOCKSOURCE_CSI: uart_clk = CSI_VALUE; break; + #endif + case UART_CLOCKSOURCE_HSI: uart_clk = HSI_VALUE; break; + case UART_CLOCKSOURCE_LSE: uart_clk = LSE_VALUE; break; + #if defined(STM32H7) + case UART_CLOCKSOURCE_PLL2: + case UART_CLOCKSOURCE_PLL3: + #endif + case UART_CLOCKSOURCE_UNDEFINED: break; + } + #else + if (self->uart.Instance == USART1 + #if defined(USART6) + || self->uart.Instance == USART6 + #endif + ) { + uart_clk = HAL_RCC_GetPCLK2Freq(); + } else { + uart_clk = HAL_RCC_GetPCLK1Freq(); + } + #endif + + // This formula assumes UART_OVERSAMPLING_16 + uint32_t baudrate = uart_clk / self->uart.Instance->BRR; + + return baudrate; +} + mp_uint_t uart_rx_any(pyb_uart_obj_t *self) { int buffer_bytes = self->read_buf_head - self->read_buf_tail; if (buffer_bytes < 0) { |