diff options
Diffstat (limited to 'stmhal/mphalport.c')
| -rw-r--r-- | stmhal/mphalport.c | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/stmhal/mphalport.c b/stmhal/mphalport.c index 6893701f5..dff781ff2 100644 --- a/stmhal/mphalport.c +++ b/stmhal/mphalport.c @@ -21,10 +21,6 @@ NORETURN void mp_hal_raise(HAL_StatusTypeDef status) { mp_raise_OSError(mp_hal_status_to_errno_table[status]); } -void mp_hal_set_interrupt_char(int c) { - usb_vcp_set_interrupt_char(c); -} - int mp_hal_stdin_rx_chr(void) { for (;;) { #if 0 @@ -43,7 +39,7 @@ int mp_hal_stdin_rx_chr(void) { } else if (MP_STATE_PORT(pyb_stdio_uart) != NULL && uart_rx_any(MP_STATE_PORT(pyb_stdio_uart))) { return uart_rx_char(MP_STATE_PORT(pyb_stdio_uart)); } - __WFI(); + MICROPY_EVENT_POLL_HOOK } } @@ -76,6 +72,10 @@ void mp_hal_stdout_tx_strn_cooked(const char *str, size_t len) { void mp_hal_ticks_cpu_enable(void) { if (!mp_hal_ticks_cpu_enabled) { CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + #if defined(__CORTEX_M) && __CORTEX_M == 7 + // on Cortex-M7 we must unlock the DWT before writing to its registers + DWT->LAR = 0xc5acce55; + #endif DWT->CYCCNT = 0; DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; mp_hal_ticks_cpu_enabled = true; @@ -110,6 +110,10 @@ void mp_hal_gpio_clock_enable(GPIO_TypeDef *gpio) { #endif #if defined(GPIOG) && defined(__GPIOG_CLK_ENABLE) } else if (gpio == GPIOG) { + #if defined(STM32L476xx) || defined(STM32L486xx) + // Port G pins 2 thru 15 are powered using VddIO2 on these MCUs. + HAL_PWREx_EnableVddIO2(); + #endif __GPIOG_CLK_ENABLE(); #endif #ifdef __GPIOH_CLK_ENABLE |