diff options
Diffstat (limited to 'stmhal/system_stm32.c')
| -rw-r--r-- | stmhal/system_stm32.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/stmhal/system_stm32.c b/stmhal/system_stm32.c index ed843af82..b71a03181 100644 --- a/stmhal/system_stm32.c +++ b/stmhal/system_stm32.c @@ -331,12 +331,8 @@ void SystemClock_Config(void) regarding system frequency refer to product datasheet. */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); #elif defined(MCU_SERIES_L4) - /* Enable the LSE Oscillator */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.LSEState = RCC_LSE_ON; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - __fatal_error("HAL_RCC_OscConfig"); - } + // Configure LSE Drive Capability + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); #endif /* Enable HSE Oscillator and activate PLL with HSE as source */ @@ -464,6 +460,8 @@ void SystemClock_Config(void) PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_PLLSAI1; + PeriphClkInitStruct.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI; + PeriphClkInitStruct.PLLSAI1.PLLSAI1M = 1; PeriphClkInitStruct.PLLSAI1.PLLSAI1N = 24; PeriphClkInitStruct.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; PeriphClkInitStruct.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; |