| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2025-09-19 | py/emitinlinerv32: Add Zba opcodes to the inline assembler. | Alessandro Gatti | |
| This commit adds support for Zba opcodes to the RV32 inline assembler. Three new opcodes were added, SH1ADD, SH2ADD, and SH3ADD, which performs a scaled addition (by 1, 2, or 3 bits respectively). At the moment only qemu's VIRT_RV32 and rp2's RPI_PICO2/RPI_PICO2_W ports support these opcodes (the latter only when using the RISCV variant). Signed-off-by: Alessandro Gatti <a.gatti@frob.it> | |||
| 2025-01-02 | py/emitinlinerv32: Add inline assembler support for RV32. | Alessandro Gatti | |
| This commit adds support for writing inline assembler functions when targeting a RV32IMC processor. Given that this takes up a bit of rodata space due to its large instruction decoding table and its extensive error messages, it is enabled by default only on offline targets such as mpy-cross and the qemu port. Signed-off-by: Alessandro Gatti <a.gatti@frob.it> | |||
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index : user/sven/micropython.git | |
| The MicroPython project | Sven Wegener |
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