diff options
| author | Linus Torvalds <torvalds@ppc970.osdl.org> | 2004-07-04 20:54:07 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2004-07-04 20:54:07 -0700 |
| commit | 07f0a148b27e12aa11086153ca9425d311e20522 (patch) | |
| tree | 40afcc0d62ed8e82dc189bb53248b45351bf9e30 | |
| parent | 8feceb0097be6a7a3bbf35290a94585fecd16c58 (diff) | |
| parent | 930e06f4c476a344797190aa099ff602eec10d8f (diff) | |
Merge bk://drm.bkbits.net/drm-2.6
into ppc970.osdl.org:/home/torvalds/v2.6/linux
| -rw-r--r-- | drivers/char/drm/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/char/drm/radeon.h | 2 | ||||
| -rw-r--r-- | drivers/char/drm/radeon_state.c | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/drivers/char/drm/Kconfig b/drivers/char/drm/Kconfig index 087ad5d29c68..13797ca0c2ab 100644 --- a/drivers/char/drm/Kconfig +++ b/drivers/char/drm/Kconfig @@ -76,7 +76,7 @@ config DRM_SIS tristate "SiS video cards" depends on DRM && AGP help - Choose this option if you have a SiS 630 or compatibel video + Choose this option if you have a SiS 630 or compatible video chipset. If M is selected the module will be called sis. AGP support is required for this driver to work. diff --git a/drivers/char/drm/radeon.h b/drivers/char/drm/radeon.h index 54fac7940015..83902f86942b 100644 --- a/drivers/char/drm/radeon.h +++ b/drivers/char/drm/radeon.h @@ -141,7 +141,7 @@ do { \ radeon_do_cleanup_pageflip( dev ); \ } \ radeon_mem_release( filp, dev_priv->gart_heap ); \ - radeon_mem_release( filp, dev_priv->fb_heap ); \ + radeon_mem_release( filp, dev_priv->fb_heap ); \ } \ } while (0) diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c index 64143d190c16..a1da7c3d5513 100644 --- a/drivers/char/drm/radeon_state.c +++ b/drivers/char/drm/radeon_state.c @@ -563,7 +563,7 @@ static struct { { R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" }, { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" }, { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" }, - { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_1" }, + { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" }, { R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" }, }; |