diff options
| author | Imre Deak <imre.deak@intel.com> | 2025-12-15 21:23:49 +0200 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2025-12-19 16:46:40 +0200 |
| commit | 2fb850a6aeb20b6a28c23dbddf1eaa704abb9ce9 (patch) | |
| tree | 5283e7ab6b312594cec616b9bc7dd6d374c10e6f | |
| parent | b1ec2916c929a58b533b7f652d0162299d8a6398 (diff) | |
drm/i915/dp: Use the effective data rate for DP compressed BW calculation
Use intel_dp_effective_data_rate() to calculate the required link BW for
compressed streams on non-UHBR DP-SST links. This ensures that the BW is
calculated the same way for all DP output types and DSC/non-DSC modes,
during mode validation as well as during state computation.
This approach also allows for accounting with BW overhead due to DSC,
FEC being enabled on a link. Acounting for these will be added by
follow-up changes.
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20251215192357.172201-10-imre.deak@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dp.c | 27 |
1 files changed, 16 insertions, 11 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 79373b84d30f..a2939843a72a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2026,15 +2026,19 @@ static bool intel_dp_dsc_supports_format(const struct intel_connector *connector return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format); } -static bool is_bw_sufficient_for_dsc_config(int dsc_bpp_x16, u32 link_clock, - u32 lane_count, u32 mode_clock, - enum intel_output_format output_format, - int timeslots) +static bool is_bw_sufficient_for_dsc_config(struct intel_dp *intel_dp, + int link_clock, int lane_count, + int mode_clock, int mode_hdisplay, + int dsc_slice_count, int link_bpp_x16, + unsigned long bw_overhead_flags) { - u32 available_bw, required_bw; + int available_bw; + int required_bw; - available_bw = (link_clock * lane_count * timeslots * 16) / 8; - required_bw = dsc_bpp_x16 * (intel_dp_mode_to_fec_clock(mode_clock)); + available_bw = intel_dp_max_link_data_rate(intel_dp, link_clock, lane_count); + required_bw = intel_dp_link_required(link_clock, lane_count, + mode_clock, mode_hdisplay, + link_bpp_x16, bw_overhead_flags); return available_bw >= required_bw; } @@ -2082,11 +2086,12 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp, if (ret) continue; } else { - if (!is_bw_sufficient_for_dsc_config(dsc_bpp_x16, link_rate, - lane_count, + if (!is_bw_sufficient_for_dsc_config(intel_dp, + link_rate, lane_count, adjusted_mode->crtc_clock, - pipe_config->output_format, - timeslots)) + adjusted_mode->hdisplay, + pipe_config->dsc.slice_count, + dsc_bpp_x16, 0)) continue; } |