[ARM PATCH] 2577/1: more ixp2000 comment work (typo fixes and annotations)

Patch from Lennert Buytenhek

Fix two more ixp2000 typos, and place some comments in ixp2000-regs.h
to remind the developer that the virtual addresses of some of the io
mappings have been hardcoded in various assembly files.  (I've been
bitten by this too many times now.)

Signed-off-by: Lennert Buytenhek
Signed-off-by: Russell King

3 files changed, 15 insertions, 6 deletions

diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c
index 02cb77e8b59f..4f3c3d5c781c 100644
--- a/arch/arm/mach-ixp2000/core.c
+++ b/arch/arm/mach-ixp2000/core.c
@@ -376,7 +376,9 @@ void __init ixp2000_init_irq(void)
 	set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
 
 	/*
-	 * Enable PCI irq
+	 * Enable PCI irqs.  The actual PCI[AB] decoding is done in
+	 * entry-macro.S, so we don't need a chained handler for the
+	 * PCI interrupt source.
 	 */
 	ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
 	for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
diff --git a/include/asm-arm/arch-ixp2000/ixp2000-regs.h b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
index ef50b38f7d9f..fe1f9158e9aa 100644
--- a/include/asm-arm/arch-ixp2000/ixp2000-regs.h
+++ b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
@@ -22,7 +22,7 @@
  * Static I/O regions.
  *
  * Most of the registers are clumped in 4K regions spread throughout
- * the 0xc000000 -> 0xc0100000 address range, but we just map in
+ * the 0xc0000000 -> 0xc0100000 address range, but we just map in
  * the whole range using a single 1 MB section instead of small
  * 4K pages.  This has two advantages for us:
  *
@@ -32,7 +32,11 @@
  *    as required per erratum #66.  We accomplish this by using a
  *    new MT_IXP2000_DEVICE memory type with the bits set as required.
  *
- * CAP stands for CSR Access Proxy
+ * CAP stands for CSR Access Proxy.
+ *
+ * If you change the virtual address of this mapping, please propagate
+ * the change to arch/arm/kernel/debug.S, which hardcodes the virtual
+ * address of the UART located in this region.
  */
 
 #define	IXP2000_CAP_PHYS_BASE		0xc0000000
@@ -50,7 +54,10 @@
 #define	IXP2000_GPIO_VIRT_BASE		0Xfef10000
 
 /*
- * Devices outside of the 0xc0000000 -> 0xc0100000 range
+ * Devices outside of the 0xc0000000 -> 0xc0100000 range.  The virtual
+ * addresses of the INTCTL and PCI_CSR mappings are hardcoded in
+ * entry-macro.S, so if you ever change these please propagate
+ * the change.
  */
 #define IXP2000_INTCTL_PHYS_BASE	0xd6000000
 #define	IXP2000_INTCTL_VIRT_BASE	0xfee00000
@@ -203,7 +210,7 @@
 
 #define IXP2000_PCICNTL_PNR		(1<<17)	/* PCI not Reset bit of PCI_CONTROL */
 #define IXP2000_PCICNTL_PCF		(1<<28)	/* PCI Centrolfunction bit */
-#define IXP2000_XSCALE_INT		(1<<1)	/* Interrupt from  XScale to PCI */
+#define IXP2000_XSCALE_INT		(1<<1)	/* Interrupt from XScale to PCI */
 
 /* These are from the IRQ register in the PCI ISR register */
 #define PCI_CONTROL_BE_DEO		(1 << 22)	/* Big Endian Data Enable Out */
diff --git a/include/asm-arm/arch-ixp2000/platform.h b/include/asm-arm/arch-ixp2000/platform.h
index 7118a843ab12..509e44d528d8 100644
--- a/include/asm-arm/arch-ixp2000/platform.h
+++ b/include/asm-arm/arch-ixp2000/platform.h
@@ -20,7 +20,7 @@
  * to on-chip I/O register to not complete fully. What this means is
  * that if you have a write to on-chip I/O followed by a back-to-back
  * read or write, the first write will happen twice. OR...if it's
- * not a back-to-back trasaction, the read or write will generate 
+ * not a back-to-back transaction, the read or write will generate
  * incorrect data.
  *
  * The official work around for this is to set the on-chip I/O regions