diff options
| author | Gert Wollny <gert.wollny@collabora.com> | 2025-11-19 17:45:51 +0100 |
|---|---|---|
| committer | Christian Gmeiner <cgmeiner@igalia.com> | 2026-01-06 16:43:19 +0100 |
| commit | 6a0b99e9fb45f403c3097a9047963d2dd5b0fab2 (patch) | |
| tree | 5415d6dd436cf1f9505ac486e8f2a47c4d75647a | |
| parent | 85ba57ad88cf96b2fb4cf6c81639c7907bf3cd94 (diff) | |
drm/etnaviv: Add module parameter to force PPU flop reset
v2: Check for feature PIPE_3D when forcing PPU flop reset (Lucas)
v3: - drop use of ppu_flop_reset enum (Christian Gmeiner)
- don't initialize module parameter to zero (checkpatch)
- avoid multi-line string in warning message (checkpatch)
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Tested-by: Marek Vasut <marek.vasut@mailbox.org> # STM32MP255C DHCOS DHSBC
Link: https://patch.msgid.link/20251119164624.9297-6-gert.wollny@collabora.com
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
| -rw-r--r-- | drivers/gpu/drm/etnaviv/etnaviv_flop_reset.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_flop_reset.c b/drivers/gpu/drm/etnaviv/etnaviv_flop_reset.c index 2ae6532a51ab..58d957ee861d 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_flop_reset.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_flop_reset.c @@ -15,6 +15,9 @@ #include "etnaviv_flop_reset.h" +static int etnaviv_force_flop_reset; +module_param_named(force_flop_reset, etnaviv_force_flop_reset, int, 0); + #define PPU_IMAGE_STRIDE 64 #define PPU_IMAGE_XSIZE 64 #define PPU_IMAGE_YSIZE 6 @@ -150,6 +153,19 @@ bool etnaviv_flop_reset_ppu_require(const struct etnaviv_chip_identity *chip_id) return true; } + if (etnaviv_force_flop_reset) { + if (!(chip_id->features & chipFeatures_PIPE_3D)) { + pr_warn("Etnaviv: model: 0x%04x, revision: 0x%04x does not support PIPE_3D\n", + chip_id->model, chip_id->revision); + pr_warn("Request to force PPU flop reset ignored.\n"); + return false; + } + + pr_info("Force PPU flop reset for model: 0x%04x, revision: 0x%04x\n", + chip_id->model, chip_id->revision); + return true; + } + return false; } |