diff options
| author | Alexander Viro <viro@parcelfarce.linux.theplanet.co.uk> | 2004-02-25 18:07:47 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2004-02-25 18:07:47 -0800 |
| commit | 7265df88a1fc37644ea0b4dddcc8ce4f9b227ee4 (patch) | |
| tree | d6e68459306a55f1f0222afd468d8ac65ce79c02 | |
| parent | 6c34bb1713cc2c73eb5086eac021b8dbde57c4bc (diff) | |
[PATCH] Clean up __cacheline_aligned
arm-26, ppc, sparc, sparc64 and sh have per-arch definitions of
__cacheline_aligned that are identical to default. And yes, removal is
safe - all users of __cacheline_aligned actually pull linux/cache.h in.
| -rw-r--r-- | include/asm-arm26/cache.h | 8 | ||||
| -rw-r--r-- | include/asm-ppc/cache.h | 8 | ||||
| -rw-r--r-- | include/asm-sh/cache.h | 8 | ||||
| -rw-r--r-- | include/asm-sparc/cache.h | 8 | ||||
| -rw-r--r-- | include/asm-sparc64/cache.h | 8 |
5 files changed, 0 insertions, 40 deletions
diff --git a/include/asm-arm26/cache.h b/include/asm-arm26/cache.h index d95112e028a6..f52ca1b808cd 100644 --- a/include/asm-arm26/cache.h +++ b/include/asm-arm26/cache.h @@ -8,12 +8,4 @@ #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) #define SMP_CACHE_BYTES L1_CACHE_BYTES -#ifdef MODULE -#define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES))) -#else -#define __cacheline_aligned \ - __attribute__((__aligned__(L1_CACHE_BYTES), \ - __section__(".data.cacheline_aligned"))) -#endif - #endif diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h index 6a3f4c05dc67..1fcf0f3e7b87 100644 --- a/include/asm-ppc/cache.h +++ b/include/asm-ppc/cache.h @@ -30,14 +30,6 @@ #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) #define L1_CACHE_PAGES 8 -#ifdef MODULE -#define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES))) -#else -#define __cacheline_aligned \ - __attribute__((__aligned__(L1_CACHE_BYTES), \ - __section__(".data.cacheline_aligned"))) -#endif - #ifndef __ASSEMBLY__ extern void clean_dcache_range(unsigned long start, unsigned long stop); extern void flush_dcache_range(unsigned long start, unsigned long stop); diff --git a/include/asm-sh/cache.h b/include/asm-sh/cache.h index f8cf61f9869a..9decb1ced217 100644 --- a/include/asm-sh/cache.h +++ b/include/asm-sh/cache.h @@ -21,14 +21,6 @@ #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) -#ifdef MODULE -#define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES))) -#else -#define __cacheline_aligned \ - __attribute__((__aligned__(L1_CACHE_BYTES), \ - __section__(".data.cacheline_aligned"))) -#endif - #define L1_CACHE_SHIFT_MAX 5 /* largest L1 which this arch supports */ struct cache_info { diff --git a/include/asm-sparc/cache.h b/include/asm-sparc/cache.h index 86fd491b42a6..e6316fd7e1a4 100644 --- a/include/asm-sparc/cache.h +++ b/include/asm-sparc/cache.h @@ -17,14 +17,6 @@ #define SMP_CACHE_BYTES 32 -#ifdef MODULE -#define __cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES))) -#else -#define __cacheline_aligned \ - __attribute__((__aligned__(SMP_CACHE_BYTES), \ - __section__(".data.cacheline_aligned"))) -#endif - /* Direct access to the instruction cache is provided through and * alternate address space. The IDC bit must be off in the ICCR on * HyperSparcs for these accesses to work. The code below does not do diff --git a/include/asm-sparc64/cache.h b/include/asm-sparc64/cache.h index c4ba581b7af1..ade5ec3bfd5a 100644 --- a/include/asm-sparc64/cache.h +++ b/include/asm-sparc64/cache.h @@ -14,12 +14,4 @@ #define SMP_CACHE_BYTES_SHIFT 6 #define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT) /* L2 cache line size. */ -#ifdef MODULE -#define __cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES))) -#else -#define __cacheline_aligned \ - __attribute__((__aligned__(SMP_CACHE_BYTES), \ - __section__(".data.cacheline_aligned"))) -#endif - #endif |