Merge hostme.bitkeeper.com:/ua/repos/g/gkernel/linus-2.5

into hostme.bitkeeper.com:/ua/repos/g/gkernel/net-drivers-2.5

7 files changed, 139 insertions, 2697 deletions

diff --git a/drivers/net/8139too.c b/drivers/net/8139too.c
index f62b4f5fb0b8..f9d076567706 100644
--- a/drivers/net/8139too.c
+++ b/drivers/net/8139too.c
@@ -217,6 +217,7 @@ typedef enum {
 	DFE538TX,
 	DFE690TXD,
 	FE2000VX,
+	ALLIED8139,
 	RTL8129,
 } board_t;
 
@@ -235,6 +236,7 @@ static struct {
 	{ "D-Link DFE-538TX (RealTek RTL8139)", RTL8139_CAPS },
 	{ "D-Link DFE-690TXD (RealTek RTL8139)", RTL8139_CAPS },
 	{ "AboCom FE2000VX (RealTek RTL8139)", RTL8139_CAPS },
+	{ "Allied Telesyn 8139 CardBus", RTL8139_CAPS },
 	{ "RealTek RTL8129", RTL8129_CAPS },
 };
 
@@ -249,6 +251,7 @@ static struct pci_device_id rtl8139_pci_tbl[] __devinitdata = {
 	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DFE538TX },
 	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DFE690TXD },
 	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, FE2000VX },
+	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ALLIED8139 },
 
 #ifdef CONFIG_8139TOO_8129
 	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
diff --git a/drivers/net/Config.in b/drivers/net/Config.in
index 8e0c833cad1e..3209bc3cef17 100644
--- a/drivers/net/Config.in
+++ b/drivers/net/Config.in
@@ -37,7 +37,6 @@ if [ "$CONFIG_NET_ETHERNET" = "y" ]; then
         bool '    Use AAUI port instead of TP by default' CONFIG_MACE_AAUI_PORT
       fi
       dep_tristate '  BMAC (G3 ethernet) support' CONFIG_BMAC $CONFIG_ALL_PPC
-      dep_tristate '  GMAC (G4/iBook ethernet) support' CONFIG_GMAC $CONFIG_ALL_PPC
       tristate '  National DP83902AV (Oak ethernet) support' CONFIG_OAKNET
    fi
    if [ "$CONFIG_ZORRO" = "y" ]; then
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 0c0f48d75bcb..46fb29b5a0f2 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -57,7 +57,6 @@ obj-$(CONFIG_SUNGEM) += sungem.o
 
 obj-$(CONFIG_MACE) += mace.o
 obj-$(CONFIG_BMAC) += bmac.o
-obj-$(CONFIG_GMAC) += gmac.o
 
 obj-$(CONFIG_OAKNET) += oaknet.o 8390.o
 
diff --git a/drivers/net/bmac.c b/drivers/net/bmac.c
index e94ccb93c341..1392552b73d9 100644
--- a/drivers/net/bmac.c
+++ b/drivers/net/bmac.c
@@ -22,7 +22,8 @@
 #include <asm/io.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
-#include <asm/feature.h>
+#include <asm/machdep.h>
+#include <asm/pmac_feature.h>
 #ifdef CONFIG_PMAC_PBOOK
 #include <linux/adb.h>
 #include <linux/pmu.h>
@@ -155,7 +156,7 @@ static void bmac_reset_and_enable(struct net_device *dev);
 static void bmac_start_chip(struct net_device *dev);
 static void bmac_init_chip(struct net_device *dev);
 static void bmac_init_registers(struct net_device *dev);
-static void bmac_reset_chip(struct net_device *dev);
+static void bmac_enable_and_reset_chip(struct net_device *dev);
 static int bmac_set_address(struct net_device *dev, void *addr);
 static void bmac_misc_intr(int irq, void *dev_id, struct pt_regs *regs);
 static void bmac_txdma_intr(int irq, void *dev_id, struct pt_regs *regs);
@@ -229,21 +230,18 @@ volatile unsigned short bmread(struct net_device *dev, unsigned long reg_offset
 }
 
 static void
-bmac_reset_chip(struct net_device *dev)
+bmac_enable_and_reset_chip(struct net_device *dev)
 {
 	struct bmac_data *bp = (struct bmac_data *) dev->priv;
 	volatile struct dbdma_regs *rd = bp->rx_dma;
 	volatile struct dbdma_regs *td = bp->tx_dma;
 
-	dbdma_reset(rd);
-	dbdma_reset(td);
+	if (rd)
+		dbdma_reset(rd);
+	if (td)
+		dbdma_reset(td);
 
-	feature_set(bp->node, FEATURE_BMac_IO_enable);
-	udelay(10000);
-	feature_set(bp->node, FEATURE_BMac_reset);
-	udelay(10000);
-	feature_clear(bp->node, FEATURE_BMac_reset);
-	udelay(10000);
+	pmac_call_feature(PMAC_FTR_BMAC_ENABLE, bp->node, 0, 1);
 }
 
 #define MIFDELAY	udelay(10)
@@ -522,10 +520,7 @@ bmac_sleep_notify(struct pmu_sleep_notifier *self, int when)
 				}
 			}
 		}
-		feature_set(bp->node, FEATURE_BMac_reset);
-		mdelay(10);
-		feature_clear(bp->node, FEATURE_BMac_IO_enable);
-		mdelay(10);
+		pmac_call_feature(PMAC_FTR_BMAC_ENABLE, bp->node, 0, 0);
 		break;
 	case PBOOK_WAKE:
 		/* see if this is enough */
@@ -1254,7 +1249,7 @@ static void bmac_reset_and_enable(struct net_device *dev)
 	unsigned char *data;
 
 	save_flags(flags); cli();
-	bmac_reset_chip(dev);
+	bmac_enable_and_reset_chip(dev);
 	bmac_init_tx_ring(bp);
 	bmac_init_rx_ring(bp);
 	bmac_init_chip(dev);
@@ -1337,14 +1332,30 @@ static void __init bmac_probe1(struct device_node *bmac, int is_bmac_plus)
 		       bmac->full_name);
 		return;
 	}
+	bp = (struct bmac_data *) dev->priv;
 	SET_MODULE_OWNER(dev);
+	bp->node = bmac;
 
+	if (!request_OF_resource(bmac, 0, " (bmac)")) {
+		printk(KERN_ERR "BMAC: can't request IO resource !\n");
+		goto err_out;
+	}
+	if (!request_OF_resource(bmac, 1, " (bmac tx dma)")) {
+		printk(KERN_ERR "BMAC: can't request TX DMA resource !\n");
+		goto err_out;
+	}
+
+	if (!request_OF_resource(bmac, 2, " (bmac rx dma)")) {
+		printk(KERN_ERR "BMAC: can't request RX DMA resource !\n");
+		goto err_out;
+	}
 	dev->base_addr = (unsigned long)
 		ioremap(bmac->addrs[0].address, bmac->addrs[0].size);
 	if (!dev->base_addr)
 		goto err_out;
 	dev->irq = bmac->intrs[0].line;
 
+	bmac_enable_and_reset_chip(dev);
 	bmwrite(dev, INTDISABLE, DisableAll);
 
 	printk(KERN_INFO "%s: BMAC%s at", dev->name, (is_bmac_plus? "+": ""));
@@ -1356,6 +1367,10 @@ static void __init bmac_probe1(struct device_node *bmac, int is_bmac_plus)
 	XXDEBUG((", base_addr=%#0lx", dev->base_addr));
 	printk("\n");
 
+	/* Enable chip without interrupts for now */
+	bmac_enable_and_reset_chip(dev);
+	bmwrite(dev, INTDISABLE, DisableAll);
+
 	dev->open = bmac_open;
 	dev->stop = bmac_close;
 	dev->hard_start_xmit = bmac_output;
@@ -1367,7 +1382,6 @@ static void __init bmac_probe1(struct device_node *bmac, int is_bmac_plus)
 	if (bmac_verify_checksum(dev) != 0)
 		goto err_out_iounmap;
 
-	bp = (struct bmac_data *) dev->priv;
 	bp->is_bmac_plus = is_bmac_plus;
 	bp->tx_dma = (volatile struct dbdma_regs *)
 		ioremap(bmac->addrs[1].address, bmac->addrs[1].size);
@@ -1386,7 +1400,6 @@ static void __init bmac_probe1(struct device_node *bmac, int is_bmac_plus)
 	bp->queue = (struct sk_buff_head *)(bp->rx_cmds + N_RX_RING + 1);
 	skb_queue_head_init(bp->queue);
 
-	bp->node = bmac;
 	memset((char *) bp->tx_cmds, 0,
 	       (N_TX_RING + N_RX_RING + 2) * sizeof(struct dbdma_cmd));
 	/*     init_timer(&bp->tx_timeout); */
@@ -1408,6 +1421,12 @@ static void __init bmac_probe1(struct device_node *bmac, int is_bmac_plus)
 		goto err_out_irq1;
 	}
 
+	/* Mask chip interrupts and disable chip, will be
+	 * re-enabled on open()
+	 */
+	disable_irq(dev->irq);
+	pmac_call_feature(PMAC_FTR_BMAC_ENABLE, bp->node, 0, 0);
+	
 	bp->next_bmac = bmac_devs;
 	bmac_devs = dev;
 	return;
@@ -1423,6 +1442,12 @@ err_out_iounmap_tx:
 err_out_iounmap:
 	iounmap((void *)dev->base_addr);
 err_out:
+	if (bp->node) {
+		release_OF_resource(bp->node, 0);
+		release_OF_resource(bp->node, 1);
+		release_OF_resource(bp->node, 2);
+		pmac_call_feature(PMAC_FTR_BMAC_ENABLE, bp->node, 0, 0);
+	}
 	unregister_netdev(dev);
 	kfree(dev);
 }
@@ -1434,6 +1459,7 @@ static int bmac_open(struct net_device *dev)
 	/* reset the chip */
 	bp->opened = 1;
 	bmac_reset_and_enable(dev);
+	enable_irq(dev->irq);
 	dev->flags |= IFF_RUNNING;
 	return 0;
 }
@@ -1446,6 +1472,7 @@ static int bmac_close(struct net_device *dev)
 	unsigned short config;
 	int i;
 
+	bp->sleeping = 1;
 	dev->flags &= ~(IFF_UP | IFF_RUNNING);
 
 	/* disable rx and tx */
@@ -1479,6 +1506,8 @@ static int bmac_close(struct net_device *dev)
 	XXDEBUG(("bmac: all bufs freed\n"));
 
 	bp->opened = 0;
+	disable_irq(dev->irq);
+	pmac_call_feature(PMAC_FTR_BMAC_ENABLE, bp->node, 0, 0);
 
 	return 0;
 }
@@ -1548,7 +1577,7 @@ static void bmac_tx_timeout(unsigned long data)
 	bmwrite(dev, TXCFG, (config & ~TxMACEnable));
 	out_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD));
 	printk(KERN_ERR "bmac: transmit timeout - resetting\n");
-	bmac_reset_chip(dev);
+	bmac_enable_and_reset_chip(dev);
 
 	/* restart rx dma */
 	cp = bus_to_virt(ld_le32(&rd->cmdptr));
@@ -1670,11 +1699,15 @@ static void __exit bmac_cleanup (void)
 		bp = (struct bmac_data *) dev->priv;
 		bmac_devs = bp->next_bmac;
 
+		unregister_netdev(dev);
+
+		release_OF_resource(bp->node, 0);
+		release_OF_resource(bp->node, 1);
+		release_OF_resource(bp->node, 2);
 		free_irq(dev->irq, dev);
 		free_irq(bp->tx_dma_intr, dev);
 		free_irq(bp->rx_dma_intr, dev);
 
-		unregister_netdev(dev);
 		kfree(dev);
 	} while (bmac_devs != NULL);
 }
diff --git a/drivers/net/gmac.c b/drivers/net/gmac.c
deleted file mode 100644
index 1406a5edb968..000000000000
--- a/drivers/net/gmac.c
+++ /dev/null
@@ -1,1699 +0,0 @@
-/*
- * Network device driver for the GMAC ethernet controller on
- * Apple G4 Powermacs.
- *
- * Copyright (C) 2000 Paul Mackerras & Ben. Herrenschmidt
- * 
- * portions based on sunhme.c by David S. Miller
- *
- * Changes:
- * Arnaldo Carvalho de Melo <acme@conectiva.com.br> - 08/06/2000
- * - check init_etherdev return in gmac_probe1
- * BenH <benh@kernel.crashing.org> - 03/09/2000
- * - Add support for new PHYs
- * - Add some PowerBook sleep code
- * BenH <benh@kernel.crashing.org> - ??/??/????
- *  - PHY updates
- * BenH <benh@kernel.crashing.org> - 08/08/2001
- * - Add more PHYs, fixes to sleep code
- * Matt Domsch <Matt_Domsch@dell.com> - 11/12/2001
- * - use library crc32 functions
- */
-
-#include <linux/module.h>
-
-#include <linux/config.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/types.h>
-#include <linux/fcntl.h>
-#include <linux/interrupt.h>
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/delay.h>
-#include <linux/string.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/crc32.h>
-#include <asm/prom.h>
-#include <asm/io.h>
-#include <asm/pgtable.h>
-#include <asm/feature.h>
-#include <asm/keylargo.h>
-#include <asm/pci-bridge.h>
-#ifdef CONFIG_PMAC_PBOOK
-#include <linux/adb.h>
-#include <linux/pmu.h>
-#include <asm/irq.h>
-#endif
-
-#include "gmac.h"
-
-#define DEBUG_PHY
-
-/* Driver version 1.5, kernel 2.4.x */
-#define GMAC_VERSION	"v1.5k4"
-
-#define DUMMY_BUF_LEN	RX_BUF_ALLOC_SIZE + RX_OFFSET + GMAC_BUFFER_ALIGN
-static unsigned char *dummy_buf;
-static struct net_device *gmacs;
-
-/* Prototypes */
-static int mii_read(struct gmac *gm, int phy, int r);
-static int mii_write(struct gmac *gm, int phy, int r, int v);
-static void mii_poll_start(struct gmac *gm);
-static void mii_poll_stop(struct gmac *gm);
-static void mii_interrupt(struct gmac *gm);
-static int mii_lookup_and_reset(struct gmac *gm);
-static void mii_setup_phy(struct gmac *gm);
-static int mii_do_reset_phy(struct gmac *gm, int phy_addr);
-static void mii_init_BCM5400(struct gmac *gm);
-static void mii_init_BCM5401(struct gmac *gm);
-
-static void gmac_set_power(struct gmac *gm, int power_up);
-static int gmac_powerup_and_reset(struct net_device *dev);
-static void gmac_set_gigabit_mode(struct gmac *gm, int gigabit);
-static void gmac_set_duplex_mode(struct gmac *gm, int full_duplex);
-static void gmac_mac_init(struct gmac *gm, unsigned char *mac_addr);
-static void gmac_init_rings(struct gmac *gm, int from_irq);
-static void gmac_start_dma(struct gmac *gm);
-static void gmac_stop_dma(struct gmac *gm);
-static void gmac_set_multicast(struct net_device *dev);
-static int gmac_open(struct net_device *dev);
-static int gmac_close(struct net_device *dev);
-static void gmac_tx_timeout(struct net_device *dev);
-static int gmac_xmit_start(struct sk_buff *skb, struct net_device *dev);
-static void gmac_tx_cleanup(struct net_device *dev, int force_cleanup);
-static void gmac_receive(struct net_device *dev);
-static void gmac_interrupt(int irq, void *dev_id, struct pt_regs *regs);
-static struct net_device_stats *gmac_stats(struct net_device *dev);
-static int gmac_probe(void);
-static void gmac_probe1(struct device_node *gmac);
-
-#ifdef CONFIG_PMAC_PBOOK
-int gmac_sleep_notify(struct pmu_sleep_notifier *self, int when);
-static struct pmu_sleep_notifier gmac_sleep_notifier = {
-	gmac_sleep_notify, SLEEP_LEVEL_NET,
-};
-#endif
-
-/*
- * Read via the mii interface from a PHY register
- */
-static int
-mii_read(struct gmac *gm, int phy, int r)
-{
-	int timeout;
-
-	GM_OUT(GM_MIF_FRAME_CTL_DATA,
-		(0x01 << GM_MIF_FRAME_START_SHIFT) |
-		(0x02 << GM_MIF_FRAME_OPCODE_SHIFT) |
-		GM_MIF_FRAME_TURNAROUND_HI |
-		(phy << GM_MIF_FRAME_PHY_ADDR_SHIFT) |
-		(r << GM_MIF_FRAME_REG_ADDR_SHIFT));
-		
-	for (timeout = 1000; timeout > 0; --timeout) {
-		udelay(20);
-		if (GM_IN(GM_MIF_FRAME_CTL_DATA) & GM_MIF_FRAME_TURNAROUND_LO)
-			return GM_IN(GM_MIF_FRAME_CTL_DATA) & GM_MIF_FRAME_DATA_MASK;
-	}
-	return -1;
-}
-
-/*
- * Write on the mii interface to a PHY register
- */
-static int
-mii_write(struct gmac *gm, int phy, int r, int v)
-{
-	int timeout;
-
-	GM_OUT(GM_MIF_FRAME_CTL_DATA,
-		(0x01 << GM_MIF_FRAME_START_SHIFT) |
-		(0x01 << GM_MIF_FRAME_OPCODE_SHIFT) |
-		GM_MIF_FRAME_TURNAROUND_HI |
-		(phy << GM_MIF_FRAME_PHY_ADDR_SHIFT) |
-		(r << GM_MIF_FRAME_REG_ADDR_SHIFT) |
-		(v & GM_MIF_FRAME_DATA_MASK));
-
-	for (timeout = 1000; timeout > 0; --timeout) {
-		udelay(20);
-		if (GM_IN(GM_MIF_FRAME_CTL_DATA) & GM_MIF_FRAME_TURNAROUND_LO)
-			return 0;
-	}
-	return -1;
-}
-
-/*
- * Start MIF autopolling of the PHY status register
- */
-static void 
-mii_poll_start(struct gmac *gm)
-{
-	unsigned int tmp;
-	
-	/* Start the MIF polling on the external transceiver. */
-	tmp = GM_IN(GM_MIF_CFG);
-	tmp &= ~(GM_MIF_CFGPR_MASK | GM_MIF_CFGPD_MASK);
-	tmp |= ((gm->phy_addr & 0x1f) << GM_MIF_CFGPD_SHIFT);
-	tmp |= (MII_SR << GM_MIF_CFGPR_SHIFT);
-	tmp |= GM_MIF_CFGPE;
-	GM_OUT(GM_MIF_CFG, tmp);
-
-	/* Let the bits set. */
-	udelay(GM_MIF_POLL_DELAY);
-
-	GM_OUT(GM_MIF_IRQ_MASK, 0xffc0);
-}
-
-/*
- * Stop MIF autopolling of the PHY status register
- */
-static void 
-mii_poll_stop(struct gmac *gm)
-{
-	GM_OUT(GM_MIF_IRQ_MASK, 0xffff);
-	GM_BIC(GM_MIF_CFG, GM_MIF_CFGPE);
-	udelay(GM_MIF_POLL_DELAY);
-}
-
-/*
- * Called when the MIF detect a change of the PHY status
- * 
- * handles monitoring the link and updating GMAC with the correct
- * duplex mode.
- * 
- * Note: Are we missing status changes ? In this case, we'll have to
- * a timer and control the autoneg. process more closely. Also, we may
- * want to stop rx and tx side when the link is down.
- */
-
-/* Link modes of the BCM5400 PHY */
-static int phy_BCM5400_link_table[8][3] = {
-	{ 0, 0, 0 },	/* No link */
-	{ 0, 0, 0 },	/* 10BT Half Duplex */
-	{ 1, 0, 0 },	/* 10BT Full Duplex */
-	{ 0, 1, 0 },	/* 100BT Half Duplex */
-	{ 0, 1, 0 },	/* 100BT Half Duplex */
-	{ 1, 1, 0 },	/* 100BT Full Duplex*/
-	{ 1, 0, 1 },	/* 1000BT */
-	{ 1, 0, 1 },	/* 1000BT */
-};
-
-static void
-mii_interrupt(struct gmac *gm)
-{
-	int		phy_status;
-	int		lpar_ability;
-	
-	mii_poll_stop(gm);
-
-	/* May the status change before polling is re-enabled ? */
-	mii_poll_start(gm);
-	
-	/* We read the Auxilliary Status Summary register */
-	phy_status = mii_read(gm, gm->phy_addr, MII_SR);
-	if ((phy_status ^ gm->phy_status) & (MII_SR_ASSC | MII_SR_LKS)) {
-		int		full_duplex = 0;
-		int		link_100 = 0;
-		int		gigabit = 0;
-#ifdef DEBUG_PHY
-		printk(KERN_INFO "%s: Link state change, phy_status: 0x%04x\n",
-			gm->dev->name, phy_status);
-#endif
-		gm->phy_status = phy_status;
-
-		/* Should we enable that in generic mode ? */
-		lpar_ability = mii_read(gm, gm->phy_addr, MII_ANLPA);
-		if (lpar_ability & MII_ANLPA_PAUS)
-			GM_BIS(GM_MAC_CTRL_CONFIG, GM_MAC_CTRL_CONF_SND_PAUSE_EN);
-		else
-			GM_BIC(GM_MAC_CTRL_CONFIG, GM_MAC_CTRL_CONF_SND_PAUSE_EN);
-
-		/* Link ? Check for speed and duplex */
-		if ((phy_status & MII_SR_LKS) && (phy_status & MII_SR_ASSC)) {
-		    int restart = 0;
-		    int aux_stat, link;
-		    switch (gm->phy_type) {
-		      case PHY_B5201:
-		      case PHY_B5221:
-		    	aux_stat = mii_read(gm, gm->phy_addr, MII_BCM5201_AUXCTLSTATUS);
-#ifdef DEBUG_PHY
-			printk(KERN_INFO "%s:    Link up ! BCM5201/5221 aux_stat: 0x%04x\n",
-				gm->dev->name, aux_stat);
-#endif
-		    	full_duplex = ((aux_stat & MII_BCM5201_AUXCTLSTATUS_DUPLEX) != 0);
-		    	link_100 = ((aux_stat & MII_BCM5201_AUXCTLSTATUS_SPEED) != 0);
-		        break;
-		      case PHY_B5400:
-		      case PHY_B5401:
-		      case PHY_B5411:
-		    	aux_stat = mii_read(gm, gm->phy_addr, MII_BCM5400_AUXSTATUS);
-		    	link = (aux_stat & MII_BCM5400_AUXSTATUS_LINKMODE_MASK) >>
-		    			MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT;
-#ifdef DEBUG_PHY
-			printk(KERN_INFO "%s:    Link up ! BCM54xx aux_stat: 0x%04x (link mode: %d)\n",
-				gm->dev->name, aux_stat, link);
-#endif
-		    	full_duplex = phy_BCM5400_link_table[link][0];
-		    	link_100 = phy_BCM5400_link_table[link][1];
-		    	gigabit = phy_BCM5400_link_table[link][2];
-		    	break;
-		      case PHY_LXT971:
-		    	aux_stat = mii_read(gm, gm->phy_addr, MII_LXT971_STATUS2);
-#ifdef DEBUG_PHY
-			printk(KERN_INFO "%s:    Link up ! LXT971 stat2: 0x%04x\n",
-				gm->dev->name, aux_stat);
-#endif
-		    	full_duplex = ((aux_stat & MII_LXT971_STATUS2_FULLDUPLEX) != 0);
-		    	link_100 = ((aux_stat & MII_LXT971_STATUS2_SPEED) != 0);
-		    	break;
-		      default:
-		    	full_duplex = (lpar_ability & MII_ANLPA_FDAM) != 0;
-		    	link_100 = (lpar_ability & MII_ANLPA_100M) != 0;
-		    	break;
-		    }
-#ifdef DEBUG_PHY
-		    printk(KERN_INFO "%s:    Full Duplex: %d, Speed: %s\n",
-		    	gm->dev->name, full_duplex,
-		    	gigabit ? "1000" : (link_100 ? "100" : "10"));
-#endif
-                    if (gigabit != gm->gigabit) {
-                    	gm->gigabit = gigabit;
-                    	gmac_set_gigabit_mode(gm, gm->gigabit);
-                    	restart = 1;
-                    }
-		    if (full_duplex != gm->full_duplex) {
-			gm->full_duplex = full_duplex;
-			gmac_set_duplex_mode(gm, gm->full_duplex);
-			restart = 1;
-		    }
-		    if (restart)
-			gmac_start_dma(gm);
-		} else if (!(phy_status & MII_SR_LKS)) {
-#ifdef DEBUG_PHY
-		    printk(KERN_INFO "%s:    Link down !\n", gm->dev->name);
-#endif
-		}
-	}
-}
-
-/* Power management: stop PHY chip for suspend mode
- * 
- * TODO: This will have to be modified is WOL is to be supported.
- */
-static void
-gmac_suspend(struct gmac* gm)
-{
-	int data, timeout;
-	unsigned long flags;
-	
-	gm->sleeping = 1;
-	netif_device_detach(gm->dev);
-
-
-	spin_lock_irqsave(&gm->lock, flags);
-	if (gm->opened) {
-		disable_irq(gm->dev->irq);
-		/* Stop polling PHY */
-		mii_poll_stop(gm);
-	}
-	/* Mask out all chips interrupts */
-	GM_OUT(GM_IRQ_MASK, 0xffffffff);
-	spin_unlock_irqrestore(&gm->lock, flags);
-	
-	if (gm->opened) {
-		int i;
-		/* Empty Tx ring of any remaining gremlins */
-		gmac_tx_cleanup(gm->dev, 1);
-	
-		/* Empty Rx ring of any remaining gremlins */
-		for (i = 0; i < NRX; ++i) {
-			if (gm->rx_buff[i] != 0) {
-				dev_kfree_skb_irq(gm->rx_buff[i]);
-				gm->rx_buff[i] = 0;
-			}
-		}
-	}
-
-	/* Clear interrupts on 5201 */
-	if (gm->phy_type == PHY_B5201 || gm->phy_type == PHY_B5221)
-		mii_write(gm, gm->phy_addr, MII_BCM5201_INTERRUPT, 0);
-		
-	/* Drive MDIO high */
-	GM_OUT(GM_MIF_CFG, 0);
-	
-	/* Unchanged, don't ask me why */
-	data = mii_read(gm, gm->phy_addr, MII_ANLPA);
-	mii_write(gm, gm->phy_addr, MII_ANLPA, data);
-	
-	/* Stop everything */
-	GM_OUT(GM_MAC_RX_CONFIG, 0);
-	GM_OUT(GM_MAC_TX_CONFIG, 0);
-	GM_OUT(GM_MAC_XIF_CONFIG, 0);
-	GM_OUT(GM_TX_CONF, 0);
-	GM_OUT(GM_RX_CONF, 0);
-	
-	/* Set MAC in reset state */
-	GM_OUT(GM_RESET, GM_RESET_TX | GM_RESET_RX);
-	for (timeout = 100; timeout > 0; --timeout) {
-		mdelay(10);
-		if ((GM_IN(GM_RESET) & (GM_RESET_TX | GM_RESET_RX)) == 0)
-			break;
-	}
-	GM_OUT(GM_MAC_TX_RESET, GM_MAC_TX_RESET_NOW);
-	GM_OUT(GM_MAC_RX_RESET, GM_MAC_RX_RESET_NOW);
-
-	/* Superisolate PHY */
-	if (gm->phy_type == PHY_B5201 || gm->phy_type == PHY_B5221)
-		mii_write(gm, gm->phy_addr, MII_BCM5201_MULTIPHY,
-			MII_BCM5201_MULTIPHY_SUPERISOLATE);
-
-	/* Put MDIO in sane electric state. According to an obscure
-	 * Apple comment, not doing so may let them drive some current
-	 * during sleep and possibly damage BCM PHYs.
-	 */
-	GM_OUT(GM_MIF_CFG, GM_MIF_CFGBB);
-	GM_OUT(GM_MIF_BB_CLOCK, 0);
-	GM_OUT(GM_MIF_BB_DATA, 0);
-	GM_OUT(GM_MIF_BB_OUT_ENABLE, 0);
-	GM_OUT(GM_MAC_XIF_CONFIG,
-		GM_MAC_XIF_CONF_GMII_MODE|GM_MAC_XIF_CONF_MII_INT_LOOP);
-	(void)GM_IN(GM_MAC_XIF_CONFIG);
-	
-	/* Unclock the GMAC chip */
-	gmac_set_power(gm, 0);
-}
-
-static void
-gmac_resume(struct gmac *gm)
-{
-	int data;
-
-	if (gmac_powerup_and_reset(gm->dev)) {
-		printk(KERN_ERR "%s: Couldn't revive gmac ethernet !\n", gm->dev->name);
-		return;
-	}
-
-	gm->sleeping = 0;
-	
-	if (gm->opened) {
-		/* Create fresh rings */
-		gmac_init_rings(gm, 1);
-		/* re-initialize the MAC */
-		gmac_mac_init(gm, gm->dev->dev_addr);	
-		/* re-initialize the multicast tables & promisc mode if any */
-		gmac_set_multicast(gm->dev);
-	}
-
-	/* Early enable Tx and Rx so that we are clocked */
-	GM_BIS(GM_TX_CONF, GM_TX_CONF_DMA_EN);
-	mdelay(20);
-	GM_BIS(GM_RX_CONF, GM_RX_CONF_DMA_EN);
-	mdelay(20);
-	GM_BIS(GM_MAC_TX_CONFIG, GM_MAC_TX_CONF_ENABLE);
-	mdelay(20);
-	GM_BIS(GM_MAC_RX_CONFIG, GM_MAC_RX_CONF_ENABLE);
-	mdelay(20);
-	if (gm->phy_type == PHY_B5201 || gm->phy_type == PHY_B5221) {
-		data = mii_read(gm, gm->phy_addr, MII_BCM5201_MULTIPHY);
-		mii_write(gm, gm->phy_addr, MII_BCM5201_MULTIPHY,
-			data & ~MII_BCM5201_MULTIPHY_SUPERISOLATE);
-	}
-	mdelay(1);
-
-	if (gm->opened) {
-		/* restart polling PHY */
-		mii_interrupt(gm);
-		/* restart DMA operations */
-		gmac_start_dma(gm);
-		netif_device_attach(gm->dev);
-		enable_irq(gm->dev->irq);
-	} else {
-		/* Driver not opened, just leave things off. Note that
-		 * we could be smart and superisolate the PHY when the
-		 * driver is closed, but I won't do that unless I have
-		 * a better understanding of some electrical issues with
-		 * this PHY chip --BenH
-		 */
-		GM_OUT(GM_MAC_RX_CONFIG, 0);
-		GM_OUT(GM_MAC_TX_CONFIG, 0);
-		GM_OUT(GM_MAC_XIF_CONFIG, 0);
-		GM_OUT(GM_TX_CONF, 0);
-		GM_OUT(GM_RX_CONF, 0);
-	}
-}
-
-static int
-mii_do_reset_phy(struct gmac *gm, int phy_addr)
-{
-	int mii_control, timeout;
-	
-	mii_control = mii_read(gm, phy_addr, MII_CR);
-	mii_write(gm, phy_addr, MII_CR, mii_control | MII_CR_RST);
-	mdelay(10);
-	for (timeout = 100; timeout > 0; --timeout) {
-		mii_control = mii_read(gm, phy_addr, MII_CR);
-		if (mii_control == -1) {
-			printk(KERN_ERR "%s PHY died after reset !\n",
-				gm->dev->name);
-			return 1;
-		}
-		if ((mii_control & MII_CR_RST) == 0)
-			break;
-		mdelay(10);
-	}
-	if (mii_control & MII_CR_RST) {
-		printk(KERN_ERR "%s PHY reset timeout !\n", gm->dev->name);
-		return 1;
-	}
-	mii_write(gm, phy_addr, MII_CR, mii_control & ~MII_CR_ISOL);
-	return 0;
-}
-
-/* Here's a bunch of configuration routines for
- * Broadcom PHYs used on various Mac models. Unfortunately,
- * except for the 5201, Broadcom never sent me any documentation,
- * so this is from my understanding of Apple's Open Firmware
- * drivers and Darwin's implementation
- */
- 
-static void
-mii_init_BCM5400(struct gmac *gm)
-{
-	int data;
-
-	/* Configure for gigabit full duplex */
-	data = mii_read(gm, gm->phy_addr, MII_BCM5400_AUXCONTROL);
-	data |= MII_BCM5400_AUXCONTROL_PWR10BASET;
-	mii_write(gm, gm->phy_addr, MII_BCM5400_AUXCONTROL, data);
-	
-	data = mii_read(gm, gm->phy_addr, MII_BCM5400_GB_CONTROL);
-	data |= MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP;
-	mii_write(gm, gm->phy_addr, MII_BCM5400_GB_CONTROL, data);
-	
-	mdelay(10);
-
-	/* Reset and configure cascaded 10/100 PHY */
-	mii_do_reset_phy(gm, 0x1f);
-	
-	data = mii_read(gm, 0x1f, MII_BCM5201_MULTIPHY);
-	data |= MII_BCM5201_MULTIPHY_SERIALMODE;
-	mii_write(gm, 0x1f, MII_BCM5201_MULTIPHY, data);
-
-	data = mii_read(gm, gm->phy_addr, MII_BCM5400_AUXCONTROL);
-	data &= ~MII_BCM5400_AUXCONTROL_PWR10BASET;
-	mii_write(gm, gm->phy_addr, MII_BCM5400_AUXCONTROL, data);
-}
-
-static void
-mii_init_BCM5401(struct gmac *gm)
-{
-	int data;
-	int rev;
-
-	rev = mii_read(gm, gm->phy_addr, MII_ID1) & 0x000f;
-	if (rev == 0 || rev == 3) {
-		/* Some revisions of 5401 appear to need this
-		 * initialisation sequence to disable, according
-		 * to OF, "tap power management"
-		 * 
-		 * WARNING ! OF and Darwin don't agree on the
-		 * register addresses. OF seem to interpret the
-		 * register numbers below as decimal
-		 */
-		mii_write(gm, gm->phy_addr, 0x18, 0x0c20);
-		mii_write(gm, gm->phy_addr, 0x17, 0x0012);
-		mii_write(gm, gm->phy_addr, 0x15, 0x1804);
-		mii_write(gm, gm->phy_addr, 0x17, 0x0013);
-		mii_write(gm, gm->phy_addr, 0x15, 0x1204);
-		mii_write(gm, gm->phy_addr, 0x17, 0x8006);
-		mii_write(gm, gm->phy_addr, 0x15, 0x0132);
-		mii_write(gm, gm->phy_addr, 0x17, 0x8006);
-		mii_write(gm, gm->phy_addr, 0x15, 0x0232);
-		mii_write(gm, gm->phy_addr, 0x17, 0x201f);
-		mii_write(gm, gm->phy_addr, 0x15, 0x0a20);
-	}
-	
-	/* Configure for gigabit full duplex */
-	data = mii_read(gm, gm->phy_addr, MII_BCM5400_GB_CONTROL);
-	data |= MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP;
-	mii_write(gm, gm->phy_addr, MII_BCM5400_GB_CONTROL, data);
-
-	mdelay(10);
-
-	/* Reset and configure cascaded 10/100 PHY */
-	mii_do_reset_phy(gm, 0x1f);
-	
-	data = mii_read(gm, 0x1f, MII_BCM5201_MULTIPHY);
-	data |= MII_BCM5201_MULTIPHY_SERIALMODE;
-	mii_write(gm, 0x1f, MII_BCM5201_MULTIPHY, data);
-}
-
-static void
-mii_init_BCM5411(struct gmac *gm)
-{
-	int data;
-
-	/* Here's some more Apple black magic to setup
-	 * some voltage stuffs.
-	 */
-	mii_write(gm, gm->phy_addr, 0x1c, 0x8c23);
-	mii_write(gm, gm->phy_addr, 0x1c, 0x8ca3);
-	mii_write(gm, gm->phy_addr, 0x1c, 0x8c23);
-
-	/* Here, Apple seems to want to reset it, do
-	 * it as well
-	 */
-	mii_write(gm, gm->phy_addr, MII_CR, MII_CR_RST);
-
-	/* Start autoneg */
-	mii_write(gm, gm->phy_addr, MII_CR,
-			MII_CR_ASSE|MII_CR_FDM|	/* Autospeed, full duplex */
-			MII_CR_RAN|
-			MII_CR_SPEEDSEL2 /* chip specific, gigabit enable ? */);
-
-	data = mii_read(gm, gm->phy_addr, MII_BCM5400_GB_CONTROL);
-	data |= MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP;
-	mii_write(gm, gm->phy_addr, MII_BCM5400_GB_CONTROL, data);
-}
-
-static int
-mii_lookup_and_reset(struct gmac *gm)
-{
-	int	i, mii_status, mii_control;
-
-	gm->phy_addr = -1;
-	gm->phy_type = PHY_UNKNOWN;
-
-	/* Hard reset the PHY */
-	feature_gmac_phy_reset(gm->of_node);
-	
-	/* Find the PHY */
-	for(i=0; i<=31; i++) {
-		mii_control = mii_read(gm, i, MII_CR);
-		mii_status = mii_read(gm, i, MII_SR);
-		if (mii_control != -1  && mii_status != -1 &&
-			(mii_control != 0xffff || mii_status != 0xffff))
-			break;
-	}
-	gm->phy_addr = i;
-	if (gm->phy_addr > 31)
-		return 0;
-
-	/* Reset it */
-	if (mii_do_reset_phy(gm, gm->phy_addr))
-		goto fail;
-	
-	/* Read the PHY ID */
-	gm->phy_id = (mii_read(gm, gm->phy_addr, MII_ID0) << 16) |
-		mii_read(gm, gm->phy_addr, MII_ID1);
-#ifdef DEBUG_PHY
-	printk(KERN_INFO "%s: PHY ID: 0x%08x\n", gm->dev->name, gm->phy_id);
-#endif
-	if ((gm->phy_id & MII_BCM5400_MASK) == MII_BCM5400_ID) {
-		gm->phy_type = PHY_B5400;
-		printk(KERN_INFO  "%s: Found Broadcom BCM5400 PHY (Gigabit)\n",
-			gm->dev->name);
-		mii_init_BCM5400(gm);		
-	} else if ((gm->phy_id & MII_BCM5401_MASK) == MII_BCM5401_ID) {
-		gm->phy_type = PHY_B5401;
-		printk(KERN_INFO  "%s: Found Broadcom BCM5401 PHY (Gigabit)\n",
-			gm->dev->name);
-		mii_init_BCM5401(gm);		
-	} else if ((gm->phy_id & MII_BCM5411_MASK) == MII_BCM5411_ID) {
-		gm->phy_type = PHY_B5411;
-		printk(KERN_INFO  "%s: Found Broadcom BCM5411 PHY (Gigabit)\n",
-			gm->dev->name);
-		mii_init_BCM5411(gm);		
-	} else if ((gm->phy_id & MII_BCM5201_MASK) == MII_BCM5201_ID) {
-		gm->phy_type = PHY_B5201;
-		printk(KERN_INFO "%s: Found Broadcom BCM5201 PHY\n", gm->dev->name);
-	} else if ((gm->phy_id & MII_BCM5221_MASK) == MII_BCM5221_ID) {
-		gm->phy_type = PHY_B5221;
-		printk(KERN_INFO "%s: Found Broadcom BCM5221 PHY\n", gm->dev->name);
-	} else if ((gm->phy_id & MII_LXT971_MASK) == MII_LXT971_ID) {
-		gm->phy_type = PHY_LXT971;
-		printk(KERN_INFO "%s: Found LevelOne LX971 PHY\n", gm->dev->name);
-	} else {
-		printk(KERN_WARNING "%s: Warning ! Unknown PHY ID 0x%08x, using generic mode...\n",
-			gm->dev->name, gm->phy_id);
-	}
-
-	return 1;
-	
-fail:
-	gm->phy_addr = -1;
-	return 0;
-}
-
-/* 
- * Setup the PHY autonegociation parameters
- * 
- * Code to force the PHY duplex mode and speed should be
- * added here
- */
-static void
-mii_setup_phy(struct gmac *gm)
-{
-	int data;
-	
-	/* Stop auto-negociation */
-	data = mii_read(gm, gm->phy_addr, MII_CR);
-	mii_write(gm, gm->phy_addr, MII_CR, data & ~MII_CR_ASSE);
-
-	/* Set advertisement to 10/100 and Half/Full duplex
-	 * (full capabilities) */
-	data = mii_read(gm, gm->phy_addr, MII_ANA);
-	data |= MII_ANA_TXAM | MII_ANA_FDAM | MII_ANA_10M;
-	mii_write(gm, gm->phy_addr, MII_ANA, data);
-	
-	/* Restart auto-negociation */
-	data = mii_read(gm, gm->phy_addr, MII_CR);
-	data |= MII_CR_ASSE;
-	mii_write(gm, gm->phy_addr, MII_CR, data);
-	data |= MII_CR_RAN;
-	mii_write(gm, gm->phy_addr, MII_CR, data);
-}
-
-/* 
- * Turn On/Off the gmac cell inside Uni-N
- * 
- * ToDo: Add code to support powering down of the PHY.
- */
-static void
-gmac_set_power(struct gmac *gm, int power_up)
-{
-	if (power_up) {
-		feature_set_gmac_power(gm->of_node, 1);
-		if (gm->pci_devfn != 0xff) {
-			u16 cmd;
-			
-			/*
-			 * Make sure PCI is correctly configured
-			 *
-			 * We use old pci_bios versions of the function since, by
-			 * default, gmac is not powered up, and so will be absent
-			 * from the kernel initial PCI lookup. 
-			 * 
-			 * Should be replaced by 2.4 new PCI mecanisms and really
-			 * regiser the device.
-			 */
-			pcibios_read_config_word(gm->pci_bus, gm->pci_devfn,
-				PCI_COMMAND, &cmd);
-			cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
-	    		pcibios_write_config_word(gm->pci_bus, gm->pci_devfn,
-	    			PCI_COMMAND, cmd);
-	    		pcibios_write_config_byte(gm->pci_bus, gm->pci_devfn,
-	    			PCI_LATENCY_TIMER, 16);
-	    		pcibios_write_config_byte(gm->pci_bus, gm->pci_devfn,
-	    			PCI_CACHE_LINE_SIZE, 8);
-		}
-	} else {
-		feature_set_gmac_power(gm->of_node, 0);
-	}
-}
-
-/*
- * Makes sure the GMAC cell is powered up, and reset it
- */
-static int
-gmac_powerup_and_reset(struct net_device *dev)
-{
-	struct gmac *gm = (struct gmac *) dev->priv;
-	int timeout;
-	
-	/* turn on GB clock */
-	gmac_set_power(gm, 1);
-	/* Perform a software reset */
-	GM_OUT(GM_RESET, GM_RESET_TX | GM_RESET_RX);
-	for (timeout = 100; timeout > 0; --timeout) {
-		mdelay(10);
-		if ((GM_IN(GM_RESET) & (GM_RESET_TX | GM_RESET_RX)) == 0) {
-			/* Mask out all chips interrupts */
-			GM_OUT(GM_IRQ_MASK, 0xffffffff);
-			GM_OUT(GM_MAC_TX_RESET, GM_MAC_TX_RESET_NOW);
-			GM_OUT(GM_MAC_RX_RESET, GM_MAC_RX_RESET_NOW);
-			return 0;
-		}
-	}
-	printk(KERN_ERR "%s reset failed!\n", dev->name);
-	gmac_set_power(gm, 0);
-	gm->phy_type = 0;
-	return -1;
-}
-
-/*
- * Set the MAC duplex mode.
- * 
- * Side effect: stops Tx MAC
- */
-static void
-gmac_set_duplex_mode(struct gmac *gm, int full_duplex)
-{
-	/* Stop Tx MAC */
-	GM_BIC(GM_MAC_TX_CONFIG, GM_MAC_TX_CONF_ENABLE);
-	while(GM_IN(GM_MAC_TX_CONFIG) & GM_MAC_TX_CONF_ENABLE)
-		;
-	
-	if (full_duplex) {
-		GM_BIS(GM_MAC_TX_CONFIG, GM_MAC_TX_CONF_IGNORE_CARRIER
-			| GM_MAC_TX_CONF_IGNORE_COLL);
-		GM_BIC(GM_MAC_XIF_CONFIG, GM_MAC_XIF_CONF_DISABLE_ECHO);
-	} else {
-		GM_BIC(GM_MAC_TX_CONFIG, GM_MAC_TX_CONF_IGNORE_CARRIER
-			| GM_MAC_TX_CONF_IGNORE_COLL);
-		GM_BIS(GM_MAC_XIF_CONFIG, GM_MAC_XIF_CONF_DISABLE_ECHO);
-	}
-}
-
-/* Set the MAC gigabit mode. Side effect: stops Tx MAC */
-static void
-gmac_set_gigabit_mode(struct gmac *gm, int gigabit)
-{
-	/* Stop Tx MAC */
-	GM_BIC(GM_MAC_TX_CONFIG, GM_MAC_TX_CONF_ENABLE);
-	while(GM_IN(GM_MAC_TX_CONFIG) & GM_MAC_TX_CONF_ENABLE)
-		;
-	
-	if (gigabit) {
-		GM_BIS(GM_MAC_XIF_CONFIG, GM_MAC_XIF_CONF_GMII_MODE);
-	} else {
-		GM_BIC(GM_MAC_XIF_CONFIG, GM_MAC_XIF_CONF_GMII_MODE);
-	}
-}
-
-/*
- * Initialize a bunch of registers to put the chip into a known
- * and hopefully happy state
- */
-static void
-gmac_mac_init(struct gmac *gm, unsigned char *mac_addr)
-{
-	int i, fifo_size;
-
-	/* Set random seed to low bits of MAC address */
-	GM_OUT(GM_MAC_RANDOM_SEED, mac_addr[5] | (mac_addr[4] << 8));
-	
-	/* Configure the data path mode to MII/GII */
-	GM_OUT(GM_PCS_DATAPATH_MODE, GM_PCS_DATAPATH_MII);
-	
-	/* Configure XIF to MII mode. Full duplex led is set
-	 * by Apple, so...
-	 */
-	GM_OUT(GM_MAC_XIF_CONFIG, GM_MAC_XIF_CONF_TX_MII_OUT_EN
-		| GM_MAC_XIF_CONF_FULL_DPLX_LED);
-
-	/* Mask out all MAC interrupts */
-	GM_OUT(GM_MAC_TX_MASK, 0xffff);
-	GM_OUT(GM_MAC_RX_MASK, 0xffff);
-	GM_OUT(GM_MAC_CTRLSTAT_MASK, 0xff);
-	
-	/* Setup bits of MAC */
-	GM_OUT(GM_MAC_SND_PAUSE, GM_MAC_SND_PAUSE_DEFAULT);
-	GM_OUT(GM_MAC_CTRL_CONFIG, GM_MAC_CTRL_CONF_RCV_PAUSE_EN);
-	
-	/* Configure GEM DMA */
-	GM_OUT(GM_GCONF, GM_GCONF_BURST_SZ |
-		(31 << GM_GCONF_TXDMA_LIMIT_SHIFT) |
-		(31 << GM_GCONF_RXDMA_LIMIT_SHIFT));
-	GM_OUT(GM_TX_CONF,
-		(GM_TX_CONF_FIFO_THR_DEFAULT << GM_TX_CONF_FIFO_THR_SHIFT) |
-		NTX_CONF);
-
-	/* 34 byte offset for checksum computation.  This works because ip_input() will clear out
-	 * the skb->csum and skb->ip_summed fields and recompute the csum if IP options are
-	 * present in the header.  34 == (ethernet header len) + sizeof(struct iphdr)
- 	*/
-	GM_OUT(GM_RX_CONF,
-		(RX_OFFSET << GM_RX_CONF_FBYTE_OFF_SHIFT) |
-		(0x22 << GM_RX_CONF_CHK_START_SHIFT) |
-		(GM_RX_CONF_DMA_THR_DEFAULT << GM_RX_CONF_DMA_THR_SHIFT) |
-		NRX_CONF);
-
-	/* Configure other bits of MAC */
-	GM_OUT(GM_MAC_INTR_PKT_GAP0, GM_MAC_INTR_PKT_GAP0_DEFAULT);
-	GM_OUT(GM_MAC_INTR_PKT_GAP1, GM_MAC_INTR_PKT_GAP1_DEFAULT);
-	GM_OUT(GM_MAC_INTR_PKT_GAP2, GM_MAC_INTR_PKT_GAP2_DEFAULT);
-	GM_OUT(GM_MAC_MIN_FRAME_SIZE, GM_MAC_MIN_FRAME_SIZE_DEFAULT);
-	GM_OUT(GM_MAC_MAX_FRAME_SIZE, GM_MAC_MAX_FRAME_SIZE_DEFAULT);
-	GM_OUT(GM_MAC_PREAMBLE_LEN, GM_MAC_PREAMBLE_LEN_DEFAULT);
-	GM_OUT(GM_MAC_JAM_SIZE, GM_MAC_JAM_SIZE_DEFAULT);
-	GM_OUT(GM_MAC_ATTEMPT_LIMIT, GM_MAC_ATTEMPT_LIMIT_DEFAULT);
-	GM_OUT(GM_MAC_SLOT_TIME, GM_MAC_SLOT_TIME_DEFAULT);
-	GM_OUT(GM_MAC_CONTROL_TYPE, GM_MAC_CONTROL_TYPE_DEFAULT);
-	
-	/* Setup MAC addresses, clear filters, clear hash table */
-	GM_OUT(GM_MAC_ADDR_NORMAL0, (mac_addr[4] << 8) + mac_addr[5]);
-	GM_OUT(GM_MAC_ADDR_NORMAL1, (mac_addr[2] << 8) + mac_addr[3]);
-	GM_OUT(GM_MAC_ADDR_NORMAL2, (mac_addr[0] << 8) + mac_addr[1]);
-	GM_OUT(GM_MAC_ADDR_ALT0, 0);
-	GM_OUT(GM_MAC_ADDR_ALT1, 0);
-	GM_OUT(GM_MAC_ADDR_ALT2, 0);
-	GM_OUT(GM_MAC_ADDR_CTRL0, 0x0001);
-	GM_OUT(GM_MAC_ADDR_CTRL1, 0xc200);
-	GM_OUT(GM_MAC_ADDR_CTRL2, 0x0180);
-	GM_OUT(GM_MAC_ADDR_FILTER0, 0);
-	GM_OUT(GM_MAC_ADDR_FILTER1, 0);
-	GM_OUT(GM_MAC_ADDR_FILTER2, 0);
-	GM_OUT(GM_MAC_ADDR_FILTER_MASK1_2, 0);
-	GM_OUT(GM_MAC_ADDR_FILTER_MASK0, 0);
-	for (i = 0; i < 27; ++i)
-		GM_OUT(GM_MAC_ADDR_FILTER_HASH0 + i, 0);
-	
-	/* Clear stat counters */
-	GM_OUT(GM_MAC_COLLISION_CTR, 0);
-	GM_OUT(GM_MAC_FIRST_COLLISION_CTR, 0);
-	GM_OUT(GM_MAC_EXCS_COLLISION_CTR, 0);
-	GM_OUT(GM_MAC_LATE_COLLISION_CTR, 0);
-	GM_OUT(GM_MAC_DEFER_TIMER_COUNTER, 0);
-	GM_OUT(GM_MAC_PEAK_ATTEMPTS, 0);
-	GM_OUT(GM_MAC_RX_FRAME_CTR, 0);
-	GM_OUT(GM_MAC_RX_LEN_ERR_CTR, 0);
-	GM_OUT(GM_MAC_RX_ALIGN_ERR_CTR, 0);
-	GM_OUT(GM_MAC_RX_CRC_ERR_CTR, 0);
-	GM_OUT(GM_MAC_RX_CODE_VIOLATION_CTR, 0);
-	
-	/* default to half duplex */
-	GM_OUT(GM_MAC_TX_CONFIG, 0);
-	GM_OUT(GM_MAC_RX_CONFIG, 0);
-	gmac_set_duplex_mode(gm, gm->full_duplex);
-	
-	/* Setup pause thresholds */
-	fifo_size = GM_IN(GM_RX_FIFO_SIZE);
-	GM_OUT(GM_RX_PTH,
-		((fifo_size - ((GM_MAC_MAX_FRAME_SIZE_ALIGN + 8) * 2 / GM_RX_PTH_UNITS))
-			<< GM_RX_PTH_OFF_SHIFT) |
-		((fifo_size - ((GM_MAC_MAX_FRAME_SIZE_ALIGN + 8) * 3 / GM_RX_PTH_UNITS))
-			<< GM_RX_PTH_ON_SHIFT));
-		
-	/* Setup interrupt blanking */
-	if (GM_IN(GM_BIF_CFG) & GM_BIF_CFG_M66EN)
-		GM_OUT(GM_RX_BLANK, (5 << GM_RX_BLANK_INTR_PACKETS_SHIFT)
-			| (8 << GM_RX_BLANK_INTR_TIME_SHIFT));
-	else
-		GM_OUT(GM_RX_BLANK, (5 << GM_RX_BLANK_INTR_PACKETS_SHIFT)
-			| (4 << GM_RX_BLANK_INTR_TIME_SHIFT));	
-}
-
-/*
- * Fill the Rx and Tx rings with good initial values, alloc
- * fresh Rx skb's.
- */
-static void
-gmac_init_rings(struct gmac *gm, int from_irq)
-{
-	int i;
-	struct sk_buff *skb;
-	unsigned char *data;
-	struct gmac_dma_desc *ring;
-	int gfp_flags = GFP_KERNEL;
-
-	if (from_irq || in_interrupt())
-		gfp_flags = GFP_ATOMIC;
-
-	/* init rx ring */
-	ring = (struct gmac_dma_desc *) gm->rxring;
-	memset(ring, 0, NRX * sizeof(struct gmac_dma_desc));
-	for (i = 0; i < NRX; ++i, ++ring) {
-		data = dummy_buf;
-		gm->rx_buff[i] = skb = gmac_alloc_skb(RX_BUF_ALLOC_SIZE, gfp_flags);
-		if (skb != 0) {
-			skb->dev = gm->dev;
-			skb_put(skb, ETH_FRAME_LEN + RX_OFFSET);
-			skb_reserve(skb, RX_OFFSET);
-			data = skb->data - RX_OFFSET;
-		}
-		st_le32(&ring->lo_addr, virt_to_bus(data));
-		st_le32(&ring->size, RX_SZ_OWN | ((RX_BUF_ALLOC_SIZE-RX_OFFSET) << RX_SZ_SHIFT));
-	}
-
-	/* init tx ring */
-	ring = (struct gmac_dma_desc *) gm->txring;
-	memset(ring, 0, NTX * sizeof(struct gmac_dma_desc));
-
-	gm->next_rx = 0;
-	gm->next_tx = 0;
-	gm->tx_gone = 0;
-
-	/* set pointers in chip */
-	mb();
-	GM_OUT(GM_RX_DESC_HI, 0);
-	GM_OUT(GM_RX_DESC_LO, virt_to_bus(gm->rxring));
-	GM_OUT(GM_TX_DESC_HI, 0);
-	GM_OUT(GM_TX_DESC_LO, virt_to_bus(gm->txring));
-}
-
-/*
- * Start the Tx and Rx DMA engines and enable interrupts
- * 
- * Note: The various mdelay(20); come from Darwin implentation. Some
- * tests (doc ?) are needed to replace those with something more intrusive.
- */
-static void
-gmac_start_dma(struct gmac *gm)
-{
-	/* Enable Tx and Rx */
-	GM_BIS(GM_TX_CONF, GM_TX_CONF_DMA_EN);
-	mdelay(20);
-	GM_BIS(GM_RX_CONF, GM_RX_CONF_DMA_EN);
-	mdelay(20);
-	GM_BIS(GM_MAC_RX_CONFIG, GM_MAC_RX_CONF_ENABLE);
-	mdelay(20);
-	GM_BIS(GM_MAC_TX_CONFIG, GM_MAC_TX_CONF_ENABLE);
-	mdelay(20);
-	/* Kick the receiver and enable interrupts */
-	GM_OUT(GM_RX_KICK, NRX);
-	GM_BIC(GM_IRQ_MASK, 	GM_IRQ_TX_INT_ME |
-				GM_IRQ_TX_ALL |
-				GM_IRQ_RX_DONE |
-				GM_IRQ_RX_TAG_ERR |
-				GM_IRQ_MAC_RX |
-				GM_IRQ_MIF |
-				GM_IRQ_BUS_ERROR);
-}
-
-/*
- * Stop the Tx and Rx DMA engines after disabling interrupts
- * 
- * Note: The various mdelay(20); come from Darwin implentation. Some
- * tests (doc ?) are needed to replace those with something more intrusive.
- */
-static void
-gmac_stop_dma(struct gmac *gm)
-{
-	/* disable interrupts */
-	GM_OUT(GM_IRQ_MASK, 0xffffffff);
-	/* Enable Tx and Rx */
-	GM_BIC(GM_TX_CONF, GM_TX_CONF_DMA_EN);
-	mdelay(20);
-	GM_BIC(GM_RX_CONF, GM_RX_CONF_DMA_EN);
-	mdelay(20);
-	GM_BIC(GM_MAC_RX_CONFIG, GM_MAC_RX_CONF_ENABLE);
-	mdelay(20);
-	GM_BIC(GM_MAC_TX_CONFIG, GM_MAC_TX_CONF_ENABLE);
-	mdelay(20);
-}
-
-/*
- * Configure promisc mode and setup multicast hash table
- * filter
- */
-static void
-gmac_set_multicast(struct net_device *dev)
-{
-	struct gmac *gm = (struct gmac *) dev->priv;
-	struct dev_mc_list *dmi = dev->mc_list;
-	int i,j,k,b;
-	u32 crc;
-	int multicast_hash = 0;
-	int multicast_all = 0;
-	int promisc = 0;
-
-	if (gm->sleeping)
-		return;
-
-	/* Lock out others. */
-	netif_stop_queue(dev);
-
-
-	if (dev->flags & IFF_PROMISC)
-		promisc = 1;
-	else if ((dev->flags & IFF_ALLMULTI) /* || (dev->mc_count > XXX) */) {
-		multicast_all = 1;
-	} else {
-		u16 hash_table[16];
-
-		for(i = 0; i < 16; i++)
-			hash_table[i] = 0;
-
-	    	for (i = 0; i < dev->mc_count; i++) {
-			crc = ether_crc_le(6, dmi->dmi_addr);
-			j = crc >> 24;	/* bit number in multicast_filter */
-			hash_table[j >> 4] |= 1 << (15 - (j & 0xf));
-			dmi = dmi->next;
-	    	}
-
-	    	for (i = 0; i < 16; i++)
-	    		GM_OUT(GM_MAC_ADDR_FILTER_HASH0 + (i*4), hash_table[i]);
-		GM_BIS(GM_MAC_RX_CONFIG, GM_MAC_RX_CONF_HASH_ENABLE);
-	    	multicast_hash = 1;
-	}
-
-	if (promisc)
-		GM_BIS(GM_MAC_RX_CONFIG, GM_MAC_RX_CONF_RX_ALL);
-	else
-		GM_BIC(GM_MAC_RX_CONFIG, GM_MAC_RX_CONF_RX_ALL);
-
-	if (multicast_hash)
-		GM_BIS(GM_MAC_RX_CONFIG, GM_MAC_RX_CONF_HASH_ENABLE);
-	else
-		GM_BIC(GM_MAC_RX_CONFIG, GM_MAC_RX_CONF_HASH_ENABLE);
-
-	if (multicast_all)
-		GM_BIS(GM_MAC_RX_CONFIG, GM_MAC_RX_CONF_RX_ALL_MULTI);
-	else
-		GM_BIC(GM_MAC_RX_CONFIG, GM_MAC_RX_CONF_RX_ALL_MULTI);
-	
-	/* Let us get going again. */
-	netif_wake_queue(dev);
-}
-
-/*
- * Open the interface
- */
-static int
-gmac_open(struct net_device *dev)
-{
-	int ret;
-	struct gmac *gm = (struct gmac *) dev->priv;
-
-	/* Power up and reset chip */
-	if (gmac_powerup_and_reset(dev))
-		return -EIO;
-
-	/* Get our interrupt */
-	ret = request_irq(dev->irq, gmac_interrupt, 0, dev->name, dev);
-	if (ret) {
-		printk(KERN_ERR "%s can't get irq %d\n", dev->name, dev->irq);
-		return ret;
-	}
-
-	gm->full_duplex = 0;
-	gm->phy_status = 0;
-	
-	/* Find a PHY */
-	if (!mii_lookup_and_reset(gm))
-		printk(KERN_WARNING "%s WARNING ! Can't find PHY\n", dev->name);
-
-	/* Configure the PHY */
-	mii_setup_phy(gm);
-	
-	/* Initialize the descriptor rings */
-	gmac_init_rings(gm, 0);
-
-	/* Initialize the MAC */
-	gmac_mac_init(gm, dev->dev_addr);
-	
-	/* Initialize the multicast tables & promisc mode if any */
-	gmac_set_multicast(dev);
-	
-	/*
-	 * Check out PHY status and start auto-poll
-	 * 
-	 * Note: do this before enabling interrutps
-	 */
-	mii_interrupt(gm);
-
-	/* Start the chip */
-	gmac_start_dma(gm);
-
-	gm->opened = 1;
-
-	return 0;
-}
-
-/* 
- * Close the interface
- */
-static int
-gmac_close(struct net_device *dev)
-{
-	struct gmac *gm = (struct gmac *) dev->priv;
-	int i;
-
-	gm->opened = 0;
-
-	/* Stop chip and interrupts */
-	gmac_stop_dma(gm);
-
-	/* Stop polling PHY */
-	mii_poll_stop(gm);
-
-	/* Free interrupt */
-	free_irq(dev->irq, dev);
-	
-	/* Shut down chip */
-	gmac_set_power(gm, 0);
-	gm->phy_type = 0;
-
-	/* Empty rings of any remaining gremlins */
-	for (i = 0; i < NRX; ++i) {
-		if (gm->rx_buff[i] != 0) {
-			dev_kfree_skb(gm->rx_buff[i]);
-			gm->rx_buff[i] = 0;
-		}
-	}
-	for (i = 0; i < NTX; ++i) {
-		if (gm->tx_buff[i] != 0) {
-			dev_kfree_skb(gm->tx_buff[i]);
-			gm->tx_buff[i] = 0;
-		}
-	}
-
-	return 0;
-}
-
-#ifdef CONFIG_PMAC_PBOOK
-int
-gmac_sleep_notify(struct pmu_sleep_notifier *self, int when)
-{
-	struct gmac *gm;
-	
-	/* XXX should handle more than one */
-	if (gmacs == NULL)
-		return PBOOK_SLEEP_OK;
-
-	gm = (struct gmac *) gmacs->priv;
-	if (!gm->opened)
-		return PBOOK_SLEEP_OK;
-		
-	switch (when) {
-	case PBOOK_SLEEP_REQUEST:
-		break;
-	case PBOOK_SLEEP_REJECT:
-		break;
-	case PBOOK_SLEEP_NOW:
-		gmac_suspend(gm);
-		break;
-	case PBOOK_WAKE:
-		gmac_resume(gm);
-		break;
-	}
-	return PBOOK_SLEEP_OK;
-}
-#endif /* CONFIG_PMAC_PBOOK */
-
-/*
- * Handle a transmit timeout
- */
-static void
-gmac_tx_timeout(struct net_device *dev)
-{
-	struct gmac *gm = (struct gmac *) dev->priv;
-	int i, timeout;
-	unsigned long flags;
-
-	if (gm->sleeping)
-		return;
-
-	printk (KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
-
-	spin_lock_irqsave(&gm->lock, flags);
-
-	/* Stop chip */
-	gmac_stop_dma(gm);
-	/* Empty Tx ring of any remaining gremlins */
-	gmac_tx_cleanup(dev, 1);
-	/* Empty Rx ring of any remaining gremlins */
-	for (i = 0; i < NRX; ++i) {
-		if (gm->rx_buff[i] != 0) {
-			dev_kfree_skb_irq(gm->rx_buff[i]);
-			gm->rx_buff[i] = 0;
-		}
-	}
-	/* Perform a software reset */
-	GM_OUT(GM_RESET, GM_RESET_TX | GM_RESET_RX);
-	for (timeout = 100; timeout > 0; --timeout) {
-		mdelay(10);
-		if ((GM_IN(GM_RESET) & (GM_RESET_TX | GM_RESET_RX)) == 0) {
-			/* Mask out all chips interrupts */
-			GM_OUT(GM_IRQ_MASK, 0xffffffff);
-			GM_OUT(GM_MAC_TX_RESET, GM_MAC_TX_RESET_NOW);
-			GM_OUT(GM_MAC_RX_RESET, GM_MAC_RX_RESET_NOW);
-			break;
-		}
-	}
-	if (!timeout)
-		printk(KERN_ERR "%s reset chip failed !\n", dev->name);
-	/* Create fresh rings */
-	gmac_init_rings(gm, 1);
-	/* re-initialize the MAC */
-	gmac_mac_init(gm, dev->dev_addr);	
-	/* re-initialize the multicast tables & promisc mode if any */
-	gmac_set_multicast(dev);
-	/* Restart PHY auto-poll */
-	mii_interrupt(gm);
-	/* Restart chip */
-	gmac_start_dma(gm);
-	
-	spin_unlock_irqrestore(&gm->lock, flags);
-
-	netif_wake_queue(dev);
-}
-
-/*
- * Add a packet to the transmit ring
- */
-static int
-gmac_xmit_start(struct sk_buff *skb, struct net_device *dev)
-{
-	struct gmac *gm = (struct gmac *) dev->priv;
-	volatile struct gmac_dma_desc *dp;
-	unsigned long flags;
-	int i;
-
-	if (gm->sleeping)
-		return 1;
-		
-	spin_lock_irqsave(&gm->lock, flags);
-
-	i = gm->next_tx;
-	if (gm->tx_buff[i] != 0) {
-		/* 
-		 * Buffer is full, can't send this packet at the moment
-		 * 
-		 * Can this ever happen in 2.4 ?
-		 */
-		netif_stop_queue(dev);
-		spin_unlock_irqrestore(&gm->lock, flags);
-		return 1;
-	}
-	gm->next_tx = (i + 1) & (NTX - 1);
-	gm->tx_buff[i] = skb;
-	
-	dp = &gm->txring[i];
-	/* FIXME: Interrupt on all packet for now, change this to every N packet,
-	 * with N to be adjusted
-	 */
-	dp->flags = TX_FL_INTERRUPT;
-	dp->hi_addr = 0;
-	st_le32(&dp->lo_addr, virt_to_bus(skb->data));
-	mb();
-	st_le32(&dp->size, TX_SZ_SOP | TX_SZ_EOP | skb->len);
-	mb();
-
-	GM_OUT(GM_TX_KICK, gm->next_tx);
-
-	if (gm->tx_buff[gm->next_tx] != 0)
-		netif_stop_queue(dev);
-
-	spin_unlock_irqrestore(&gm->lock, flags);
-
-	dev->trans_start = jiffies;
-
-	return 0;
-}
-
-/*
- * Handle servicing of the transmit ring by deallocating used
- * Tx packets and restoring flow control when necessary
- */
-static void
-gmac_tx_cleanup(struct net_device *dev, int force_cleanup)
-{
-	struct gmac *gm = (struct gmac *) dev->priv;
-	volatile struct gmac_dma_desc *dp;
-	struct sk_buff *skb;
-	int gone, i;
-
-	i = gm->tx_gone;
-
-	/* Note: If i==gone, we empty the entire ring. This works because
-	 * if the ring was empty, we wouldn't have received the interrupt
-	 */
-	do {
-		gone = GM_IN(GM_TX_COMP);
-		skb = gm->tx_buff[i];
-		if (skb == NULL)
-			break;
-		dp = &gm->txring[i];
-		if (force_cleanup)
-			++gm->stats.tx_errors;
-		else {
-			++gm->stats.tx_packets;
-			gm->stats.tx_bytes += skb->len;
-		}
-		gm->tx_buff[i] = NULL;
-		dev_kfree_skb_irq(skb);
-		if (++i >= NTX)
-			i = 0;
-	} while (force_cleanup || i != gone);
-	gm->tx_gone = i;
-
-	if (!force_cleanup && netif_queue_stopped(dev) &&
-	    (gm->tx_buff[gm->next_tx] == 0))
-		netif_wake_queue(dev);
-}
-
-/*
- * Handle servicing of receive ring
- */
-static void
-gmac_receive(struct net_device *dev)
-{
-	struct gmac *gm = (struct gmac *) dev->priv;
-	int i = gm->next_rx;
-	volatile struct gmac_dma_desc *dp;
-	struct sk_buff *skb, *new_skb;
-	int len, flags, drop, last;
-	unsigned char *data;
-	u16 csum;
-
-	last = -1;
-	for (;;) {
-		dp = &gm->rxring[i];
-		/* Buffer not yet filled, no more Rx buffers to handle */
-		if (ld_le32(&dp->size) & RX_SZ_OWN)
-			break;
-		/* Get packet length, flags, etc... */
-		len = (ld_le32(&dp->size) >> 16) & 0x7fff;
-		flags = ld_le32(&dp->flags);
-		skb = gm->rx_buff[i];
-		drop = 0;
-		new_skb = NULL;
-		csum = ld_le32(&dp->size) & RX_SZ_CKSUM_MASK;
-		
-		/* Handle errors */
-		if ((len < ETH_ZLEN)||(flags & RX_FL_CRC_ERROR)||(!skb)) {
-			++gm->stats.rx_errors;
-			if (len < ETH_ZLEN)
-				++gm->stats.rx_length_errors;
-			if (flags & RX_FL_CRC_ERROR)
-				++gm->stats.rx_crc_errors;
-			if (!skb) {
-				++gm->stats.rx_dropped;
-				skb = gmac_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
-				if (skb) {
-					gm->rx_buff[i] = skb;
-			    		skb->dev = dev;
-			    		skb_put(skb, ETH_FRAME_LEN + RX_OFFSET);
-			    		skb_reserve(skb, RX_OFFSET);
-				}
-			}
-			drop = 1;
-		} else {
-			/* Large packet, alloc a new skb for the ring */
-			if (len > RX_COPY_THRESHOLD) {
-			    new_skb = gmac_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
-			    if(!new_skb) {
-			    	printk(KERN_INFO "%s: Out of SKBs in Rx, packet dropped !\n",
-			    		dev->name);
-			    	drop = 1;
-			    	++gm->stats.rx_dropped;
-			    	goto finish;
-			    }
-
-			    gm->rx_buff[i] = new_skb;
-			    new_skb->dev = dev;
-			    skb_put(new_skb, ETH_FRAME_LEN + RX_OFFSET);
-			    skb_reserve(new_skb, RX_OFFSET);
-			    skb_trim(skb, len);
-			} else {
-			    /* Small packet, copy it to a new small skb */
-			    struct sk_buff *copy_skb = dev_alloc_skb(len + RX_OFFSET);
-
-			    if(!copy_skb) {
-				printk(KERN_INFO "%s: Out of SKBs in Rx, packet dropped !\n",
-					dev->name);
-				drop = 1;
-				++gm->stats.rx_dropped;
-			    	goto finish;
-			    }
-
-			    copy_skb->dev = dev;
-			    skb_reserve(copy_skb, RX_OFFSET);
-			    skb_put(copy_skb, len);
-			    memcpy(copy_skb->data, skb->data, len);
-
-			    new_skb = skb;
-			    skb = copy_skb;
-			}
-		}
-	finish:
-		/* Need to drop packet ? */
-		if (drop) {
-			new_skb = skb;
-			skb = NULL;
-		}
-		
-		/* Put back ring entry */
-		data = new_skb ? (new_skb->data - RX_OFFSET) : dummy_buf;
-		dp->hi_addr = 0;
-		st_le32(&dp->lo_addr, virt_to_bus(data));
-		mb();
-		st_le32(&dp->size, RX_SZ_OWN | ((RX_BUF_ALLOC_SIZE-RX_OFFSET) << RX_SZ_SHIFT));
-		
-		/* Got Rx packet ? */
-		if (skb) {
-			/* Yes, baby, keep that hot ;) */
-			if(!(csum ^ 0xffff))
-				skb->ip_summed = CHECKSUM_UNNECESSARY;
-			else
-				skb->ip_summed = CHECKSUM_NONE;
-			skb->ip_summed = CHECKSUM_NONE;
-			skb->protocol = eth_type_trans(skb, dev);
-			gm->stats.rx_bytes += skb->len;
-			netif_rx(skb);
-			dev->last_rx = jiffies;
-			++gm->stats.rx_packets;
-		}
-		
-		last = i;
-		if (++i >= NRX)
-			i = 0;
-	}
-	gm->next_rx = i;
-	if (last >= 0) {
-		mb();
-		GM_OUT(GM_RX_KICK, last & 0xfffffffc);
-	}
-}
-
-/*
- * Service chip interrupts
- */
-static void
-gmac_interrupt(int irq, void *dev_id, struct pt_regs *regs)
-{
-	struct net_device *dev = (struct net_device *) dev_id;
-	struct gmac *gm = (struct gmac *) dev->priv;
-	unsigned int status;
-
-	status = GM_IN(GM_IRQ_STATUS);
-	if (status & (GM_IRQ_BUS_ERROR | GM_IRQ_MIF))
-		GM_OUT(GM_IRQ_ACK, status & (GM_IRQ_BUS_ERROR | GM_IRQ_MIF));
-	
-	if (status & (GM_IRQ_RX_TAG_ERR | GM_IRQ_BUS_ERROR)) {
-		printk(KERN_ERR "%s: IRQ Error status: 0x%08x\n",
-			dev->name, status);
-	}
-	
-	if (status & GM_IRQ_MIF) {
-		spin_lock(&gm->lock);
-		mii_interrupt(gm);
-		spin_unlock(&gm->lock);
-	}
-	
-	if (status & GM_IRQ_RX_DONE) {
-		spin_lock(&gm->lock);
-		gmac_receive(dev);
-		spin_unlock(&gm->lock);
-	}
-		
-	if (status & (GM_IRQ_TX_INT_ME | GM_IRQ_TX_ALL)) {
-		spin_lock(&gm->lock);
-		gmac_tx_cleanup(dev, 0);
-		spin_unlock(&gm->lock);
-	}
-}
-
-/*
- * Retreive some error stats from chip and return them
- * to above layer
- */
-static struct net_device_stats *
-gmac_stats(struct net_device *dev)
-{
-	struct gmac *gm = (struct gmac *) dev->priv;
-	struct net_device_stats *stats = &gm->stats;
-
-	if (gm && gm->opened && !gm->sleeping) {
-		stats->rx_crc_errors += GM_IN(GM_MAC_RX_CRC_ERR_CTR);
-		GM_OUT(GM_MAC_RX_CRC_ERR_CTR, 0);
-
-		stats->rx_frame_errors += GM_IN(GM_MAC_RX_ALIGN_ERR_CTR);
-		GM_OUT(GM_MAC_RX_ALIGN_ERR_CTR, 0);
-
-		stats->rx_length_errors += GM_IN(GM_MAC_RX_LEN_ERR_CTR);
-		GM_OUT(GM_MAC_RX_LEN_ERR_CTR, 0);
-
-		stats->tx_aborted_errors += GM_IN(GM_MAC_EXCS_COLLISION_CTR);
-
-		stats->collisions +=
-			(GM_IN(GM_MAC_EXCS_COLLISION_CTR) +
-			 GM_IN(GM_MAC_LATE_COLLISION_CTR));
-		GM_OUT(GM_MAC_EXCS_COLLISION_CTR, 0);
-		GM_OUT(GM_MAC_LATE_COLLISION_CTR, 0);
-	}
-
-	return stats;
-}
-
-static int __init
-gmac_probe(void)
-{
-	struct device_node *gmac;
-
-	/* We bump use count during probe since get_free_page can sleep
-	 * which can be a race condition if module is unloaded at this
-	 * point.
-	 */
-	MOD_INC_USE_COUNT;
-	
-	/*
-	 * We don't use PCI scanning on pmac since the GMAC cell is disabled
-	 * by default, and thus absent from kernel original PCI probing.
-	 */
-	for (gmac = find_compatible_devices("network", "gmac"); gmac != 0;
-	     gmac = gmac->next)
-		gmac_probe1(gmac);
-
-#ifdef CONFIG_PMAC_PBOOK
-	if (gmacs)
-		pmu_register_sleep_notifier(&gmac_sleep_notifier);
-#endif
-
-	MOD_DEC_USE_COUNT;
-
-	return gmacs? 0: -ENODEV;
-}
-
-static void
-gmac_probe1(struct device_node *gmac)
-{
-	struct gmac *gm;
-	unsigned long tx_descpage, rx_descpage;
-	unsigned char *addr;
-	struct net_device *dev;
-	int i;
-
-	if (gmac->n_addrs < 1 || gmac->n_intrs < 1) {
-		printk(KERN_ERR "can't use GMAC %s: %d addrs and %d intrs\n",
-		       gmac->full_name, gmac->n_addrs, gmac->n_intrs);
-		return;
-	}
-
-	addr = get_property(gmac, "local-mac-address", NULL);
-	if (addr == NULL) {
-		printk(KERN_ERR "Can't get mac-address for GMAC %s\n",
-		       gmac->full_name);
-		return;
-	}
-
-	if (dummy_buf == NULL) {
-		dummy_buf = kmalloc(DUMMY_BUF_LEN, GFP_KERNEL);
-		if (dummy_buf == NULL) {
-			printk(KERN_ERR "GMAC: failed to allocated dummy buffer\n");
-			return;
-		}
-	}
-
-	tx_descpage = get_free_page(GFP_KERNEL);
-	if (tx_descpage == 0) {
-		printk(KERN_ERR "GMAC: can't get a page for tx descriptors\n");
-		return;
-	}
-	rx_descpage = get_free_page(GFP_KERNEL);
-	if (rx_descpage == 0) {
-		printk(KERN_ERR "GMAC: can't get a page for rx descriptors\n");
-		goto out_txdesc;
-	}
-
-	dev = init_etherdev(NULL, sizeof(struct gmac));
-	if (!dev) {
-		printk(KERN_ERR "GMAC: init_etherdev failed, out of memory\n");
-		goto out_rxdesc;
-	}
-	SET_MODULE_OWNER(dev);
-
-	gm = dev->priv;
-	dev->base_addr = gmac->addrs[0].address;
-	gm->regs = (volatile unsigned int *)
-		ioremap(gmac->addrs[0].address, 0x10000);
-	if (!gm->regs) {
-		printk(KERN_ERR "GMAC: unable to map I/O registers\n");
-		goto out_unreg;
-	}
-	dev->irq = gmac->intrs[0].line;
-	gm->dev = dev;
-	gm->of_node = gmac;
-
-	spin_lock_init(&gm->lock);
-	
-	if (pci_device_from_OF_node(gmac, &gm->pci_bus, &gm->pci_devfn)) {
-		gm->pci_bus = gm->pci_devfn = 0xff;
-		printk(KERN_ERR "Can't locate GMAC PCI entry\n");
-	}
-
-	printk(KERN_INFO "%s: GMAC at", dev->name);
-	for (i = 0; i < 6; ++i) {
-		dev->dev_addr[i] = addr[i];
-		printk("%c%.2x", (i? ':': ' '), addr[i]);
-	}
-	printk(", driver " GMAC_VERSION "\n");
-
-	gm->tx_desc_page = tx_descpage;
-	gm->rx_desc_page = rx_descpage;
-	gm->rxring = (volatile struct gmac_dma_desc *) rx_descpage;
-	gm->txring = (volatile struct gmac_dma_desc *) tx_descpage;
-
-	gm->phy_addr = 0;
-	gm->opened = 0;
-	gm->sleeping = 0;
-
-	dev->open = gmac_open;
-	dev->stop = gmac_close;
-	dev->hard_start_xmit = gmac_xmit_start;
-	dev->get_stats = gmac_stats;
-	dev->set_multicast_list = &gmac_set_multicast;
-	dev->tx_timeout = &gmac_tx_timeout;
-	dev->watchdog_timeo = 5*HZ;
-
-	ether_setup(dev);
-
-	gm->next_gmac = gmacs;
-	gmacs = dev;
-	return;
-
-out_unreg:
-	unregister_netdev(dev);
-	kfree(dev);
-out_rxdesc:
-	free_page(rx_descpage);
-out_txdesc:
-	free_page(tx_descpage);
-}
-
-MODULE_AUTHOR("Paul Mackerras/Ben Herrenschmidt");
-MODULE_DESCRIPTION("PowerMac GMAC driver.");
-MODULE_LICENSE("GPL");
-
-static void __exit gmac_cleanup_module(void)
-{
-	struct gmac *gm;
-	struct net_device *dev;
-
-#ifdef CONFIG_PMAC_PBOOK
-	if (gmacs)
-		pmu_unregister_sleep_notifier(&gmac_sleep_notifier);
-#endif
-
-	while ((dev = gmacs) != NULL) {
-		gm = (struct gmac *) dev->priv;
-		unregister_netdev(dev);
-		iounmap((void *) gm->regs);
-		free_page(gm->tx_desc_page);
-		free_page(gm->rx_desc_page);
-		gmacs = gm->next_gmac;
-		kfree(dev);
-	}
-	if (dummy_buf != NULL) {
-		kfree(dummy_buf);
-		dummy_buf = NULL;
-	}
-}
-
-module_init(gmac_probe);
-module_exit(gmac_cleanup_module);
diff --git a/drivers/net/gmac.h b/drivers/net/gmac.h
deleted file mode 100644
index a06dc8caf95e..000000000000
--- a/drivers/net/gmac.h
+++ /dev/null
@@ -1,946 +0,0 @@
-/*
- * Definitions for the GMAC ethernet chip, used in the
- * Apple G4 powermac.
- */
-
-
-/* 
- * GMAC register definitions
- * 
- * Note: We encode the register size the same way Apple does. I didn't copy
- *       Apple's source as-is to avoid licence issues however. That's really
- *       painful to re-define all those registers ...
- *       The constants themselves were partially found in OF code, in Sun
- *       GEM driver and in Apple's Darwin GMAC driver
- */
-
-#define REG_SZ_8			0x00000000
-#define REG_SZ_16			0x40000000
-#define REG_SZ_32			0x80000000
-#define REG_MASK			0x0FFFFFFF
-
-	/*
-	 * Global registers
-	 */
-
-/* -- 0x0004	RW	Global configuration
- * d: 0x00000042
- */
-#define GM_GCONF			(0x0004 | REG_SZ_16)
-#define GM_GCONF_BURST_SZ		0x0001		/* 1: 64 bytes/burst, 0: infinite */
-#define GM_GCONF_TXDMA_LIMIT_MASK	0x003e		/* 5-1: No of 64 bytes transfers */
-#define GM_GCONF_TXDMA_LIMIT_SHIFT	1
-#define GM_GCONF_RXDMA_LIMIT_MASK	0x07c0		/* 10-6: No of 64 bytes transfers */
-#define GM_GCONF_RXDMA_LIMIT_SHIFT	6
-
-/* -- 0x000C	R-C	Global Interrupt status. 
- * d: 0x00000000	bits 0-6 cleared on read (C)
- */
-#define GM_IRQ_STATUS			(0x000c | REG_SZ_32)
-#define GM_IRQ_TX_INT_ME		0x00000001	/* C Frame with INT_ME bit set in fifo */
-#define GM_IRQ_TX_ALL			0x00000002	/* C TX descriptor ring empty */
-#define GM_IRQ_TX_DONE			0x00000004	/* C moved from host to TX fifo */
-#define GM_IRQ_RX_DONE			0x00000010	/* C moved from RX fifo to host */
-#define GM_IRQ_RX_NO_BUF		0x00000020	/* C No RX buffer available */
-#define GM_IRQ_RX_TAG_ERR		0x00000040	/* C RX tag error */
-#define GM_IRQ_PCS			0x00002000	/* PCS interrupt ? */
-#define GM_IRQ_MAC_TX			0x00004000	/* MAC tx register set */
-#define GM_IRQ_MAC_RX			0x00008000	/* MAC rx register set  */
-#define GM_IRQ_MAC_CTRL			0x00010000	/* MAC control register set  */
-#define GM_IRQ_MIF			0x00020000	/* MIF status register set */
-#define GM_IRQ_BUS_ERROR		0x00040000	/* Bus error status register set */
-#define GM_IRQ_TX_COMP			0xfff80000	/* TX completion mask */
-	
-/* -- 0x0010	RW	Interrupt mask. 
- * d: 0xFFFFFFFF
- */
-#define GM_IRQ_MASK			(0x0010 | REG_SZ_32)
-
-/* -- 0x0014	WO	Interrupt ack.
- * 			Ack. "high" interrupts
- */
-#define GM_IRQ_ACK			(0x0014 | REG_SZ_32)
-
-/* -- 0x001C	WO	Alias of status register (no auto-clear of "low" interrupts)
- */
-#define GM_IRQ_ALT_STAT			(0x001C | REG_SZ_32)
-
-/* -- 0x1000	R-C	PCI Error status register
- */
-#define GM_PCI_ERR_STAT			(0x1000 | REG_SZ_8)
-#define GM_PCI_ERR_BAD_ACK		0x01		/* Bad Ack64 */
-#define GM_PCI_ERR_TIMEOUT		0x02		/* Transaction timeout */
-#define GM_PCI_ERR_OTHER		0x04		/* Any other PCI error */
-	
-/* -- 0x1004	RW	PCI Error mask register
- * d: 0xFFFFFFFF
- */
-#define GM_PCI_ERR_MASK			(0x1004 | REG_SZ_8)
-
-/* -- 0x1008	RW	BIF Configuration
- * d: 0x00000000
- */
-#define GM_BIF_CFG			(0x1008 | REG_SZ_8)
-#define	GM_BIF_CFG_SLOWCLK		0x01		/* for parity error timing */
-#define	GM_BIF_CFG_HOST_64		0x02		/* 64-bit host */
-#define	GM_BIF_CFG_B64D_DIS		0x04		/* no 64-bit wide data cycle */
-#define	GM_BIF_CFG_M66EN		0x08		/* Read-only: sense if configured for 66MHz */
-	
-/* -- 0x100C	RW	BIF Diagnostic ???
- */
-#define GM_BIF_DIAG			(0x100C | REG_SZ_32)
-#define GM_BIF_DIAG_BURST_STATE		0x007F0000
-#define GM_BIF_DIAG_STATE_MACH		0xFF000000
-
-/* -- 0x1010	RW	Software reset
- *			Lower two bits reset TX and RX, both reset whole gmac. They come back
- *			to 0 when reset is complete.
- *			bit 2 force RSTOUT# pin when set (PHY reset)
- */
-#define GM_RESET			(0x1010 | REG_SZ_8)
-#define	GM_RESET_TX			0x01
-#define	GM_RESET_RX			0x02
-#define	GM_RESET_RSTOUT			0x04		/* PHY reset */
-
-
-	/*
-	 * Tx DMA Registers
-	 */
-
-/* -- 0x2000	RW	Tx Kick
- * d: 0x00000000	Written by the host with the last tx descriptor number +1 to send
- */
-#define GM_TX_KICK			(0x2000 | REG_SZ_16)
-
-/* -- 0x2004	RW	Tx configuration
- * d: 0x118010		Controls operation of Tx DMA channel
- */
-
-#define GM_TX_CONF			(0x2004 | REG_SZ_32)
-#define	GM_TX_CONF_DMA_EN		0x00000001	/* Tx DMA enable */
-#define	GM_TX_CONF_RING_SZ_MASK		0x0000001e	/* Tx desc ring size */
-#define GM_TX_CONF_RING_SZ_SHIFT	1		/* Tx desc ring size shift */
-#define GM_TX_CONF_FIFO_PIO		0x00000020	/* Tx fifo PIO select ??? */
-#define	GM_TX_CONF_FIFO_THR_MASK	0x001ffc00	/* Tx fifo threshold */
-#define GM_TX_CONF_FIFO_THR_SHIFT	10		/* Tx fifo threshold shift */
-#define GM_TX_CONF_FIFO_THR_DEFAULT	0x7ff		/* Tx fifo threshold default */
-#define	GM_TX_CONF_PACED_MODE		0x00100000	/* 1: tx_all irq after last descriptor */
-							/* 0: tx_all irq when tx fifo empty */
-#define	GM_TX_RING_SZ_32		(0 << 1)
-#define	GM_TX_RING_SZ_64		(1 << 1)
-#define	GM_TX_RING_SZ_128		(2 << 1)
-#define	GM_TX_RING_SZ_256		(3 << 1)
-#define	GM_TX_RING_SZ_512		(4 << 1)
-#define	GM_TX_RING_SZ_1024		(5 << 1)
-#define	GM_TX_RING_SZ_2048		(6 << 1)
-#define	GM_TX_RING_SZ_4086		(7 << 1)
-#define	GM_TX_RING_SZ_8192		(8 << 1)
-
-/* -- 0x2008	RW	Tx descriptor ring base low
- * -- 0x200C	RW	Tx descriptor ring base high
- *
- * Base of tx ring, must be 2k aligned
- */
-#define GM_TX_DESC_LO			(0x2008 | REG_SZ_32)
-#define GM_TX_DESC_HI			(0x200C | REG_SZ_32)
- 
-/* -- 0x2100	RW	Tx Completion
- * d: 0x00000000	Written by the gmac with the last tx descriptor number +1 sent
- */
-#define GM_TX_COMP			(0x2100 | REG_SZ_16)
-
-
-	/*
-	 * Rx DMA registers
-	 */
-
-
-/* -- 0x4000	RW	Rx configuration
- * d: 0x1000010		Controls operation of Rx DMA channel
- */
-
-#define GM_RX_CONF			(0x4000 | REG_SZ_32)
-#define	GM_RX_CONF_DMA_EN		0x00000001	/* Rx DMA enable */
-#define	GM_RX_CONF_RING_SZ_MASK		0x0000001e	/* Rx desc ring size */
-#define GM_RX_CONF_RING_SZ_SHIFT	1
-#define	GM_RX_CONF_BATCH_DIS		0x00000020	/* Rx batch disable */
-#define	GM_RX_CONF_FBYTE_OFF_MASK	0x00001c00	/* First byte offset (10-12) */
-#define GM_RX_CONF_FBYTE_OFF_SHIFT	10
-#define	GM_RX_CONF_CHK_START_MASK	0x000FE000	/* Checksum start offset */
-#define GM_RX_CONF_CHK_START_SHIFT	13
-#define	GM_RX_CONF_DMA_THR_MASK		0x07000000	/* Rx DMA threshold */
-#define GM_RX_CONF_DMA_THR_SHIFT	24		/* Rx DMA threshold shift */
-#define GM_RX_CONF_DMA_THR_DEFAULT	1		/* Rx DMA threshold default */
-
-#define	GM_RX_RING_SZ_32		(0 << 1)
-#define	GM_RX_RING_SZ_64		(1 << 1)
-#define	GM_RX_RING_SZ_128		(2 << 1)
-#define	GM_RX_RING_SZ_256		(3 << 1)
-#define	GM_RX_RING_SZ_512		(4 << 1)
-#define	GM_RX_RING_SZ_1024		(5 << 1)
-#define	GM_RX_RING_SZ_2048		(6 << 1)
-#define	GM_RX_RING_SZ_4086		(7 << 1)
-#define	GM_RX_RING_SZ_8192		(8 << 1)
-
-/* -- 0x4004	RW	Rx descriptor ring base low
- * -- 0x4008	RW	Rx descriptor ring base high
- *
- * Base of rx ring
- */
-#define GM_RX_DESC_LO			(0x4004 | REG_SZ_32)
-#define GM_RX_DESC_HI			(0x4008 | REG_SZ_32)
-
-/* -- 0x4020	RW	Rx pause threshold
- * d: 0x000000f8	
- *
- * Two PAUSE thresholds are used to define when PAUSE flow control frames are
- * emitted by GEM. The granularity of these thresholds is in 64 byte increments.
- * XOFF PAUSE frames use the pause_time value pre-programmed in the
- * Send PAUSE MAC Register.
- * XON PAUSE frames use a pause_time of 0.
- */
-#define GM_RX_PTH			(0x4020 | REG_SZ_32)
-			/*
-			 * 0-8: XOFF PAUSE emitted when RX FIFO
-			 * occupancy rises above this value (times 64 bytes)
-			 */
-#define	GM_RX_PTH_OFF_MASK		0x000001ff
-#define GM_RX_PTH_OFF_SHIFT		0
-			/*
-			 * 12-20: XON PAUSE emitted when RX FIFO
-			 * occupancy falls below this value (times 64 bytes)
-			 */
-#define	GM_RX_PTH_ON_MASK		0x001ff000
-#define	GM_RX_PTH_ON_SHIFT		12
-
-#define GM_RX_PTH_UNITS			64
-
-/* -- 0x4100	RW	Rx Kick
- * d: 0x00000000	The last valid RX descriptor is the one right before the value of the
- *                      register. Initially set to 0 on reset. RX descriptors must be posted
- *                      in multiples of 4. The first descriptor should be cache-line aligned
- *                      for best performance.
- */
-#define GM_RX_KICK			(0x4100 | REG_SZ_16)
-
-/* -- 0x4104	RW	Rx Completion
- * d: 0x00000000	All descriptors upto but excluding the register value are ready to be
- *                      processed by the host.
- */
-#define GM_RX_COMP			(0x4104 | REG_SZ_16)
- 
-/* -- 0x4108	RW	Rx Blanking
- * d: 0x00000000	Written by the gmac with the last tx descriptor number +1 sent
- *
- * Defines the values used for receive interrupt blanking.
- * For INTR_TIME field, every count is 2048 PCI clock time. For 66 Mhz, each
- * count is about 15 ns.
- */
-#define GM_RX_BLANK			(0x4108 | REG_SZ_32)
-			/*
-			 * 0-8:no.of pkts to be recvd since the last RX_DONE
-			 * interrupt, before a new interrupt
-			 */
-#define	GM_RX_BLANK_INTR_PACKETS_MASK	0x000001ff
-#define	GM_RX_BLANK_INTR_PACKETS_SHIFT	0
-			/*
-			 * 12-19 : no. of clocks to be counted since the last
-			 * RX_DONE interrupt, before a new interrupt
-			 */
-#define	GM_RX_BLANK_INTR_TIME_MASK	0x000ff000
-#define	GM_RX_BLANK_INTR_TIME_SHIFT	12
-
-#define GM_RX_BLANK_UNITS		2048
-
-/* -- 0x4120	RO	Rx fifo size
- *
- * This 11-bit RO register indicates the size, in 64-byte multiples, of the
- * RX FIFO. Software should use it to properly configure the PAUSE thresholds.
- * The value read is 0x140, indicating a 20kbyte RX FIFO.
- * -------------------------------------------------------------------------
- */
-#define GM_RX_FIFO_SIZE			(0x4120 | REG_SZ_16)
-#define GM_RZ_FIFO_SIZE_UNITS		64
-
-
-	/*
-	 * MAC regisers
-	 */
-
-/* -- 0x6000		MAC Tx reset control
- */
-#define GM_MAC_TX_RESET			(0x6000 | REG_SZ_8)
-#define GM_MAC_TX_RESET_NOW		0x01
-
-/* -- 0x6004		MAC Rx reset control
- */
-#define GM_MAC_RX_RESET			(0x6004 | REG_SZ_8)
-#define GM_MAC_RX_RESET_NOW		0x01
-
-/* -- 0x6008		Send Pause command register
- */
-#define GM_MAC_SND_PAUSE		(0x6008 | REG_SZ_32)
-#define GM_MAC_SND_PAUSE_TIME_MASK	0x0000ffff
-#define GM_MAC_SND_PAUSE_TIME_SHIFT	0
-#define GM_MAC_SND_PAUSE_NOW		0x00010000
-#define GM_MAC_SND_PAUSE_DEFAULT	0x00001bf0
-
-/* -- 0x6010		MAC transmit status
- */
-#define GM_MAC_TX_STATUS		(0x6010 | REG_SZ_16)
-#define GM_MAC_TX_STAT_SENT		0x0001
-#define GM_MAC_TX_STAT_UNDERRUN		0x0002
-#define GM_MAC_TX_STAT_MAX_PKT_ERR	0x0004
-#define GM_MAC_TX_STAT_NORM_COLL_OVF	0x0008
-#define GM_MAC_TX_STAT_EXCS_COLL_OVF	0x0010
-#define GM_MAC_TX_STAT_LATE_COLL_OVF	0x0020
-#define GM_MAC_TX_STAT_FIRS_COLL_OVF	0x0040
-#define GM_MAC_TX_STAT_DEFER_TIMER_OVF	0x0080
-#define GM_MAC_TX_STAT_PEAK_ATTMP_OVF	0x0100
-
-/* -- 0x6014		MAC receive status
- */
-#define GM_MAC_RX_STATUS		(0x6014 | REG_SZ_16)
-#define GM_MAC_RX_STAT_RECEIVED		0x0001
-#define GM_MAC_RX_STAT_FIFO_OVF		0x0002
-#define GM_MAC_RX_STAT_FRAME_CTR_OVF	0x0004
-#define GM_MAC_RX_STAT_ALIGN_ERR_OVF	0x0008
-#define GM_MAC_RX_STAT_CRC_ERR_OVF	0x0010
-#define GM_MAC_RX_STAT_LEN_ERR_OVF	0x0020
-#define GM_MAC_RX_STAT_CODE_ERR_OVF	0x0040
-
-/* -- 0x6018		MAC control & status
- */
-#define GM_MAC_CTRLSTAT			(0x6018 | REG_SZ_32)
-#define GM_MAC_CTRLSTAT_PAUSE_RCVD	0x00000001
-#define GM_MAC_CTRLSTAT_PAUSE_STATE	0x00000002
-#define GM_MAC_CTRLSTAT_PAUSE_NOT	0x00000004
-#define GM_MAC_CTRLSTAT_PAUSE_TIM_MASK	0xffff0000
-#define GM_MAC_CTRLSTAT_PAUSE_TIM_SHIFT	16
-
-/* -- 0x6020		MAC Tx mask
- * 			Same bits as MAC Tx status
- */
-#define GM_MAC_TX_MASK			(0x6020 | REG_SZ_16)
-
-/* -- 0x6024		MAC Rx mask
- * 			Same bits as MAC Rx status
- */
-#define GM_MAC_RX_MASK			(0x6024 | REG_SZ_16)
-
-/* -- 0x6028		MAC Control/Status mask
- * 			Same bits as MAC control/status low order byte
- */
-#define GM_MAC_CTRLSTAT_MASK		(0x6024 | REG_SZ_8)
-
-/* -- 0x6030		MAC Tx configuration
- */
-#define GM_MAC_TX_CONFIG		(0x6030 | REG_SZ_16)
-#define GM_MAC_TX_CONF_ENABLE		0x0001
-#define GM_MAC_TX_CONF_IGNORE_CARRIER	0x0002
-#define GM_MAC_TX_CONF_IGNORE_COLL	0x0004
-#define GM_MAC_TX_CONF_ENABLE_IPG0	0x0008
-#define GM_MAC_TX_CONF_DONT_GIVEUP	0x0010
-#define GM_MAC_TX_CONF_DONT_GIVEUP_NLMT	0x0020
-#define GM_MAC_TX_CONF_NO_BACKOFF	0x0040
-#define GM_MAC_TX_CONF_SLOWDOWN		0x0080
-#define GM_MAC_TX_CONF_NO_FCS		0x0100
-#define GM_MAC_TX_CONF_CARRIER_EXT	0x0200
-
-/* -- 0x6034		MAC Rx configuration
- */
-#define GM_MAC_RX_CONFIG		(0x6034 | REG_SZ_16)
-#define GM_MAC_RX_CONF_ENABLE		0x0001
-#define GM_MAC_RX_CONF_STRIP_PAD	0x0002
-#define GM_MAC_RX_CONF_STIP_FCS		0x0004
-#define GM_MAC_RX_CONF_RX_ALL		0x0008
-#define GM_MAC_RX_CONF_RX_ALL_MULTI	0x0010
-#define GM_MAC_RX_CONF_HASH_ENABLE	0x0020
-#define GM_MAC_RX_CONF_ADDR_FLTR_ENABLE	0x0040
-#define GM_MAC_RX_CONF_PASS_ERROR_FRAM	0x0080
-#define GM_MAC_RX_CONF_CARRIER_EXT	0x0100
-
-/* -- 0x6038		MAC control configuration
- */
-#define GM_MAC_CTRL_CONFIG		(0x6038 | REG_SZ_8)
-#define GM_MAC_CTRL_CONF_SND_PAUSE_EN	0x01
-#define GM_MAC_CTRL_CONF_RCV_PAUSE_EN	0x02
-#define GM_MAC_CTRL_CONF_PASS_CTRL_FRAM	0x04
-
-/* -- 0x603c		MAC XIF configuration */
-#define GM_MAC_XIF_CONFIG		(0x603c | REG_SZ_8)
-#define GM_MAC_XIF_CONF_TX_MII_OUT_EN	0x01
-#define GM_MAC_XIF_CONF_MII_INT_LOOP	0x02
-#define GM_MAC_XIF_CONF_DISABLE_ECHO	0x04
-#define GM_MAC_XIF_CONF_GMII_MODE	0x08
-#define GM_MAC_XIF_CONF_MII_BUFFER_EN	0x10
-#define GM_MAC_XIF_CONF_LINK_LED	0x20
-#define GM_MAC_XIF_CONF_FULL_DPLX_LED	0x40
-
-/* -- 0x6040		MAC inter-packet GAP 0
- */
-#define GM_MAC_INTR_PKT_GAP0		(0x6040 | REG_SZ_8)
-#define GM_MAC_INTR_PKT_GAP0_DEFAULT	0x00
-
-/* -- 0x6044		MAC inter-packet GAP 1
- */
-#define GM_MAC_INTR_PKT_GAP1		(0x6044 | REG_SZ_8)
-#define GM_MAC_INTR_PKT_GAP1_DEFAULT	0x08
-
-/* -- 0x6048		MAC inter-packet GAP 2
- */
-#define GM_MAC_INTR_PKT_GAP2		(0x6048 | REG_SZ_8)
-#define GM_MAC_INTR_PKT_GAP2_DEFAULT	0x04
-
-/* -- 604c		MAC slot time
- */
-#define GM_MAC_SLOT_TIME		(0x604C | REG_SZ_16)
-#define GM_MAC_SLOT_TIME_DEFAULT	0x0040
-
-/* -- 6050		MAC minimum frame size
- */
-#define GM_MAC_MIN_FRAME_SIZE		(0x6050 | REG_SZ_16)
-#define GM_MAC_MIN_FRAME_SIZE_DEFAULT	0x0040
-
-/* -- 6054		MAC maximum frame size
- */
-#define GM_MAC_MAX_FRAME_SIZE		(0x6054 | REG_SZ_16)
-#define GM_MAC_MAX_FRAME_SIZE_DEFAULT	0x05ee
-#define GM_MAC_MAX_FRAME_SIZE_ALIGN	0x5f0
-
-/* -- 6058		MAC preamble length
- */
-#define GM_MAC_PREAMBLE_LEN		(0x6058 | REG_SZ_16)
-#define GM_MAC_PREAMBLE_LEN_DEFAULT	0x0007
-
-/* -- 605c		MAC jam size
- */
-#define GM_MAC_JAM_SIZE			(0x605c | REG_SZ_8)
-#define GM_MAC_JAM_SIZE_DEFAULT		0x04
-
-/* -- 6060		MAC attempt limit
- */
-#define GM_MAC_ATTEMPT_LIMIT		(0x6060 | REG_SZ_8)
-#define GM_MAC_ATTEMPT_LIMIT_DEFAULT	0x10
-
-/* -- 6064		MAC control type
- */
-#define GM_MAC_CONTROL_TYPE		(0x6064 | REG_SZ_16)
-#define GM_MAC_CONTROL_TYPE_DEFAULT	0x8808
-
-/* -- 6080		MAC address 15..0
- * -- 6084		MAC address 16..31
- * -- 6088		MAC address 32..47
- */
-#define GM_MAC_ADDR_NORMAL0		(0x6080 | REG_SZ_16)
-#define GM_MAC_ADDR_NORMAL1		(0x6084 | REG_SZ_16)
-#define GM_MAC_ADDR_NORMAL2		(0x6088 | REG_SZ_16)
-
-/* -- 608c		MAC alternate address 15..0
- * -- 6090		MAC alternate address 16..31
- * -- 6094		MAC alternate address 32..47
- */
-#define GM_MAC_ADDR_ALT0		(0x608c | REG_SZ_16)
-#define GM_MAC_ADDR_ALT1		(0x6090 | REG_SZ_16)
-#define GM_MAC_ADDR_ALT2		(0x6094 | REG_SZ_16)
-
-/* -- 6098		MAC control address 15..0
- * -- 609c		MAC control address 16..31
- * -- 60a0		MAC control address 32..47
- */
-#define GM_MAC_ADDR_CTRL0		(0x6098 | REG_SZ_16)
-#define GM_MAC_ADDR_CTRL1		(0x609c | REG_SZ_16)
-#define GM_MAC_ADDR_CTRL2		(0x60a0 | REG_SZ_16)
-
-/* -- 60a4		MAC address filter (0_0)
- * -- 60a8		MAC address filter (0_1)
- * -- 60ac		MAC address filter (0_2)
- */
-#define GM_MAC_ADDR_FILTER0		(0x60a4 | REG_SZ_16)
-#define GM_MAC_ADDR_FILTER1		(0x60a8 | REG_SZ_16)
-#define GM_MAC_ADDR_FILTER2		(0x60ac | REG_SZ_16)
-
-/* -- 60b0		MAC address filter mask 1,2
- */
-#define GM_MAC_ADDR_FILTER_MASK1_2	(0x60b0 | REG_SZ_8)
-
-/* -- 60b4		MAC address filter mask 0
- */
-#define GM_MAC_ADDR_FILTER_MASK0	(0x60b4 | REG_SZ_16)
-
-/* -- [60c0 .. 60fc]	MAC hash table
- */
-#define GM_MAC_ADDR_FILTER_HASH0	(0x60c0 | REG_SZ_16)
-
-/* -- 6100		MAC normal collision counter
- */
-#define GM_MAC_COLLISION_CTR		(0x6100 | REG_SZ_16)
-
-/* -- 6104		MAC 1st successful collision counter
- */
-#define GM_MAC_FIRST_COLLISION_CTR	(0x6104 | REG_SZ_16)
-
-/* -- 6108		MAC excess collision counter
- */
-#define GM_MAC_EXCS_COLLISION_CTR	(0x6108 | REG_SZ_16)
-
-/* -- 610c		MAC late collision counter
- */
-#define GM_MAC_LATE_COLLISION_CTR	(0x610c | REG_SZ_16)
-
-/* -- 6110		MAC defer timer counter
- */
-#define GM_MAC_DEFER_TIMER_COUNTER	(0x6110 | REG_SZ_16)
-
-/* -- 6114		MAC peak attempts
- */
-#define GM_MAC_PEAK_ATTEMPTS		(0x6114 | REG_SZ_16)
-
-/* -- 6118		MAC Rx frame counter
- */
-#define GM_MAC_RX_FRAME_CTR		(0x6118 | REG_SZ_16)
-
-/* -- 611c		MAC Rx length error counter
- */
-#define GM_MAC_RX_LEN_ERR_CTR		(0x611c | REG_SZ_16)
-
-/* -- 6120		MAC Rx alignment error counter
- */
-#define GM_MAC_RX_ALIGN_ERR_CTR		(0x6120 | REG_SZ_16)
-
-/* -- 6124		MAC Rx CRC error counter
- */
-#define GM_MAC_RX_CRC_ERR_CTR		(0x6124 | REG_SZ_16)
-
-/* -- 6128		MAC Rx code violation error counter
- */
-#define GM_MAC_RX_CODE_VIOLATION_CTR	(0x6128 | REG_SZ_16)
-
-/* -- 6130		MAC random number seed
- */
-#define GM_MAC_RANDOM_SEED		(0x6130 | REG_SZ_16)
-
-/* -- 6134		MAC state machine
- */
-#define GM_MAC_STATE_MACHINE		(0x6134 | REG_SZ_8)
-
-
-	/*
-	 * MIF registers
-	 */
-
-
-/* -- 0x6200	RW	MIF bit bang clock
- */
-#define GM_MIF_BB_CLOCK			(0x6200 | REG_SZ_8)
-
-/* -- 0x6204	RW	MIF bit bang data
- */
-#define GM_MIF_BB_DATA			(0x6204 | REG_SZ_8)
-
-/* -- 0x6208	RW	MIF bit bang output enable
- */
-#define GM_MIF_BB_OUT_ENABLE		(0x6208 | REG_SZ_8)
-
-/* -- 0x620c	RW	MIF frame control & data
- */
-#define GM_MIF_FRAME_CTL_DATA		(0x620c | REG_SZ_32)
-#define GM_MIF_FRAME_START_MASK		0xc0000000
-#define GM_MIF_FRAME_START_SHIFT	30
-#define GM_MIF_FRAME_OPCODE_MASK	0x30000000
-#define GM_MIF_FRAME_OPCODE_SHIFT	28
-#define GM_MIF_FRAME_PHY_ADDR_MASK	0x0f800000
-#define GM_MIF_FRAME_PHY_ADDR_SHIFT	23
-#define GM_MIF_FRAME_REG_ADDR_MASK	0x007c0000
-#define GM_MIF_FRAME_REG_ADDR_SHIFT	18
-#define GM_MIF_FRAME_TURNAROUND_HI	0x00020000
-#define GM_MIF_FRAME_TURNAROUND_LO	0x00010000
-#define GM_MIF_FRAME_DATA_MASK		0x0000ffff
-#define GM_MIF_FRAME_DATA_SHIFT		0
-
-/* -- 0x6210	RW	MIF config reg
- */
-#define GM_MIF_CFG			(0x6210 | REG_SZ_16)
-#define	GM_MIF_CFGPS			0x00000001	/* PHY Select */
-#define	GM_MIF_CFGPE			0x00000002	/* Poll Enable */
-#define	GM_MIF_CFGBB			0x00000004	/* Bit Bang Enable */
-#define	GM_MIF_CFGPR_MASK		0x000000f8	/* Poll Register address */
-#define	GM_MIF_CFGPR_SHIFT		3
-#define	GM_MIF_CFGM0			0x00000100	/* MDIO_0 Data / MDIO_0 attached */
-#define	GM_MIF_CFGM1			0x00000200	/* MDIO_1 Data / MDIO_1 attached */
-#define	GM_MIF_CFGPD_MASK		0x00007c00	/* Poll Device PHY address */
-#define	GM_MIF_CFGPD_SHIFT		10
-
-#define	GM_MIF_POLL_DELAY		200
-
-#define	GM_INTERNAL_PHYAD		1		/* PHY address for int. transceiver */
-#define	GM_EXTERNAL_PHYAD		0		/* PHY address for ext. transceiver */
-
-/* -- 0x6214	RW	MIF interrupt mask reg
- *			same as basic/status Register
- */
-#define GM_MIF_IRQ_MASK			(0x6214 | REG_SZ_16)
-
-/* -- 0x6218	RW	MIF basic/status reg
- *			The Basic portion of this register indicates the last
- *			value of the register read indicated in the POLL REG field
- *			of the Configuration Register.
- *			The Status portion indicates bit(s) that have changed.
- *			The MIF Mask register is corresponding to this register in
- *			terms of the bit(s) that need to be masked for generating
- *			interrupt on the MIF Interrupt Bit of the Global Status Rgister.
- */
-#define GM_MIF_STATUS			(0x6218 | REG_SZ_32)
-
-#define	GM_MIF_STATUS_MASK		0x0000ffff	/* 0-15 : Status */
-#define	GM_MIF_BASIC_MASK		0xffff0000	/* 16-31 : Basic register */
-
-	/*
-	 * PCS link registers
-	 */
-
-/* -- 0x9000	RW	PCS mii control reg
- */
-#define GM_PCS_CONTROL			(0x9000 | REG_SZ_16)
-
-/* -- 0x9004	RW	PCS mii status reg
- */
-#define GM_PCS_STATUS			(0x9004 | REG_SZ_16)
-
-/* -- 0x9008	RW	PCS mii advertisement
- */
-#define GM_PCS_ADVERTISEMENT		(0x9008 | REG_SZ_16)
-
-/* -- 0x900c	RW	PCS mii LP ability
- */
-#define GM_PCS_ABILITY			(0x900c | REG_SZ_16)
-
-/* -- 0x9010	RW	PCS config
- */
-#define GM_PCS_CONFIG			(0x9010 | REG_SZ_8)
-
-/* -- 0x9014	RW	PCS state machine
- */
-#define GM_PCS_STATE_MACHINE		(0x9014 | REG_SZ_32)
-
-/* -- 0x9018	RW	PCS interrupt status
- */
-#define GM_PCS_IRQ_STATUS		(0x9018 | REG_SZ_8)
-
-/* -- 0x9050	RW	PCS datapath mode
- */
-#define GM_PCS_DATAPATH_MODE		(0x9050 | REG_SZ_8)
-#define GM_PCS_DATAPATH_INTERNAL	0x01	/* Internal serial link */
-#define GM_PCS_DATAPATH_SERDES		0x02	/* 10-bit Serdes interface */
-#define GM_PCS_DATAPATH_MII		0x04	/* Select mii/gmii mode */
-#define GM_PCS_DATAPATH_GMII_OUT	0x08	/* serial mode only, copy data to gmii */
-
-/* -- 0x9054	RW	PCS serdes control
- */
-#define GM_PCS_SERDES_CTRL		(0x9054 | REG_SZ_8)
-
-/* -- 0x9058	RW	PCS serdes output select
- */
-#define GM_PCS_SERDES_SELECT		(0x9058 | REG_SZ_8)
-
-/* -- 0x905c	RW	PCS serdes state
- */
-#define GM_PCS_SERDES_STATE		(0x905c | REG_SZ_8)
-
-
-	/*
-	 * PHY registers
-	 */
-
-/*
- * Standard PHY registers (from de4x5.h)
- */
-#define MII_CR       0x00          /* MII Management Control Register */
-#define MII_SR       0x01          /* MII Management Status Register */
-#define MII_ID0      0x02          /* PHY Identifier Register 0 */
-#define MII_ID1      0x03          /* PHY Identifier Register 1 */
-#define MII_ANA      0x04          /* Auto Negotiation Advertisement */
-#define MII_ANLPA    0x05          /* Auto Negotiation Link Partner Ability */
-#define MII_ANE      0x06          /* Auto Negotiation Expansion */
-#define MII_ANP      0x07          /* Auto Negotiation Next Page TX */
-
-/*
-** MII Management Control Register
-*/
-#define MII_CR_RST	 0x8000         /* RESET the PHY chip */
-#define MII_CR_LPBK	 0x4000         /* Loopback enable */
-#define MII_CR_SPD 	 0x2000         /* 0: 10Mb/s; 1: 100Mb/s */
-#define MII_CR_10  	 0x0000         /* Set 10Mb/s */
-#define MII_CR_100 	 0x2000         /* Set 100Mb/s */
-#define MII_CR_ASSE	 0x1000         /* Auto Speed Select Enable */
-#define MII_CR_PD  	 0x0800         /* Power Down */
-#define MII_CR_ISOL	 0x0400         /* Isolate Mode */
-#define MII_CR_RAN 	 0x0200         /* Restart Auto Negotiation */
-#define MII_CR_FDM 	 0x0100         /* Full Duplex Mode */
-#define MII_CR_CTE 	 0x0080         /* Collision Test Enable */
-#define MII_CR_SPEEDSEL2 0x0040		/* Speed selection 2 on BCM */
-/*
-** MII Management Status Register
-*/
-#define MII_SR_T4C  0x8000         /* 100BASE-T4 capable */
-#define MII_SR_TXFD 0x4000         /* 100BASE-TX Full Duplex capable */
-#define MII_SR_TXHD 0x2000         /* 100BASE-TX Half Duplex capable */
-#define MII_SR_TFD  0x1000         /* 10BASE-T Full Duplex capable */
-#define MII_SR_THD  0x0800         /* 10BASE-T Half Duplex capable */
-#define MII_SR_ASSC 0x0020         /* Auto Speed Selection Complete*/
-#define MII_SR_RFD  0x0010         /* Remote Fault Detected */
-#define MII_SR_ANC  0x0008         /* Auto Negotiation capable */
-#define MII_SR_LKS  0x0004         /* Link Status */
-#define MII_SR_JABD 0x0002         /* Jabber Detect */
-#define MII_SR_XC   0x0001         /* Extended Capabilities */
-
-/*
-** MII Management Auto Negotiation Advertisement Register
-*/
-#define MII_ANA_TAF  0x03e0        /* Technology Ability Field */
-#define MII_ANA_T4AM 0x0200        /* T4 Technology Ability Mask */
-#define MII_ANA_TXAM 0x0180        /* TX Technology Ability Mask */
-#define MII_ANA_FDAM 0x0140        /* Full Duplex Technology Ability Mask */
-#define MII_ANA_HDAM 0x02a0        /* Half Duplex Technology Ability Mask */
-#define MII_ANA_100M 0x0380        /* 100Mb Technology Ability Mask */
-#define MII_ANA_10M  0x0060        /* 10Mb Technology Ability Mask */
-#define MII_ANA_CSMA 0x0001        /* CSMA-CD Capable */
-
-/*
-** MII Management Auto Negotiation Remote End Register
-*/
-#define MII_ANLPA_NP   0x8000      /* Next Page (Enable) */
-#define MII_ANLPA_ACK  0x4000      /* Remote Acknowledge */
-#define MII_ANLPA_RF   0x2000      /* Remote Fault */
-#define MII_ANLPA_TAF  0x03e0      /* Technology Ability Field */
-#define MII_ANLPA_T4AM 0x0200      /* T4 Technology Ability Mask */
-#define MII_ANLPA_TXAM 0x0180      /* TX Technology Ability Mask */
-#define MII_ANLPA_FDAM 0x0140      /* Full Duplex Technology Ability Mask */
-#define MII_ANLPA_HDAM 0x02a0      /* Half Duplex Technology Ability Mask */
-#define MII_ANLPA_100M 0x0380      /* 100Mb Technology Ability Mask */
-#define MII_ANLPA_10M  0x0060      /* 10Mb Technology Ability Mask */
-#define MII_ANLPA_CSMA 0x0001      /* CSMA-CD Capable */
-#define MII_ANLPA_PAUS 0x0400 
-
-/* Generic PHYs
- * 
- * These GENERIC values assumes that the PHY devices follow 802.3u and
- * allow parallel detection to set the link partner ability register.
- * Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
- */
-
-/*
- * Model-specific PHY registers
- *
- * Note: Only the BCM5201 is described here for now. I'll add the 5400 once
- *       I see a machine using it in real world.
- */
-
-/* Supported PHYs (phy_type field ) */
-#define PHY_B5400	0x5400
-#define PHY_B5401	0x5401
-#define PHY_B5411	0x5411
-#define PHY_B5201	0x5201
-#define PHY_B5221	0x5221
-#define PHY_LXT971	0x0971
-#define PHY_UNKNOWN	0
-
-/* Identification (for multi-PHY) */
-#define MII_BCM5201_OUI                         0x001018
-#define MII_BCM5201_MODEL                       0x21
-#define MII_BCM5201_REV                         0x01
-#define MII_BCM5201_ID                          ((MII_BCM5201_OUI << 10) | (MII_BCM5201_MODEL << 4))
-#define MII_BCM5201_MASK                        0xfffffff0
-#define MII_BCM5221_OUI                         0x001018
-#define MII_BCM5221_MODEL                       0x1e
-#define MII_BCM5221_REV                         0x00
-#define MII_BCM5221_ID                          ((MII_BCM5221_OUI << 10) | (MII_BCM5221_MODEL << 4))
-#define MII_BCM5221_MASK                        0xfffffff0
-#define MII_BCM5400_OUI                         0x000818
-#define MII_BCM5400_MODEL                       0x04
-#define MII_BCM5400_REV                         0x01
-#define MII_BCM5400_ID                          ((MII_BCM5400_OUI << 10) | (MII_BCM5400_MODEL << 4))
-#define MII_BCM5400_MASK                        0xfffffff0
-#define MII_BCM5401_OUI                         0x000818
-#define MII_BCM5401_MODEL                       0x05
-#define MII_BCM5401_REV                         0x01
-#define MII_BCM5401_ID                          ((MII_BCM5401_OUI << 10) | (MII_BCM5401_MODEL << 4))
-#define MII_BCM5401_MASK                        0xfffffff0
-#define MII_BCM5411_OUI                         0x000818
-#define MII_BCM5411_MODEL                       0x07
-#define MII_BCM5411_REV                         0x01
-#define MII_BCM5411_ID                          ((MII_BCM5411_OUI << 10) | (MII_BCM5411_MODEL << 4))
-#define MII_BCM5411_MASK                        0xfffffff0
-#define MII_LXT971_OUI                          0x0004de
-#define MII_LXT971_MODEL                        0x0e
-#define MII_LXT971_REV                          0x00
-#define MII_LXT971_ID                           ((MII_LXT971_OUI << 10) | (MII_LXT971_MODEL << 4))
-#define MII_LXT971_MASK                         0xfffffff0
-
-/* BCM5201 AUX STATUS register */
-#define MII_BCM5201_AUXCTLSTATUS		0x18
-#define MII_BCM5201_AUXCTLSTATUS_DUPLEX		0x0001
-#define MII_BCM5201_AUXCTLSTATUS_SPEED		0x0002
-
-/* MII BCM5201 MULTIPHY interrupt register */
-#define MII_BCM5201_INTERRUPT			0x1A
-#define MII_BCM5201_INTERRUPT_INTENABLE		0x4000
-
-#define MII_BCM5201_AUXMODE2			0x1B
-#define MII_BCM5201_AUXMODE2_LOWPOWER		0x0008
-
-#define MII_BCM5201_MULTIPHY                    0x1E
-
-/* MII BCM5201 MULTIPHY register bits */
-#define MII_BCM5201_MULTIPHY_SERIALMODE         0x0002
-#define MII_BCM5201_MULTIPHY_SUPERISOLATE       0x0008
-
-/* MII BCM5400 1000-BASET Control register */
-#define MII_BCM5400_GB_CONTROL			0x09
-#define MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP	0x0200
-
-/* MII BCM5400 AUXCONTROL register */
-#define MII_BCM5400_AUXCONTROL                  0x18
-#define MII_BCM5400_AUXCONTROL_PWR10BASET       0x0004
-
-/* MII BCM5400 AUXSTATUS register */
-#define MII_BCM5400_AUXSTATUS                   0x19
-#define MII_BCM5400_AUXSTATUS_LINKMODE_MASK     0x0700
-#define MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT    8  
-
-/* MII LXT971 STATUS2 register */
-#define MII_LXT971_STATUS2			0x11
-#define MII_LXT971_STATUS2_SPEED		0x4000
-#define MII_LXT971_STATUS2_LINK			0x0400
-#define MII_LXT971_STATUS2_FULLDUPLEX		0x0200
-#define MII_LXT971_STATUS2_AUTONEG_COMPLETE	0x0080
-
-
-	/*
-	 * DMA descriptors
-	 */
-
-
-/* 
- * Descriptor counts and buffer sizes
- */
-#define NTX			64		/* must be power of 2 */
-#define NTX_CONF		GM_TX_RING_SZ_64
-#define NRX			64		/* must be power of 2 */
-#define NRX_CONF		GM_RX_RING_SZ_64
-#define RX_COPY_THRESHOLD	256
-#define GMAC_BUFFER_ALIGN	32		/* Align on a cache line */
-#define RX_BUF_ALLOC_SIZE	(ETH_FRAME_LEN + GMAC_BUFFER_ALIGN + 2)
-#define RX_OFFSET		2
-
-/*
- * Definitions of Rx and Tx descriptors
- */
-
-struct gmac_dma_desc {
-	unsigned int	size;		/* data size and OWN bit */
-	unsigned int	flags;		/* flags */
-	unsigned int	lo_addr;	/* phys addr, low 32 bits */
-	unsigned int	hi_addr;
-};
-
-/*
- * Rx bits
- */
- 
-/* Bits in size */
-#define RX_SZ_OWN		0x80000000	/* 1 = owned by chip */
-#define RX_SZ_MASK		0x7FFF0000
-#define RX_SZ_SHIFT		16
-#define RX_SZ_CKSUM_MASK	0x0000FFFF
-
-/* Bits in flags */
-#define RX_FL_CRC_ERROR		0x40000000
-#define RX_FL_ALT_ADDR		0x20000000	/* Packet rcv. from alt MAC address */
-
-/* 
- * Tx bits
- */
-
-/* Bits in size */
-#define TX_SZ_MASK		0x00007FFF
-#define TX_SZ_CRC_MASK		0x00FF8000
-#define TX_SZ_CRC_STUFF		0x1F000000
-#define TX_SZ_CRC_ENABLE	0x20000000
-#define TX_SZ_EOP		0x40000000
-#define TX_SZ_SOP		0x80000000
-/* Bits in flags */
-#define TX_FL_INTERRUPT		0x00000001
-#define TX_FL_NO_CRC		0x00000002
-
-	/*
-	 * Other stuffs
-	 */
-	 
-struct gmac {
-	volatile unsigned int		*regs;	/* hardware registers, virtual addr */
-	struct net_device		*dev;
-	struct device_node		*of_node;
-	unsigned long			tx_desc_page;	/* page for DMA descriptors */
-	unsigned long			rx_desc_page;	/* page for DMA descriptors */
-	volatile struct			gmac_dma_desc *rxring;
-	struct sk_buff			*rx_buff[NRX];
-	int				next_rx;
-	volatile struct	gmac_dma_desc	*txring;
-	struct sk_buff			*tx_buff[NTX];
-	int				next_tx;
-	int				tx_gone;
-	int				phy_addr;
-	unsigned int			phy_id;
-	int				phy_type;
-	int				phy_status;	/* Cached PHY status */
-	int				full_duplex;	/* Current set to full duplex */
-	int				gigabit;	/* Current set to 1000BT */
-	struct net_device_stats		stats;
-	u8				pci_bus;
-	u8				pci_devfn;
-	spinlock_t			lock;
-	int				opened;
-	int				sleeping;
-	struct net_device		*next_gmac;
-};
-
-
-/* Register access macros. We hope the preprocessor will be smart enough
- * to optimize them into one single access instruction
- */
-#define GM_OUT(reg, v)		(((reg) & REG_SZ_32) ? out_le32(gm->regs + \
-					(((reg) & REG_MASK)>>2), (v))  \
-				: (((reg) & REG_SZ_16) ? out_le16((volatile u16 *) \
-					(gm->regs + (((reg) & REG_MASK)>>2)), (v))  \
-				: out_8((volatile u8 *)(gm->regs + \
-					(((reg) & REG_MASK)>>2)), (v))))
-#define GM_IN(reg)		(((reg) & REG_SZ_32) ? in_le32(gm->regs + \
-					(((reg) & REG_MASK)>>2))  \
-				: (((reg) & REG_SZ_16) ? in_le16((volatile u16 *) \
-					(gm->regs + (((reg) & REG_MASK)>>2)))  \
-				: in_8((volatile u8 *)(gm->regs + \
-					(((reg) & REG_MASK)>>2)))))
-#define GM_BIS(r, v)		GM_OUT((r), GM_IN(r) | (v))
-#define GM_BIC(r, v)		GM_OUT((r), GM_IN(r) & ~(v))
-
-/* Wrapper to alloc_skb to test various alignements */
-#define GMAC_ALIGNED_RX_SKB_ADDR(addr) \
-        ((((unsigned long)(addr) + GMAC_BUFFER_ALIGN - 1) & \
-        ~(GMAC_BUFFER_ALIGN - 1)) - (unsigned long)(addr))
-        
-static inline struct sk_buff *
-gmac_alloc_skb(unsigned int length, int gfp_flags)
-{
-	struct sk_buff *skb;
-
-	skb = alloc_skb(length + GMAC_BUFFER_ALIGN, gfp_flags);
-	if(skb) {
-		int offset = GMAC_ALIGNED_RX_SKB_ADDR(skb->data);
-
-		if(offset)
-			skb_reserve(skb, offset);
-	}
-	return skb;
-}
-
diff --git a/drivers/net/mace.c b/drivers/net/mace.c
index 7704924740d2..c8861e982f4b 100644
--- a/drivers/net/mace.c
+++ b/drivers/net/mace.c
@@ -25,9 +25,6 @@
 static struct net_device *mace_devs;
 static int port_aaui = -1;
 
-MODULE_PARM(port_aaui, "i");
-MODULE_PARM_DESC(port_aaui, "MACE uses AAUI port (0-1)");
-
 #define N_RX_RING	8
 #define N_TX_RING	6
 #define MAX_TX_ACTIVE	1
@@ -35,6 +32,9 @@ MODULE_PARM_DESC(port_aaui, "MACE uses AAUI port (0-1)");
 #define RX_BUFLEN	(ETH_FRAME_LEN + 8)
 #define TX_TIMEOUT	HZ	/* 1 second */
 
+/* Chip rev needs workaround on HW & multicast addr change */
+#define BROKEN_ADDRCHG_REV	0x0941
+
 /* Bits in transmit DMA status */
 #define TX_DMA_ERR	0x80
 
@@ -60,6 +60,8 @@ struct mace_data {
     struct timer_list tx_timeout;
     int timeout_active;
     int port_aaui;
+    int chipid;
+    struct device_node* of_node;
     struct net_device *next_mace;
 };
 
@@ -153,6 +155,22 @@ static void __init mace_probe1(struct device_node *mace)
 	SET_MODULE_OWNER(dev);
 
 	mp = dev->priv;
+	mp->of_node = mace;
+	
+	if (!request_OF_resource(mace, 0, " (mace)")) {
+		printk(KERN_ERR "MACE: can't request IO resource !\n");
+		goto err_out;
+	}
+	if (!request_OF_resource(mace, 1, " (mace tx dma)")) {
+		printk(KERN_ERR "MACE: can't request TX DMA resource !\n");
+		goto err_out;
+	}
+
+	if (!request_OF_resource(mace, 2, " (mace tx dma)")) {
+		printk(KERN_ERR "MACE: can't request RX DMA resource !\n");
+		goto err_out;
+	}
+
 	dev->base_addr = mace->addrs[0].address;
 	mp->mace = (volatile struct mace *)
 		ioremap(mace->addrs[0].address, 0x1000);
@@ -164,8 +182,10 @@ static void __init mace_probe1(struct device_node *mace)
 		dev->dev_addr[j] = rev? bitrev(addr[j]): addr[j];
 		printk("%c%.2x", (j? ':': ' '), dev->dev_addr[j]);
 	}
-	printk(", chip revision %d.%d\n",
-		in_8(&mp->mace->chipid_hi), in_8(&mp->mace->chipid_lo));
+	mp->chipid = (in_8(&mp->mace->chipid_hi) << 8) |
+			in_8(&mp->mace->chipid_lo);
+	printk(", chip revision %d.%d\n", mp->chipid >> 8, mp->chipid & 0xff);
+		
 
 	mp = (struct mace_data *) dev->priv;
 	mp->maccc = ENXMT | ENRCV;
@@ -222,6 +242,16 @@ static void __init mace_probe1(struct device_node *mace)
 
 	mp->next_mace = mace_devs;
 	mace_devs = dev;
+	return;
+	
+err_out:
+	unregister_netdev(dev);
+	if (mp->of_node) {
+		release_OF_resource(mp->of_node, 0);
+		release_OF_resource(mp->of_node, 1);
+		release_OF_resource(mp->of_node, 2);
+	}
+	kfree(dev);
 }
 
 static void dbdma_reset(volatile struct dbdma_regs *dma)
@@ -274,14 +304,19 @@ static void mace_reset(struct net_device *dev)
     __mace_set_address(dev, dev->dev_addr);
 
     /* clear the multicast filter */
-    out_8(&mb->iac, ADDRCHG | LOGADDR);
-    while ((in_8(&mb->iac) & ADDRCHG) != 0)
-	;
-    for (i = 0; i < 8; ++i) {
-	out_8(&mb->ladrf, 0);
+    if (mp->chipid == BROKEN_ADDRCHG_REV)
+	out_8(&mb->iac, LOGADDR);
+    else {
+	out_8(&mb->iac, ADDRCHG | LOGADDR);
+	while ((in_8(&mb->iac) & ADDRCHG) != 0)
+		;
     }
+    for (i = 0; i < 8; ++i)
+	out_8(&mb->ladrf, 0);
+
     /* done changing address */
-    out_8(&mb->iac, 0);
+    if (mp->chipid != BROKEN_ADDRCHG_REV)
+	out_8(&mb->iac, 0);
 
     if (mp->port_aaui)
     	out_8(&mb->plscc, PORTSEL_AUI + ENPLSIO);
@@ -291,16 +326,23 @@ static void mace_reset(struct net_device *dev)
 
 static void __mace_set_address(struct net_device *dev, void *addr)
 {
-    volatile struct mace *mb = ((struct mace_data *) dev->priv)->mace;
+    struct mace_data *mp = (struct mace_data *) dev->priv;
+    volatile struct mace *mb = mp->mace;
     unsigned char *p = addr;
     int i;
 
     /* load up the hardware address */
-    out_8(&mb->iac, ADDRCHG | PHYADDR);
-    while ((in_8(&mb->iac) & ADDRCHG) != 0)
-	;
+    if (mp->chipid == BROKEN_ADDRCHG_REV)
+    	out_8(&mb->iac, PHYADDR);
+    else {
+    	out_8(&mb->iac, ADDRCHG | PHYADDR);
+	while ((in_8(&mb->iac) & ADDRCHG) != 0)
+	    ;
+    }
     for (i = 0; i < 6; ++i)
 	out_8(&mb->padr, dev->dev_addr[i] = p[i]);
+    if (mp->chipid != BROKEN_ADDRCHG_REV)
+        out_8(&mb->iac, 0);
 }
 
 static int mace_set_address(struct net_device *dev, void *addr)
@@ -313,7 +355,6 @@ static int mace_set_address(struct net_device *dev, void *addr)
 
     __mace_set_address(dev, addr);
 
-    out_8(&mb->iac, 0);
     /* note: setting ADDRCHG clears ENRCV */
     out_8(&mb->maccc, mp->maccc);
 
@@ -543,12 +584,17 @@ static void mace_set_multicast(struct net_device *dev)
 	printk("\n");
 #endif
 
-	out_8(&mb->iac, ADDRCHG | LOGADDR);
-	while ((in_8(&mb->iac) & ADDRCHG) != 0)
-	    ;
-	for (i = 0; i < 8; ++i) {
-	    out_8(&mb->ladrf, multicast_filter[i]);
+	if (mp->chipid == BROKEN_ADDRCHG_REV)
+	    out_8(&mb->iac, LOGADDR);
+	else {
+	    out_8(&mb->iac, ADDRCHG | LOGADDR);
+	    while ((in_8(&mb->iac) & ADDRCHG) != 0)
+		;
 	}
+	for (i = 0; i < 8; ++i)
+	    out_8(&mb->ladrf, multicast_filter[i]);
+	if (mp->chipid != BROKEN_ADDRCHG_REV)
+	    out_8(&mb->iac, 0);
     }
     /* reset maccc */
     out_8(&mb->maccc, mp->maccc);
@@ -899,7 +945,10 @@ static void mace_rxdma_intr(int irq, void *dev_id, struct pt_regs *regs)
 
 MODULE_AUTHOR("Paul Mackerras");
 MODULE_DESCRIPTION("PowerMac MACE driver.");
+MODULE_PARM(port_aaui, "i");
+MODULE_PARM_DESC(port_aaui, "MACE uses AAUI port (0-1)");
 MODULE_LICENSE("GPL");
+EXPORT_NO_SYMBOLS;
 
 static void __exit mace_cleanup (void)
 {
@@ -907,19 +956,23 @@ static void __exit mace_cleanup (void)
     struct mace_data *mp;
 
     while ((dev = mace_devs) != 0) {
-	mp = (struct mace_data *) mace_devs->priv;
-	mace_devs = mp->next_mace;
+		mp = (struct mace_data *) mace_devs->priv;
+		mace_devs = mp->next_mace;
 
-	free_irq(dev->irq, dev);
-	free_irq(mp->tx_dma_intr, dev);
-	free_irq(mp->rx_dma_intr, dev);
+		unregister_netdev(dev);
+		free_irq(dev->irq, dev);
+		free_irq(mp->tx_dma_intr, dev);
+		free_irq(mp->rx_dma_intr, dev);
 
-	unregister_netdev(dev);
-	kfree(dev);
+		release_OF_resource(mp->of_node, 0);
+		release_OF_resource(mp->of_node, 1);
+		release_OF_resource(mp->of_node, 2);
+
+		kfree(dev);
     }
     if (dummy_buf != NULL) {
-	kfree(dummy_buf);
-	dummy_buf = NULL;
+		kfree(dummy_buf);
+		dummy_buf = NULL;
     }
 }