diff options
| author | Russell King <rmk@flint.arm.linux.org.uk> | 2004-09-07 16:24:51 +0100 |
|---|---|---|
| committer | Russell King <rmk@flint.arm.linux.org.uk> | 2004-09-07 16:24:51 +0100 |
| commit | 8db06ceea34d15300e6163fa36ed3c71748175ee (patch) | |
| tree | 7c9b9a242620bfdc6b0c917227b9edc1238d7efc | |
| parent | f1f7ea351d9b2f53ee5d0a65d6284730e4c95677 (diff) | |
[ARM] Add cache_is_xxxx() functions for cache type identification.
Add cache_is_xxxx() functions so we can easily identify the cache
type of the CPU we're running on.
| -rw-r--r-- | include/asm-arm/system.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h index d500cc940f81..146a814e53a2 100644 --- a/include/asm-arm/system.h +++ b/include/asm-arm/system.h @@ -55,6 +55,38 @@ __val; \ }) +#define __cacheid_present(val) (val != read_cpuid(CPUID_ID)) +#define __cacheid_vivt(val) ((val & (15 << 25)) != (14 << 25)) +#define __cacheid_vipt(val) ((val & (15 << 25)) == (14 << 25)) +#define __cacheid_vipt_nonaliasing(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25)) +#define __cacheid_vipt_aliasing(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23)) + +#define cache_is_vivt() \ + ({ \ + unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ + (!__cacheid_present(__val)) || __cacheid_vivt(__val); \ + }) + +#define cache_is_vipt() \ + ({ \ + unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ + __cacheid_present(__val) && __cacheid_vipt(__val); \ + }) + +#define cache_is_vipt_nonaliasing() \ + ({ \ + unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ + __cacheid_present(__val) && \ + __cacheid_vipt_nonaliasing(__val); \ + }) + +#define cache_is_vipt_aliasing() \ + ({ \ + unsigned int __val = read_cpuid(CPUID_CACHETYPE); \ + __cacheid_present(__val) && \ + __cacheid_vipt_aliasing(__val); \ + }) + /* * This is used to ensure the compiler did actually allocate the register we * asked it for some inline assembly sequences. Apparently we can't trust |