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authorAnton Blanchard <anton@samba.org>2004-06-26 20:52:30 -0700
committerLinus Torvalds <torvalds@ppc970.osdl.org>2004-06-26 20:52:30 -0700
commit8dce5d70a4ecfb445b33569d93e99336c426e14a (patch)
treee11a25fc1ab4860cc1822a2d57fb10b5dae83a27
parentedc5e57d7644f29c4f2d9d98ef20d250f2f27ffb (diff)
[PATCH] ppc64: fix oprofile on 970
- Use 970/970FX instead of GPUL - Add POWER5 and 970FX to systemcfg.h - Create new cpu feature CPU_FTR_MMCRA_SIHV and use it Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
-rw-r--r--arch/ppc64/kernel/cputable.c6
-rw-r--r--arch/ppc64/oprofile/common.c4
-rw-r--r--arch/ppc64/oprofile/op_model_power4.c2
-rw-r--r--include/asm-ppc64/cputable.h1
-rw-r--r--include/asm-ppc64/processor.h4
-rw-r--r--include/asm-ppc64/systemcfg.h2
6 files changed, 12 insertions, 7 deletions
diff --git a/arch/ppc64/kernel/cputable.c b/arch/ppc64/kernel/cputable.c
index df13c89ff25c..44fa14e4f511 100644
--- a/arch/ppc64/kernel/cputable.c
+++ b/arch/ppc64/kernel/cputable.c
@@ -141,7 +141,8 @@ struct cpu_spec cpu_specs[] = {
0xffff0000, 0x003a0000, "POWER5 (gr)",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
- CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE,
+ CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
+ CPU_FTR_MMCRA_SIHV,
COMMON_USER_PPC64,
128, 128,
__setup_cpu_power4,
@@ -151,7 +152,8 @@ struct cpu_spec cpu_specs[] = {
0xffff0000, 0x003b0000, "POWER5 (gs)",
CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
- CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE,
+ CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
+ CPU_FTR_MMCRA_SIHV,
COMMON_USER_PPC64,
128, 128,
__setup_cpu_power4,
diff --git a/arch/ppc64/oprofile/common.c b/arch/ppc64/oprofile/common.c
index 2d5ce46cbb2e..391e9afbad64 100644
--- a/arch/ppc64/oprofile/common.c
+++ b/arch/ppc64/oprofile/common.c
@@ -154,8 +154,8 @@ int __init oprofile_arch_init(struct oprofile_operations **ops)
oprof_ppc64_ops.cpu_type = "ppc64/power4";
break;
- case PV_GPUL:
- case PV_GPULp:
+ case PV_970:
+ case PV_970FX:
model = &op_model_power4;
model->num_counters = 8;
oprof_ppc64_ops.cpu_type = "ppc64/970";
diff --git a/arch/ppc64/oprofile/op_model_power4.c b/arch/ppc64/oprofile/op_model_power4.c
index 6b132a8c670b..8a0e7a86727e 100644
--- a/arch/ppc64/oprofile/op_model_power4.c
+++ b/arch/ppc64/oprofile/op_model_power4.c
@@ -42,7 +42,7 @@ static void power4_reg_setup(struct op_counter_config *ctr,
*
* It has been verified to work on POWER5 so we enable it there.
*/
- if (!(__is_processor(PV_POWER4) || __is_processor(PV_POWER4p)))
+ if (cur_cpu_spec->cpu_features & CPU_FTR_MMCRA_SIHV)
mmcra_has_sihv = 1;
for (i = 0; i < num_counters; ++i)
diff --git a/include/asm-ppc64/cputable.h b/include/asm-ppc64/cputable.h
index abca635f9f9b..fa9b231ef3a3 100644
--- a/include/asm-ppc64/cputable.h
+++ b/include/asm-ppc64/cputable.h
@@ -131,6 +131,7 @@ extern firmware_feature_t firmware_features_table[];
#define CPU_FTR_SMT 0x0000010000000000
#define CPU_FTR_COHERENT_ICACHE 0x0000020000000000
#define CPU_FTR_LOCKLESS_TLBIE 0x0000040000000000
+#define CPU_FTR_MMCRA_SIHV 0x0000080000000000
/* Platform firmware features */
#define FW_FTR_ 0x0000000000000001
diff --git a/include/asm-ppc64/processor.h b/include/asm-ppc64/processor.h
index 265ad15da289..341c9513a67c 100644
--- a/include/asm-ppc64/processor.h
+++ b/include/asm-ppc64/processor.h
@@ -382,10 +382,10 @@
#define PV_ICESTAR 0x0036
#define PV_SSTAR 0x0037
#define PV_POWER4p 0x0038
-#define PV_GPUL 0x0039
+#define PV_970 0x0039
#define PV_POWER5 0x003A
#define PV_POWER5p 0x003B
-#define PV_GPULp 0x003C
+#define PV_970FX 0x003C
#define PV_630 0x0040
#define PV_630p 0x0041
diff --git a/include/asm-ppc64/systemcfg.h b/include/asm-ppc64/systemcfg.h
index 72b5adba9325..7cefeef2baa2 100644
--- a/include/asm-ppc64/systemcfg.h
+++ b/include/asm-ppc64/systemcfg.h
@@ -73,6 +73,8 @@ extern struct systemcfg *systemcfg;
#define PV_SSTAR 0x0037
#define PV_POWER4p 0x0038
#define PV_GPUL 0x0039
+#define PV_POWER5 0x003a
+#define PV_970FX 0x003c
#define PV_630 0x0040
#define PV_630p 0x0041