diff options
| author | Anton Altaparmakov <aia21@cantab.net> | 2004-05-10 11:29:45 +0100 |
|---|---|---|
| committer | Anton Altaparmakov <aia21@cantab.net> | 2004-05-10 11:29:45 +0100 |
| commit | b404fc906a8b79f5d9902941bbfc98348e7646c5 (patch) | |
| tree | 84b8dda4fa271de15e43d6920ecfba1c064be0de | |
| parent | e2b48faa03e8f35f7ae3c0063ce3c1179e2a50b8 (diff) | |
| parent | 3dc567d850dc6f0858472621ddba3e31fcacdbe5 (diff) | |
Merge cantab.net:/home/src/bklinux-2.6
into cantab.net:/home/src/ntfs-2.6
91 files changed, 6262 insertions, 702 deletions
diff --git a/Documentation/arm/Sharp-LH/CompactFlash b/Documentation/arm/Sharp-LH/CompactFlash new file mode 100644 index 000000000000..8616d877df9e --- /dev/null +++ b/Documentation/arm/Sharp-LH/CompactFlash @@ -0,0 +1,32 @@ +README on the Compact Flash for Card Engines +============================================ + +There are three challenges in supporting the CF interface of the Card +Engines. First, every IO operation must be followed with IO to +another memory region. Second, the slot is wired for one-to-one +address mapping *and* it is wired for 16 bit access only. Second, the +interrupt request line from the CF device isn't wired. + +The IOBARRIER issue is covered in README.IOBARRIER. This isn't an +onerous problem. Enough said here. + +The addressing issue is solved in the +arch/arm/mach-lh7a40x/ide-lpd7a40x.c file with some awkward +work-arounds. We implement a special SELECT_DRIVE routine that is +called before the IDE driver performs its own SELECT_DRIVE. Our code +recognizes that the SELECT register cannot be modified without also +writing a command. It send an IDLE_IMMEDIATE command on selecting a +drive. The function also prevents drive select to the slave drive +since there can be only one. The awkward part is that the IDE driver, +even though we have a select procedure, also attempts to change the +drive by writing directly the SELECT register. This attempt is +explicitly blocked by the OUTB function--not pretty, but effective. + +The lack of interrupts is a more serious problem. Even though the CF +card is fast when compared to a normal IDE device, we don't know that +the CF is really flash. A user could use one of the very small hard +drives being shipped with a CF interface. The IDE code includes a +check for interfaces that lack an IRQ. In these cases, submitting a +command to the IDE controller is followed by a call to poll for +completion. If the device isn't immediately ready, it schedules a +timer to poll again later. diff --git a/Documentation/arm/Sharp-LH/IOBarrier b/Documentation/arm/Sharp-LH/IOBarrier new file mode 100644 index 000000000000..bf34e046ea10 --- /dev/null +++ b/Documentation/arm/Sharp-LH/IOBarrier @@ -0,0 +1,32 @@ +README on the IOBARRIER for CardEngine IO +========================================= + +Due to an unfortunate oversight when the Card Engines were designed, +the signals that control access to some peripherals, most notably the +SMC91C9111 ethernet controller, are not properly handled. + +The symptom is that back to back IO with the peripheral returns +unreliable data. With the SMC chip, you'll see errors about the bank +register being 'screwed'. + +The cause is that the AEN signal to the SMC chip does not transition +for every memory access. It is driven through the CPLD from the CS7 +line of the CPU's static memory controller which is optimized to +eliminate unnecessary transitions. Yet, the SMC requires a transition +for every access. The Sharp website has more information on the +effect of this power conservation feature on peripheral interfacing. + +The solution is to follow every access to the SMC chip with an access +to another memory region that will force the CPU to release the chip +select line. Note that it is important to guarantee that the access +will force the CPU off-chip. We map a page of SDRAM as if it were an +uncacheable IO device and read from it after every SMC IO operation. + + SMC IO + BARRIER IO + +You might be tempted to believe that we must access another device +attached to the static memory controller, but the empirical evidence +indicates that this is not so. Mapping 0x00000000 (flash) and +0xc0000000 (SDRAM) appear to have the same effect. Using SDRAM seems +to be faster. diff --git a/Documentation/arm/Sharp-LH/KEV7A400 b/Documentation/arm/Sharp-LH/KEV7A400 new file mode 100644 index 000000000000..be32b14cd535 --- /dev/null +++ b/Documentation/arm/Sharp-LH/KEV7A400 @@ -0,0 +1,8 @@ +README on Implementing Linux for Sharp's KEV7a400 +================================================= + +This product has been discontinued by Sharp. For the time being, the +partially implemented code remains in the kernel. At some point in +the future, either the code will be finished or it will be removed +completely. This depends primarily on how many of the development +boards are in the field. diff --git a/Documentation/arm/Sharp-LH/LPD7A400 b/Documentation/arm/Sharp-LH/LPD7A400 new file mode 100644 index 000000000000..3275b453bfdf --- /dev/null +++ b/Documentation/arm/Sharp-LH/LPD7A400 @@ -0,0 +1,15 @@ +README on Implementing Linux for the Logic PD LPD7A400-10 +========================================================= + +- CPLD memory mapping + + The board designers chose to use high address lines for controlling + access to the CPLD registers. It turns out to be a big waste + because we're using an MMU and must map IO space into virtual + memory. The result is that we have to make a mapping for every + register. + +- Serial Console + + It may be OK not to use the serial console option if the user passes + the console device name to the kernel. This deserves some exploration. diff --git a/Documentation/arm/Sharp-LH/LPD7A40X b/Documentation/arm/Sharp-LH/LPD7A40X new file mode 100644 index 000000000000..8c29a27e208f --- /dev/null +++ b/Documentation/arm/Sharp-LH/LPD7A40X @@ -0,0 +1,16 @@ +README on Implementing Linux for the Logic PD LPD7A40X-10 +========================================================= + +- CPLD memory mapping + + The board designers chose to use high address lines for controlling + access to the CPLD registers. It turns out to be a big waste + because we're using an MMU and must map IO space into virtual + memory. The result is that we have to make a mapping for every + register. + +- Serial Console + + It may be OK not to use the serial console option if the user passes + the console device name to the kernel. This deserves some exploration. + diff --git a/Documentation/arm/Sharp-LH/VectoredInterruptController b/Documentation/arm/Sharp-LH/VectoredInterruptController new file mode 100644 index 000000000000..23047e9861ee --- /dev/null +++ b/Documentation/arm/Sharp-LH/VectoredInterruptController @@ -0,0 +1,80 @@ +README on the Vectored Interrupt Controller of the LH7A404 +========================================================== + +The 404 revision of the LH7A40X series comes with two vectored +interrupts controllers. While the kernel does use some of the +features of these devices, it is far from the purpose for which they +were designed. + +When this README was written, the implementation of the VICs was in +flux. It is possible that some details, especially with priorities, +will change. + +The VIC support code is inspired by routines written by Sharp. + + +Priority Control +---------------- + +The significant reason for using the VIC's vectoring is to control +interrupt priorities. There are two tables in +arch/arm/mach-lh7a40x/irq-lh7a404.c that look something like this. + + static unsigned char irq_pri_vic1[] = { IRQ_GPIO3INTR, }; + static unsigned char irq_pri_vic2[] = { + IRQ_T3UI, IRQ_GPIO7INTR, + IRQ_UART1INTR, IRQ_UART2INTR, IRQ_UART3INTR, }; + +The initialization code reads these tables and inserts a vector +address and enable for each indicated IRQ. Vectored interrupts have +higher priority than non-vectored interrupts. So, on VIC1, +IRQ_GPIO3INTR will be served before any other non-FIQ interrupt. Due +to the way that the vectoring works, IRQ_T3UI is the next highest +priority followed by the other vectored interrupts on VIC2. After +that, the non-vectored interrupts are scanned in VIC1 then in VIC2. + + +ISR +--- + +The interrupt service routine macro get_irqnr() in +arch/arm/kernel/entry-armv.S scans the VICs for the next active +interrupt. The vectoring makes this code somewhat larger than it was +before using vectoring (refer to the LH7A400 implementation). In the +case where an interrupt is vectored, the implementation will tend to +be faster than the non-vectored version. However, the worst-case path +is longer. + +It is worth noting that at present, there is no need to read +VIC2_VECTADDR because the register appears to be shared between the +controllers. The code is written such that if this changes, it ought +to still work properly. + + +Vector Addresses +---------------- + +The proper use of the vectoring hardware would jump to the ISR +specified by the vectoring address. Linux isn't structured to take +advantage of this feature, though it might be possible to change +things to support it. + +In this implementation, the vectoring address is used to speed the +search for the active IRQ. The address is coded such that the lowest +6 bits store the IRQ number for vectored interrupts. These numbers +correspond to the bits in the interrupt status registers. IRQ zero is +the lowest interrupt bit in VIC1. IRQ 32 is the lowest interrupt bit +in VIC2. Because zero is a valid IRQ number and because we cannot +detect whether or not there is a valid vectoring address if that +address is zero, the eigth bit (0x100) is set for vectored interrupts. +The address for IRQ 0x18 (VIC2) is 0x118. Only the ninth bit is set +for the default handler on VIC1 and only the tenth bit is set for the +default handler on VIC2. + +In other words. + + 0x000 - no active interrupt + 0x1ii - vectored interrupt 0xii + 0x2xx - unvectored interrupt on VIC1 (xx is don't care) + 0x4xx - unvectored interrupt on VIC2 (xx is don't care) + @@ -1,7 +1,7 @@ VERSION = 2 PATCHLEVEL = 6 SUBLEVEL = 6 -EXTRAVERSION =-rc3 +EXTRAVERSION = NAME=Zonked Quokka # *DOCUMENTATION* diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d7788028514b..588fd8b7c359 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -145,6 +145,14 @@ config ARCH_S3C2410 config ARCH_OMAP bool "TI OMAP" +config ARCH_LH7A40X + bool "Sharp LH7A40X" + help + Say Y here for systems based on one of the Sharp LH7A40X + System on a Chip processors. These CPUs include an ARM922T + core with a wide array of integrated devices for + hand-held and low-power applications. + config ARCH_VERSATILE_PB bool "Versatile PB" help @@ -170,6 +178,8 @@ source "arch/arm/mach-omap/Kconfig" source "arch/arm/mach-s3c2410/Kconfig" +source "arch/arm/mach-lh7a40x/Kconfig" + # Definitions to make life easier config ARCH_ACORN bool @@ -231,7 +241,7 @@ menu "General setup" # Select various configuration options depending on the machine type config DISCONTIGMEM bool - depends on ARCH_EDB7211 || ARCH_SA1100 + depends on ARCH_EDB7211 || ARCH_SA1100 || ARCH_LH7A40X default y help Say Y to upport efficient handling of discontiguous physical memory, @@ -293,7 +303,7 @@ config ISA_DMA config FIQ bool - depends on ARCH_ACORN || ARCH_L7200 + depends on ARCH_ACORN || ARCH_L7200 || ARCH_LH7A400 default y # Compressed boot loader in ROM. Yes, we really want to ask about diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 0dea4d3f5b4a..fb88490c57c6 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -94,6 +94,7 @@ textaddr-$(CONFIG_ARCH_FORTUNET) := 0xc0008000 machine-$(CONFIG_ARCH_ADIFCC) := adifcc machine-$(CONFIG_ARCH_OMAP) := omap machine-$(CONFIG_ARCH_S3C2410) := s3c2410 + machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x machine-$(CONFIG_ARCH_VERSATILE_PB) := versatile TEXTADDR := $(textaddr-y) diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile index 65ba5bf38ae6..602b8a68e9c0 100644 --- a/arch/arm/boot/Makefile +++ b/arch/arm/boot/Makefile @@ -54,6 +54,9 @@ params_phys-$(CONFIG_ARCH_ADIFCC) := 0xc0000100 zreladdr-$(CONFIG_ARCH_OMAP) := 0x10008000 params_phys-$(CONFIG_ARCH_OMAP) := 0x10000100 initrd_phys-$(CONFIG_ARCH_OMAP) := 0x10800000 + zreladdr-$(CONFIG_ARCH_LH7A40X) := 0xc0008000 +params_phys-$(CONFIG_ARCH_LH7A40X) := 0xc0000100 +initrd_phys-$(CONFIG_ARCH_LH7A40X) := 0xc4000000 zreladdr-$(CONFIG_ARCH_S3C2410) := 0x30008000 params_phys-$(CONFIG_ARCH_S3C2410) := 0x30000100 zreladdr-$(CONFIG_ARCH_VERSATILE_PB) := 0x00008000 diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 8e2a536aa846..d54b4f6116c3 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -73,6 +73,13 @@ .macro writeb, rb str \rb, [r3, #0x14] @ UTDR .endm +#elif defined(CONFIG_ARCH_LH7A40X) + .macro loadsp, rb + ldr \rb, =0x80000700 @ UART2 UARTBASE + .endm + .macro writeb, rb + strb \rb, [r3, #0] + .endm #else #error no serial architecture defined #endif diff --git a/arch/arm/configs/lpd7a400_defconfig b/arch/arm/configs/lpd7a400_defconfig new file mode 100644 index 000000000000..2fd8da9f14b8 --- /dev/null +++ b/arch/arm/configs/lpd7a400_defconfig @@ -0,0 +1,710 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_ARM=y +CONFIG_MMU=y +CONFIG_UID16=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_CLEAN_COMPILE=y +CONFIG_STANDALONE=y +CONFIG_BROKEN_ON_SMP=y + +# +# General setup +# +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_HOTPLUG is not set +CONFIG_IKCONFIG=y +# CONFIG_IKCONFIG_PROC is not set +CONFIG_EMBEDDED=y +CONFIG_KALLSYMS=y +CONFIG_FUTEX=y +# CONFIG_EPOLL is not set +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y + +# +# Loadable module support +# +# CONFIG_MODULES is not set + +# +# System Type +# +# CONFIG_ARCH_ADIFCC is not set +# CONFIG_ARCH_ANAKIN is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_CAMELOT is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_IOP3XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_SHARK is not set +CONFIG_ARCH_LH7A40X=y + +# +# CLPS711X/EP721X Implementations +# + +# +# Epxa10db +# + +# +# Footbridge Implementations +# + +# +# IOP3xx Implementation Options +# +# CONFIG_ARCH_IOP310 is not set +# CONFIG_ARCH_IOP321 is not set + +# +# IOP3xx Chipset Features +# + +# +# Intel PXA250/210 Implementations +# + +# +# SA11x0 Implementations +# + +# +# LH7A40X Implementations +# +# CONFIG_MACH_KEV7A400 is not set +CONFIG_MACH_LPD7A400=y +# CONFIG_MACH_LPD7A404 is not set +CONFIG_ARCH_LH7A400=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM922T=y +CONFIG_CPU_32v4=y +CONFIG_CPU_ABRT_EV4T=y +CONFIG_CPU_CACHE_V4WT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set + +# +# General setup +# +CONFIG_DISCONTIGMEM=y +CONFIG_FIQ=y +# CONFIG_ZBOOT_ROM is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 + +# +# At least one math emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Generic Driver Options +# +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_PM is not set +CONFIG_PREEMPT=y +# CONFIG_ARTHUR is not set +CONFIG_CMDLINE="" +CONFIG_ALIGNMENT_TRAP=y + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_CONCAT is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +CONFIG_MTD_LPD7A40X=y +# CONFIG_MTD_EDB7312 is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set + +# +# Plug and Play support +# + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +# CONFIG_NETLINK_DEV is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_IPV6 is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_NETFILTER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +CONFIG_IPV6_SCTP__=y +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +CONFIG_SMC91X=y + +# +# Ethernet (1000 Mbit) +# + +# +# Ethernet (10000 Mbit) +# +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices +# +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# Bluetooth support +# +# CONFIG_BT is not set + +# +# ATA/ATAPI/MFM/RLL support +# +CONFIG_IDE=y +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +CONFIG_BLK_DEV_IDEDISK=y +# CONFIG_IDEDISK_MULTI_MODE is not set +# CONFIG_IDEDISK_STROKE is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_IDE_TASK_IOCTL is not set +# CONFIG_IDE_TASKFILE_IO is not set +CONFIG_IDE_POLL=y + +# +# IDE chipset support/bugfixes +# +CONFIG_IDE_GENERIC=y +# CONFIG_BLK_DEV_IDEDMA is not set +# CONFIG_IDEDMA_AUTO is not set +# CONFIG_DMA_NONPCI is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI device support +# +# CONFIG_SCSI is not set + +# +# Fusion MPT device support +# + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +# CONFIG_SERIO is not set +# CONFIG_SERIO_I8042 is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_SERIAL_LH7A40X=y +CONFIG_SERIAL_LH7A40X_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_NVRAM is not set +CONFIG_RTC=y +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +# CONFIG_DEVPTS_FS_XATTR is not set +CONFIG_TMPFS=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_NAND is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +# CONFIG_EXPORTFS is not set +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_GSS is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_NEC98_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_EFI_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Graphics support +# +# CONFIG_FB is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +# CONFIG_MDA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Misc devices +# + +# +# USB support +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set + +# +# Kernel hacking +# +CONFIG_FRAME_POINTER=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SLAB is not set +CONFIG_MAGIC_SYSRQ=y +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_WAITQ is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_LL is not set + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_CRC32=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y diff --git a/arch/arm/configs/lpd7a404_defconfig b/arch/arm/configs/lpd7a404_defconfig new file mode 100644 index 000000000000..a13b52210599 --- /dev/null +++ b/arch/arm/configs/lpd7a404_defconfig @@ -0,0 +1,849 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_ARM=y +CONFIG_MMU=y +CONFIG_UID16=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_CLEAN_COMPILE=y +CONFIG_STANDALONE=y +CONFIG_BROKEN_ON_SMP=y + +# +# General setup +# +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_HOTPLUG is not set +CONFIG_IKCONFIG=y +# CONFIG_IKCONFIG_PROC is not set +CONFIG_EMBEDDED=y +CONFIG_KALLSYMS=y +CONFIG_FUTEX=y +# CONFIG_EPOLL is not set +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y + +# +# Loadable module support +# +# CONFIG_MODULES is not set + +# +# System Type +# +# CONFIG_ARCH_ADIFCC is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_CAMELOT is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_IOP3XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_OMAP is not set +CONFIG_ARCH_LH7A40X=y + +# +# CLPS711X/EP721X Implementations +# + +# +# Epxa10db +# + +# +# Footbridge Implementations +# + +# +# IOP3xx Implementation Options +# +# CONFIG_ARCH_IOP310 is not set +# CONFIG_ARCH_IOP321 is not set + +# +# IOP3xx Chipset Features +# + +# +# Intel PXA250/210 Implementations +# + +# +# SA11x0 Implementations +# + +# +# TI OMAP Implementations +# + +# +# OMAP Feature Selections +# + +# +# S3C2410 Implementations +# + +# +# LH7A40X Implementations +# +# CONFIG_MACH_KEV7A400 is not set +# CONFIG_MACH_LPD7A400 is not set +CONFIG_MACH_LPD7A404=y +CONFIG_ARCH_LH7A404=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM922T=y +CONFIG_CPU_32v4=y +CONFIG_CPU_ABRT_EV4T=y +CONFIG_CPU_CACHE_V4WT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set + +# +# General setup +# +CONFIG_DISCONTIGMEM=y +# CONFIG_ZBOOT_ROM is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 + +# +# At least one math emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Generic Driver Options +# +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_PM is not set +CONFIG_PREEMPT=y +# CONFIG_ARTHUR is not set +CONFIG_CMDLINE="" +CONFIG_ALIGNMENT_TRAP=y + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_CONCAT is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +CONFIG_MTD_LPD7A40X=y +# CONFIG_MTD_EDB7312 is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set + +# +# Plug and Play support +# + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Networking support +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +# CONFIG_NETLINK_DEV is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_IPV6 is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_NETFILTER is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +CONFIG_SMC91X=y + +# +# Ethernet (1000 Mbit) +# + +# +# Ethernet (10000 Mbit) +# +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices +# +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# Bluetooth support +# +# CONFIG_BT is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ATA/ATAPI/MFM/RLL support +# +CONFIG_IDE=y +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +CONFIG_BLK_DEV_IDEDISK=y +# CONFIG_IDEDISK_MULTI_MODE is not set +# CONFIG_IDEDISK_STROKE is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_BLK_DEV_IDESCSI is not set +# CONFIG_IDE_TASK_IOCTL is not set +# CONFIG_IDE_TASKFILE_IO is not set +CONFIG_IDE_POLL=y + +# +# IDE chipset support/bugfixes +# +CONFIG_IDE_GENERIC=y +# CONFIG_BLK_DEV_IDEDMA is not set +# CONFIG_IDEDMA_AUTO is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI device support +# +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +# CONFIG_BLK_DEV_SD is not set +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_REPORT_LUNS is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set + +# +# SCSI Transport Attributes +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set + +# +# SCSI low-level drivers +# +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_SATA is not set +# CONFIG_SCSI_EATA_PIO is not set +# CONFIG_SCSI_DEBUG is not set + +# +# Fusion MPT device support +# + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input I/O drivers +# +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y +# CONFIG_SERIO is not set +# CONFIG_SERIO_I8042 is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_SERIAL_LH7A40X=y +CONFIG_SERIAL_LH7A40X_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_QIC02_TAPE is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_NVRAM is not set +CONFIG_RTC=y +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +# CONFIG_DEVPTS_FS_XATTR is not set +CONFIG_TMPFS=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_NAND is not set +CONFIG_CRAMFS=y +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +# CONFIG_EXPORTFS is not set +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_NEC98_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_EFI_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Graphics support +# +# CONFIG_FB is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +# CONFIG_MDA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# Misc devices +# + +# +# USB support +# +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_BANDWIDTH is not set +# CONFIG_USB_DYNAMIC_MINORS is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_EHCI_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811HS is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_BLUETOOTH_TTY is not set +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DEBUG=y +CONFIG_USB_STORAGE_DATAFAB=y +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_HP8200e is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set + +# +# USB Human Interface Devices (HID) +# +CONFIG_USB_HID=y +CONFIG_USB_HIDINPUT=y +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set +# CONFIG_USB_AIPTEK is not set +# CONFIG_USB_WACOM is not set +# CONFIG_USB_KBTAB is not set +# CONFIG_USB_POWERMATE is not set +# CONFIG_USB_MTOUCH is not set +# CONFIG_USB_XPAD is not set +# CONFIG_USB_ATI_REMOTE is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_HPUSBSCSI is not set + +# +# USB Multimedia devices +# +# CONFIG_USB_DABUSB is not set + +# +# Video4Linux support is needed for USB Multimedia device support +# + +# +# USB Network adaptors +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_TIGL is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_TEST is not set + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set + +# +# Kernel hacking +# +CONFIG_FRAME_POINTER=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SLAB is not set +CONFIG_MAGIC_SYSRQ=y +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_WAITQ is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_LL is not set + +# +# Security options +# +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_CRC32=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S index 319b21e4fc78..9c0acea28224 100644 --- a/arch/arm/kernel/debug.S +++ b/arch/arm/kernel/debug.S @@ -550,6 +550,33 @@ 1002: @ exit busyuart .endm +#elif defined(CONFIG_ARCH_LH7A40X) + @ It isn't known if this will be appropriate for every 40x + @ board. + + .macro addruart,rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + ldr \rx, =0x80000700 @ physical base address + orrne \rx, \rx, #0xf8000000 @ virtual base + .endm + + .macro senduart,rd,rx + strb \rd, [\rx] @ DATA + .endm + + .macro busyuart,rd,rx @ spin while busy +1001: ldr \rd, [\rx, #0x10] @ STATUS + tst \rd, #1 << 3 @ BUSY (TX FIFO not empty) + bne 1001b @ yes, spin + .endm + + .macro waituart,rd,rx @ wait for Tx FIFO room +1001: ldrb \rd, [\rx, #0x10] @ STATUS + tst \rd, #1 << 5 @ TXFF (TX FIFO full) + bne 1001b @ yes, spin + .endm + #elif defined(CONFIG_ARCH_VERSATILE_PB) diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 0bb77b9fb0ab..2e85a9944735 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -789,6 +789,67 @@ ENTRY(soft_irq_mask) .macro irq_prio_table .endm +#elif defined(CONFIG_ARCH_LH7A400) + +# if defined (CONFIG_ARCH_LH7A404) +# error "LH7A400 and LH7A404 are mutually exclusive" +# endif + .macro disable_fiq + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + mov \irqnr, #0 + mov \base, #io_p2v(0x80000000) @ APB registers + ldr \irqstat, [\base, #0x500] @ PIC INTSR + +1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry + bcs 1008f @ Bit set; irq found + add \irqnr, \irqnr, #1 + bne 1001b @ Until no bits + b 1009f @ Nothing? Hmm. +1008: movs \irqstat, #1 @ Force !Z +1009: + .endm + + .macro irq_prio_table + .endm + +#elif defined(CONFIG_ARCH_LH7A404) + + .macro disable_fiq + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + mov \irqnr, #0 @ VIC1 irq base + mov \base, #io_p2v(0x80000000) @ APB registers + add \base, \base, #0x8000 + ldr \tmp, [\base, #0x0030] @ VIC1_VECTADDR + tst \tmp, #VA_VECTORED @ Direct vectored + bne 1002f + tst \tmp, #VA_VIC1DEFAULT @ Default vectored VIC1 + ldrne \irqstat, [\base, #0] @ VIC1_IRQSTATUS + bne 1001f + add \base, \base, #(0xa000 - 0x8000) + ldr \tmp, [\base, #0x0030] @ VIC2_VECTADDR + tst \tmp, #VA_VECTORED @ Direct vectored + bne 1002f + ldr \irqstat, [\base, #0] @ VIC2_IRQSTATUS + mov \irqnr, #32 @ VIC2 irq base + +1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry + bcs 1008f @ Bit set; irq found + add \irqnr, \irqnr, #1 + bne 1001b @ Until no bits + b 1009f @ Nothing? Hmm. +1002: and \irqnr, \tmp, #0x3f @ Mask for valid bits +1008: movs \irqstat, #1 @ Force !Z + str \tmp, [\base, #0x0030] @ Clear vector +1009: + .endm + + .macro irq_prio_table + .endm + #else #error Unknown architecture #endif diff --git a/arch/arm/mach-lh7a40x/Kconfig b/arch/arm/mach-lh7a40x/Kconfig new file mode 100644 index 000000000000..4475dba7218f --- /dev/null +++ b/arch/arm/mach-lh7a40x/Kconfig @@ -0,0 +1,39 @@ + +menu "LH7A40X Implementations" + +config MACH_KEV7A400 + bool "KEV7A400" + depends on ARCH_LH7A40X + select ARCH_LH7A400 + help + Say Y here if you are using the Sharp KEV7A400 development + board. This hardware is discontinued, so I'd be very + suprised if you wanted this option. + +config MACH_LPD7A400 + bool "LPD7A400 Card Engine" + depends on ARCH_LH7A40X + select ARCH_LH7A400 + select IDE_POLL + help + Say Y here if you are using Logic Product Development's + LPD7A400 CardEngine. For the time being, the LPD7A400 and + LPD7A404 options are mutually exclusive. + +config MACH_LPD7A404 + bool "LPD7A404 Card Engine" + depends on ARCH_LH7A40X + select ARCH_LH7A404 + select IDE_POLL + help + Say Y here if you are using Logic Product Development's + LPD7A404 CardEngine. For the time being, the LPD7A400 and + LPD7A404 options are mutually exclusive. + +config ARCH_LH7A400 + bool + +config ARCH_LH7A404 + bool + +endmenu diff --git a/arch/arm/mach-lh7a40x/Makefile b/arch/arm/mach-lh7a40x/Makefile new file mode 100644 index 000000000000..db3be5a23a8a --- /dev/null +++ b/arch/arm/mach-lh7a40x/Makefile @@ -0,0 +1,15 @@ +# +# Makefile for the linux kernel. +# + +# Object file lists. + +obj-y := fiq.o +# generic.o +obj-$(CONFIG_MACH_KEV7A400) += arch-kev7a400.o irq-lh7a400.o +obj-$(CONFIG_MACH_LPD7A400) += arch-lpd7a40x.o ide-lpd7a40x.o irq-lh7a400.o +obj-$(CONFIG_MACH_LPD7A404) += arch-lpd7a40x.o ide-lpd7a40x.o irq-lh7a404.o + +obj-m := +obj-n := +obj- := diff --git a/arch/arm/mach-lh7a40x/arch-kev7a400.c b/arch/arm/mach-lh7a40x/arch-kev7a400.c new file mode 100644 index 000000000000..73d8b6b56e4c --- /dev/null +++ b/arch/arm/mach-lh7a40x/arch-kev7a400.c @@ -0,0 +1,111 @@ +/* arch/arm/mach-lh7a40x/arch-kev7a400.c + * + * Copyright (C) 2004 Logic Product Development + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +#include <linux/tty.h> +#include <linux/init.h> +#include <linux/device.h> + +#include <asm/hardware.h> +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/hardware.h> /* io_p2v() */ +#include <asm/irq.h> +#include <asm/mach/irq.h> +#include <asm/mach/map.h> + +#include <linux/interrupt.h> + + /* This function calls the board specific IRQ initialization function. */ +extern void lh7a400_init_irq (void); + +static struct map_desc kev7a400_io_desc[] __initdata = { + { IO_VIRT, IO_PHYS, IO_SIZE, MT_DEVICE }, + { CPLD_VIRT, CPLD_PHYS, CPLD_SIZE, MT_DEVICE }, +}; + +void __init kev7a400_map_io(void) +{ + iotable_init (kev7a400_io_desc, ARRAY_SIZE (kev7a400_io_desc)); +} + +static u16 CPLD_IRQ_mask; /* Mask for CPLD IRQs, 1 == unmasked */ + +static void kev7a400_ack_cpld_irq (u32 irq) +{ + CPLD_CL_INT = 1 << (irq - IRQ_KEV7A400_CPLD); +} + +static void kev7a400_mask_cpld_irq (u32 irq) +{ + CPLD_IRQ_mask &= ~(1 << (irq - IRQ_KEV7A400_CPLD)); + CPLD_WR_PB_INT_MASK = CPLD_IRQ_mask; +} + +static void kev7a400_unmask_cpld_irq (u32 irq) +{ + CPLD_IRQ_mask |= 1 << (irq - IRQ_KEV7A400_CPLD); + CPLD_WR_PB_INT_MASK = CPLD_IRQ_mask; +} + +static struct irqchip kev7a400_cpld_chip = { + .ack = kev7a400_ack_cpld_irq, + .mask = kev7a400_mask_cpld_irq, + .unmask = kev7a400_unmask_cpld_irq, +}; + + +static void kev7a400_cpld_handler (unsigned int irq, struct irqdesc *desc, + struct pt_regs *regs) +{ + u32 mask = CPLD_LATCHED_INTS; + irq = IRQ_KEV7A400_CPLD; + for (; mask; mask >>= 1, ++irq) { + if (mask & 1) + desc[irq].handle (irq, desc, regs); + } +} + +void __init lh7a40x_init_board_irq (void) +{ + int irq; + + for (irq = IRQ_KEV7A400_CPLD; + irq < IRQ_KEV7A400_CPLD + NR_IRQ_BOARD; ++irq) { + set_irq_chip (irq, &kev7a400_cpld_chip); + set_irq_handler (irq, do_edge_IRQ); + set_irq_flags (irq, IRQF_VALID); + } + set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler); + + /* Clear all CPLD interrupts */ + CPLD_CL_INT = 0xff; /* CPLD_INTR_MMC_CD | CPLD_INTR_ETH_INT; */ + + GPIO_GPIOINTEN = 0; /* Disable all GPIO interrupts */ + barrier(); + +#if 0 + GPIO_INTTYPE1 + = (GPIO_INTR_PCC1_CD | GPIO_INTR_PCC1_CD); /* Edge trig. */ + GPIO_INTTYPE2 = 0; /* Falling edge & low-level */ + GPIO_GPIOFEOI = 0xff; /* Clear all GPIO interrupts */ + GPIO_GPIOINTEN = 0xff; /* Enable all GPIO interrupts */ + + init_FIQ(); +#endif +} + +MACHINE_START (KEV7A400, "Sharp KEV7a400") + MAINTAINER ("Marc Singer") + BOOT_MEM (0xc0000000, 0x80000000, io_p2v (0x80000000)) + BOOT_PARAMS (0xc0000100) + MAPIO (kev7a400_map_io) + INITIRQ (lh7a400_init_irq) +MACHINE_END diff --git a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c new file mode 100644 index 000000000000..734cc75810e4 --- /dev/null +++ b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c @@ -0,0 +1,288 @@ +/* arch/arm/mach-lh7a40x/arch-lpd7a40x.c + * + * Copyright (C) 2004 Logic Product Development + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +#include <linux/tty.h> +#include <linux/init.h> +#include <linux/device.h> + +#include <asm/hardware.h> +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/hardware.h> /* io_p2v() */ +#include <asm/irq.h> +#include <asm/mach/irq.h> +#include <asm/mach/map.h> + +#include <linux/interrupt.h> + +static struct resource smc91x_resources[] = { + [0] = { + .start = CPLD00_PHYS, + .end = CPLD00_PHYS + CPLD00_SIZE - 1, /* Only needs 16B */ + .flags = IORESOURCE_MEM, + }, + + [1] = { + .start = IRQ_LPD7A40X_ETH_INT, + .end = IRQ_LPD7A40X_ETH_INT, + .flags = IORESOURCE_IRQ, + }, + +}; + +static struct platform_device smc91x_device = { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, +}; + +#if 0 +static struct resource lh7a40x_usbclient_resources[] = { + [0] = { + .start = USB_PHYS, + .end = (USB_PHYS + 0xFF), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_USB, + .end = IRQ_USB, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 lh7a40x_usbclient_dma_mask = 0xffffffffUL; + +static struct platform_device lh7a40x_usbclient_device = { + .name = "lh7a40x-udc", + .id = 0, + .dev = { + .dma_mask = &lh7a40x_usbclient_dma_mask, + .coherent_dma_mask = 0xffffffffUL, + }, + .num_resources = ARRAY_SIZE (lh7a40x_usbclient_resources), + .resource = lh7a40x_usbclient_resources, +}; +#endif + +#if defined (CONFIG_ARCH_LH7A404) + +static struct resource lh7a404_usbhost_resources [] = { + [0] = { + .start = USBH_PHYS, + .end = (USBH_PHYS + 0xFF), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_USHINTR, + .end = IRQ_USHINTR, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 lh7a404_usbhost_dma_mask = 0xffffffffUL; + +static struct platform_device lh7a404_usbhost_device = { + .name = "lh7a404-ohci", + .id = 0, + .dev = { + .dma_mask = &lh7a404_usbhost_dma_mask, + .coherent_dma_mask = 0xffffffffUL, + }, + .num_resources = ARRAY_SIZE (lh7a404_usbhost_resources), + .resource = lh7a404_usbhost_resources, +}; + +#endif + +static struct platform_device *lpd7a40x_devs[] __initdata = { + &smc91x_device, +/* &lh7a40x_usbclient_device, */ + +#if defined (CONFIG_ARCH_LH7A404) + &lh7a404_usbhost_device, +#endif +}; + +extern void lpd7a400_map_io (void); + +static void __init lpd7a40x_init (void) +{ + CPLD_CONTROL = 0x0; /* Enable LAN (Disable LCD) */ + platform_add_devices (lpd7a40x_devs, ARRAY_SIZE (lpd7a40x_devs)); +} + +static void lh7a40x_ack_cpld_irq (u32 irq) +{ + /* CPLD doesn't have ack capability */ +} + +static void lh7a40x_mask_cpld_irq (u32 irq) +{ + switch (irq) { + case IRQ_LPD7A40X_ETH_INT: + CPLD_INTERRUPTS = CPLD_INTERRUPTS | 0x4; + break; + case IRQ_LPD7A400_TS: + CPLD_INTERRUPTS = CPLD_INTERRUPTS | 0x8; + break; + } +} + +static void lh7a40x_unmask_cpld_irq (u32 irq) +{ + switch (irq) { + case IRQ_LPD7A40X_ETH_INT: + CPLD_INTERRUPTS = CPLD_INTERRUPTS & ~ 0x4; + break; + case IRQ_LPD7A400_TS: + CPLD_INTERRUPTS = CPLD_INTERRUPTS & ~ 0x8; + break; + } +} + +static struct irqchip lpd7a40x_cpld_chip = { + .ack = lh7a40x_ack_cpld_irq, + .mask = lh7a40x_mask_cpld_irq, + .unmask = lh7a40x_unmask_cpld_irq, +}; + +#define IRQ_DISPATCH(irq) irq_desc[irq].handle ((irq), &irq_desc[irq], regs) + +static void lpd7a40x_cpld_handler (unsigned int irq, struct irqdesc *desc, + struct pt_regs *regs) +{ + unsigned int mask = CPLD_INTERRUPTS; + + desc->chip->ack (irq); + + if ((mask & 0x1) == 0) /* WLAN */ + IRQ_DISPATCH (IRQ_LPD7A40X_ETH_INT); + + if ((mask & 0x2) == 0) /* Touch */ + IRQ_DISPATCH (IRQ_LPD7A400_TS); + + desc->chip->unmask (irq); /* Level-triggered need this */ +} + + +void __init lh7a40x_init_board_irq (void) +{ + int irq; + + /* Rev A (v2.8): PF0, PF1, PF2, and PF3 are available IRQs. + PF7 supports the CPLD. + Rev B (v3.4): PF0, PF1, and PF2 are available IRQs. + PF3 supports the CPLD. + (Some) LPD7A404 prerelease boards report a version + number of 0x16, but we force an override since the + hardware is of the newer variety. + */ + + unsigned char cpld_version = CPLD_REVISION; + int pinCPLD = (cpld_version == 0x28) ? 7 : 3; + +#if defined CONFIG_MACH_LPD7A404 + cpld_version = 0x34; /* Override, for now */ +#endif + + /* First, configure user controlled GPIOF interrupts */ + + GPIO_PFDD &= ~0x0f; /* PF0-3 are inputs */ + GPIO_INTTYPE1 &= ~0x0f; /* PF0-3 are level triggered */ + GPIO_INTTYPE2 &= ~0x0f; /* PF0-3 are active low */ + barrier (); + GPIO_GPIOFINTEN |= 0x0f; /* Enable PF0, PF1, PF2, and PF3 IRQs */ + + /* Then, configure CPLD interrupt */ + + CPLD_INTERRUPTS = 0x0c; /* Disable all CPLD interrupts */ + GPIO_PFDD &= ~(1 << pinCPLD); /* Make input */ + GPIO_INTTYPE1 |= (1 << pinCPLD); /* Edge triggered */ + GPIO_INTTYPE2 &= ~(1 << pinCPLD); /* Active low */ + barrier (); + GPIO_GPIOFINTEN |= (1 << pinCPLD); /* Enable */ + + /* Cascade CPLD interrupts */ + + for (irq = IRQ_BOARD_START; + irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) { + set_irq_chip (irq, &lpd7a40x_cpld_chip); + set_irq_handler (irq, do_edge_IRQ); + set_irq_flags (irq, IRQF_VALID); + } + + set_irq_chained_handler ((cpld_version == 0x28) + ? IRQ_CPLD_V28 + : IRQ_CPLD_V34, + lpd7a40x_cpld_handler); +} + +static struct map_desc lpd7a400_io_desc[] __initdata = { + { IO_VIRT, IO_PHYS, IO_SIZE, MT_DEVICE }, + /* Mapping added to work around chip select problems */ + { IOBARRIER_VIRT, IOBARRIER_PHYS, IOBARRIER_SIZE, MT_DEVICE }, + { CF_VIRT, CF_PHYS, CF_SIZE, MT_DEVICE }, + /* This mapping is redundant since the smc driver performs another. */ +/* { CPLD00_VIRT, CPLD00_PHYS, CPLD00_SIZE, MT_DEVICE }, */ + { CPLD02_VIRT, CPLD02_PHYS, CPLD02_SIZE, MT_DEVICE }, + { CPLD06_VIRT, CPLD06_PHYS, CPLD06_SIZE, MT_DEVICE }, + { CPLD08_VIRT, CPLD08_PHYS, CPLD08_SIZE, MT_DEVICE }, + { CPLD0C_VIRT, CPLD0C_PHYS, CPLD0C_SIZE, MT_DEVICE }, + { CPLD0E_VIRT, CPLD0E_PHYS, CPLD0E_SIZE, MT_DEVICE }, + { CPLD10_VIRT, CPLD10_PHYS, CPLD10_SIZE, MT_DEVICE }, + { CPLD12_VIRT, CPLD12_PHYS, CPLD12_SIZE, MT_DEVICE }, + { CPLD14_VIRT, CPLD14_PHYS, CPLD14_SIZE, MT_DEVICE }, + { CPLD16_VIRT, CPLD16_PHYS, CPLD16_SIZE, MT_DEVICE }, + { CPLD18_VIRT, CPLD18_PHYS, CPLD18_SIZE, MT_DEVICE }, + { CPLD1A_VIRT, CPLD1A_PHYS, CPLD1A_SIZE, MT_DEVICE }, +}; + +void __init +lpd7a400_map_io(void) +{ + iotable_init (lpd7a400_io_desc, ARRAY_SIZE (lpd7a400_io_desc)); + + /* Fixup (improve) Static Memory Controller settings */ + SMC_BCR0 = 0x200039af; /* Boot Flash */ + SMC_BCR6 = 0x1000fbe0; /* CPLD */ + SMC_BCR7 = 0x1000b2c2; /* Compact Flash */ +} + +#ifdef CONFIG_MACH_LPD7A400 + +extern void lh7a400_init_irq (void); + +MACHINE_START (LPD7A400, "Logic Product Development LPD7A400-10") + MAINTAINER ("Marc Singer") + BOOT_MEM (0xc0000000, 0x80000000, io_p2v (0x80000000)) + BOOT_PARAMS (0xc0000100) + MAPIO (lpd7a400_map_io) + INITIRQ (lh7a400_init_irq) + INIT_MACHINE (lpd7a40x_init) +MACHINE_END + +#endif + +#ifdef CONFIG_MACH_LPD7A404 + +extern void lh7a404_init_irq (void); + +MACHINE_START (LPD7A404, "Logic Product Development LPD7A404-10") + MAINTAINER ("Marc Singer") + BOOT_MEM (0xc0000000, 0x80000000, io_p2v (0x80000000)) + BOOT_PARAMS (0xc0000100) + MAPIO (lpd7a400_map_io) + INITIRQ (lh7a404_init_irq) + INIT_MACHINE (lpd7a40x_init) +MACHINE_END + +#endif diff --git a/arch/arm/mach-lh7a40x/fiq.S b/arch/arm/mach-lh7a40x/fiq.S new file mode 100644 index 000000000000..fefedf844a51 --- /dev/null +++ b/arch/arm/mach-lh7a40x/fiq.S @@ -0,0 +1,39 @@ +/* + * linux/arch/arm/lib/lh7a400-fiqhandler.S + * Copyright (C) 2002, Lineo, Inc. + * based on linux/arch/arm/lib/floppydma.S, which is + * Copyright (C) 1995, 1996 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/linkage.h> +#include <asm/assembler.h> + .text + + .global fiqhandler_end + + @ register usage: + @ r8 &interrupt controller registers + @ r9 &gpio registers + @ r11 work + @ r12 work + +ENTRY(fiqhandler) + + @ read the status register to find out which FIQ this is + + ldr r12, [r8] @ intc->status + and r12, r12, #0xf @ only interested in low-order 4 bits + + @ translate FIQ 0:3 to IRQ 23:26 + @ disable this FIQ and enable the corresponding IRQ + + str r12, [r8, #0xc] @ disable this FIQ + mov r12, r12, lsl #23 @ get the corresopnding IRQ bit + str r12, [r8, #0x8] @ enable that IRQ + + subs pc, lr, #4 +fiqhandler_end: + diff --git a/arch/arm/mach-lh7a40x/ide-lpd7a40x.c b/arch/arm/mach-lh7a40x/ide-lpd7a40x.c new file mode 100644 index 000000000000..fedca413d8fe --- /dev/null +++ b/arch/arm/mach-lh7a40x/ide-lpd7a40x.c @@ -0,0 +1,166 @@ +/* arch/arm/mach-lh7a40x/ide-lpd7a40x.c + * + * Copyright (C) 2004 Logic Product Development + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + + +#include <linux/config.h> +#include <linux/ide.h> + +#include <asm/io.h> + +#define IOBARRIER_READ readl (IOBARRIER_VIRT) + +static u8 lpd7a40x_ide_inb (unsigned long port) +{ + u16 v = (u16) readw (port & ~0x1); + IOBARRIER_READ; + if (port & 0x1) + v >>= 8; + return v & 0xff; +} + +static u16 lpd7a40x_ide_inw (unsigned long port) +{ + u16 v = (u16) readw (port); + IOBARRIER_READ; + return v; +} + +static void lpd7a40x_ide_insw (unsigned long port, void *addr, u32 count) +{ + while (count--) { + *((u16*) addr)++ = (u16) readw (port); + IOBARRIER_READ; + } +} + +static u32 lpd7a40x_ide_inl (unsigned long port) +{ + u32 v = (u16) readw (port); + IOBARRIER_READ; + v |= (u16) readw (port + 2); + IOBARRIER_READ; + + return v; +} + +static void lpd7a40x_ide_insl (unsigned long port, void *addr, u32 count) +{ + while (count--) { + *((u16*) addr)++ = (u16) readw (port); + IOBARRIER_READ; + *((u16*) addr)++ = (u16) readw (port + 2); + IOBARRIER_READ; + } +} + +/* lpd7a40x_ide_outb -- this function is complicated by the fact that + * the user wants to be able to do byte IO and the hardware cannot. + * In order to write the high byte, we need to write a short. So, we + * read before writing in order to maintain the register values that + * shouldn't change. This isn't a good idea for the data IO registers + * since reading from them will not return the current value. We + * expect that this function handles the control register adequately. +*/ + +static void lpd7a40x_ide_outb (u8 valueUser, unsigned long port) +{ + /* Block writes to SELECT register. Draconian, but the only + * way to cope with this hardware configuration without + * modifying the SELECT_DRIVE call in the ide driver. */ + if ((port & 0xf) == 0x6) + return; + + if (port & 0x1) { /* Perform read before write. Only + * the COMMAND register needs + * this. */ + u16 value = (u16) readw (port & ~0x1); + IOBARRIER_READ; + value = (value & 0x00ff) | (valueUser << 8); + writew (value, port & ~0x1); + IOBARRIER_READ; + } + else { /* Allow low-byte writes which seem to + * be OK. */ + writeb (valueUser, port); + IOBARRIER_READ; + } +} + +static void lpd7a40x_ide_outbsync (ide_drive_t *drive, u8 value, + unsigned long port) +{ + lpd7a40x_ide_outb (value, port); +} + +static void lpd7a40x_ide_outw (u16 value, unsigned long port) +{ + writew (value, port); + IOBARRIER_READ; +} + +static void lpd7a40x_ide_outsw (unsigned long port, void *addr, u32 count) +{ + while (count-- > 0) { + writew (*((u16*) addr)++, port); + IOBARRIER_READ; + } +} + +static void lpd7a40x_ide_outl (u32 value, unsigned long port) +{ + writel (value, port); + IOBARRIER_READ; +} + +static void lpd7a40x_ide_outsl (unsigned long port, void *addr, u32 count) +{ + while (count-- > 0) { + writel (*((u32*) addr)++, port); + IOBARRIER_READ; + } +} + +void lpd7a40x_SELECT_DRIVE (ide_drive_t *drive) +{ + unsigned jifStart = jiffies; +#define WAIT_TIME (30*HZ/1000) + + /* Check for readiness. */ + while ((HWIF(drive)->INB(IDE_STATUS_REG) & 0x40) == 0) + if (jifStart <= jiffies + WAIT_TIME) + return; + + /* Only allow one drive. + For more information, see Documentation/arm/Sharp-LH/ */ + if (drive->select.all & (1<<4)) + return; + + /* OUTW so that the IDLE_IMMEDIATE (and not NOP) command is sent. */ + HWIF(drive)->OUTW(drive->select.all | 0xe100, IDE_SELECT_REG); +} + +void lpd7a40x_hwif_ioops (ide_hwif_t *hwif) +{ + hwif->mmio = 2; /* Just for show */ + hwif->irq = IDE_NO_IRQ; /* Stop this probing */ + + hwif->OUTB = lpd7a40x_ide_outb; + hwif->OUTBSYNC = lpd7a40x_ide_outbsync; + hwif->OUTW = lpd7a40x_ide_outw; + hwif->OUTL = lpd7a40x_ide_outl; + hwif->OUTSW = lpd7a40x_ide_outsw; + hwif->OUTSL = lpd7a40x_ide_outsl; + hwif->INB = lpd7a40x_ide_inb; + hwif->INW = lpd7a40x_ide_inw; + hwif->INL = lpd7a40x_ide_inl; + hwif->INSW = lpd7a40x_ide_insw; + hwif->INSL = lpd7a40x_ide_insl; + hwif->selectproc = lpd7a40x_SELECT_DRIVE; +} diff --git a/arch/arm/mach-lh7a40x/irq-kev7a400.c b/arch/arm/mach-lh7a40x/irq-kev7a400.c new file mode 100644 index 000000000000..691bb09232a5 --- /dev/null +++ b/arch/arm/mach-lh7a40x/irq-kev7a400.c @@ -0,0 +1,92 @@ +/* arch/arm/mach-lh7a40x/irq-kev7a400.c + * + * Copyright (C) 2004 Coastal Environmental Systems + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +#include <linux/interrupt.h> +#include <linux/init.h> + +#include <asm/irq.h> +#include <asm/mach/irq.h> +#include <asm/mach/hardware.h> +#include <asm/mach/irqs.h> + + + /* KEV7a400 CPLD IRQ handling */ + +static u16 CPLD_IRQ_mask; /* Mask for CPLD IRQs, 1 == unmasked */ + +static void +lh7a400_ack_cpld_irq (u32 irq) +{ + CPLD_CL_INT = 1 << (irq - IRQ_KEV7A400_CPLD); +} + +static void +lh7a400_mask_cpld_irq (u32 irq) +{ + CPLD_IRQ_mask &= ~(1 << (irq - IRQ_KEV7A400_CPLD)); + CPLD_WR_PB_INT_MASK = CPLD_IRQ_mask; +} + +static void +lh7a400_unmask_cpld_irq (u32 irq) +{ + CPLD_IRQ_mask |= 1 << (irq - IRQ_KEV7A400_CPLD); + CPLD_WR_PB_INT_MASK = CPLD_IRQ_mask; +} + +static struct +irqchip lh7a400_cpld_chip = { + .ack = lh7a400_ack_cpld_irq, + .mask = lh7a400_mask_cpld_irq, + .unmask = lh7a400_unmask_cpld_irq, +}; + +static void +lh7a400_cpld_handler (unsigned int irq, struct irqdesc *desc, + struct pt_regs *regs) +{ + u32 mask = CPLD_LATCHED_INTS; + irq = IRQ_KEV_7A400_CPLD; + for (; mask; mask >>= 1, ++irq) { + if (mask & 1) + desc[irq].handle (irq, desc, regs); + } +} + + /* IRQ initialization */ + +void __init +lh7a400_init_board_irq (void) +{ + int irq; + + for (irq = IRQ_KEV7A400_CPLD; + irq < IRQ_KEV7A400_CPLD + NR_IRQ_KEV7A400_CPLD; ++irq) { + set_irq_chip (irq, &lh7a400_cpld_chip); + set_irq_handler (irq, do_edge_IRQ); + set_irq_flags (irq, IRQF_VALID); + } + set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler); + + /* Clear all CPLD interrupts */ + CPLD_CL_INT = 0xff; /* CPLD_INTR_MMC_CD | CPLD_INTR_ETH_INT; */ + + /* *** FIXME CF enabled in ide-probe.c */ + + GPIO_GPIOINTEN = 0; /* Disable all GPIO interrupts */ + barrier(); + GPIO_INTTYPE1 + = (GPIO_INTR_PCC1_CD | GPIO_INTR_PCC1_CD); /* Edge trig. */ + GPIO_INTTYPE2 = 0; /* Falling edge & low-level */ + GPIO_GPIOFEOI = 0xff; /* Clear all GPIO interrupts */ + GPIO_GPIOINTEN = 0xff; /* Enable all GPIO interrupts */ + + init_FIQ(); +} diff --git a/arch/arm/mach-lh7a40x/irq-lh7a400.c b/arch/arm/mach-lh7a40x/irq-lh7a400.c new file mode 100644 index 000000000000..f334d81c2cd8 --- /dev/null +++ b/arch/arm/mach-lh7a40x/irq-lh7a400.c @@ -0,0 +1,90 @@ +/* arch/arm/mach-lh7a40x/irq-lh7a400.c + * + * Copyright (C) 2004 Coastal Environmental Systems + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/ptrace.h> + +#include <asm/hardware.h> +#include <asm/irq.h> +#include <asm/mach/irq.h> +#include <asm/arch/irq.h> +#include <asm/arch/irqs.h> + + + /* CPU IRQ handling */ + +static void lh7a400_mask_irq (u32 irq) +{ + INTC_INTENC = (1 << irq); +} + +static void lh7a400_unmask_irq (u32 irq) +{ + INTC_INTENS = (1 << irq); +} + +static void lh7a400_ack_gpio_irq (u32 irq) +{ + GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (irq)); + INTC_INTENC = (1 << irq); +} + +static struct irqchip lh7a400_internal_chip = { + .ack = lh7a400_mask_irq, /* Level triggering -> mask is ack */ + .mask = lh7a400_mask_irq, + .unmask = lh7a400_unmask_irq, +}; + +static struct irqchip lh7a400_gpio_chip = { + .ack = lh7a400_ack_gpio_irq, + .mask = lh7a400_mask_irq, + .unmask = lh7a400_unmask_irq, +}; + + + /* IRQ initialization */ + +void __init lh7a400_init_irq (void) +{ + int irq; + + INTC_INTENC = 0xffffffff; /* Disable all interrupts */ + GPIO_GPIOFINTEN = 0x00; /* Disable all GPIOF interrupts */ + barrier (); + + for (irq = 0; irq < NR_IRQS; ++irq) { + switch (irq) { + case IRQ_GPIO0INTR: + case IRQ_GPIO1INTR: + case IRQ_GPIO2INTR: + case IRQ_GPIO3INTR: + case IRQ_GPIO4INTR: + case IRQ_GPIO5INTR: + case IRQ_GPIO6INTR: + case IRQ_GPIO7INTR: + set_irq_chip (irq, &lh7a400_gpio_chip); + set_irq_handler (irq, do_level_IRQ); /* OK default */ + break; + default: + set_irq_chip (irq, &lh7a400_internal_chip); + set_irq_handler (irq, do_level_IRQ); + } + set_irq_flags (irq, IRQF_VALID); + } + + lh7a40x_init_board_irq (); + +/* *** FIXME: the LH7a400 does use FIQ interrupts in some cases. For + the time being, these are not initialized. */ + +/* init_FIQ(); */ +} diff --git a/arch/arm/mach-lh7a40x/irq-lh7a404.c b/arch/arm/mach-lh7a40x/irq-lh7a404.c new file mode 100644 index 000000000000..122fadabc97d --- /dev/null +++ b/arch/arm/mach-lh7a40x/irq-lh7a404.c @@ -0,0 +1,158 @@ +/* arch/arm/mach-lh7a40x/irq-lh7a404.c + * + * Copyright (C) 2004 Logic Product Development + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/ptrace.h> + +#include <asm/hardware.h> +#include <asm/irq.h> +#include <asm/mach/irq.h> +#include <asm/arch/irq.h> +#include <asm/arch/irqs.h> + +#define USE_PRIORITIES + +/* See Documentation/arm/Sharp-LH/VectoredInterruptController for more + * information on using the vectored interrupt controller's + * prioritizing feature. */ + +static unsigned char irq_pri_vic1[] = { +#if defined (USE_PRIORITIES) +IRQ_GPIO3INTR, +#endif +}; +static unsigned char irq_pri_vic2[] = { +#if defined (USE_PRIORITIES) + IRQ_T3UI, IRQ_GPIO7INTR, + IRQ_UART1INTR, IRQ_UART2INTR, IRQ_UART3INTR, +#endif +}; + + /* CPU IRQ handling */ + +static void lh7a404_vic1_mask_irq (u32 irq) +{ + VIC1_INTENCLR = (1 << irq); +} + +static void lh7a404_vic1_unmask_irq (u32 irq) +{ + VIC1_INTEN = (1 << irq); +} + +static void lh7a404_vic2_mask_irq (u32 irq) +{ + VIC2_INTENCLR = (1 << (irq - 32)); +} + +static void lh7a404_vic2_unmask_irq (u32 irq) +{ + VIC2_INTEN = (1 << (irq - 32)); +} + +static void lh7a404_vic1_ack_gpio_irq (u32 irq) +{ + GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (irq)); + VIC1_INTENCLR = (1 << irq); +} + +static void lh7a404_vic2_ack_gpio_irq (u32 irq) +{ + GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (irq)); + VIC2_INTENCLR = (1 << irq); +} + +static struct irqchip lh7a404_vic1_chip = { + .ack = lh7a404_vic1_mask_irq, /* Because level-triggered */ + .mask = lh7a404_vic1_mask_irq, + .unmask = lh7a404_vic1_unmask_irq, +}; + +static struct irqchip lh7a404_vic2_chip = { + .ack = lh7a404_vic2_mask_irq, /* Because level-triggered */ + .mask = lh7a404_vic2_mask_irq, + .unmask = lh7a404_vic2_unmask_irq, +}; + +static struct irqchip lh7a404_gpio_vic1_chip = { + .ack = lh7a404_vic1_ack_gpio_irq, + .mask = lh7a404_vic1_mask_irq, + .unmask = lh7a404_vic1_unmask_irq, +}; + +static struct irqchip lh7a404_gpio_vic2_chip = { + .ack = lh7a404_vic2_ack_gpio_irq, + .mask = lh7a404_vic2_mask_irq, + .unmask = lh7a404_vic2_unmask_irq, +}; + + /* IRQ initialization */ + +void __init lh7a404_init_irq (void) +{ + int irq; + + VIC1_INTENCLR = 0xffffffff; + VIC2_INTENCLR = 0xffffffff; + VIC1_INTSEL = 0; /* All IRQs */ + VIC2_INTSEL = 0; /* All IRQs */ + VIC1_NVADDR = VA_VIC1DEFAULT; + VIC2_NVADDR = VA_VIC2DEFAULT; + VIC1_VECTADDR = 0; + VIC2_VECTADDR = 0; + + GPIO_GPIOFINTEN = 0x00; /* Disable all GPIOF interrupts */ + barrier (); + + /* Install prioritized interrupts, if there are any. */ + /* The | 0x20*/ + for (irq = 0; irq < 16; ++irq) { + (&VIC1_VAD0)[irq] + = (irq < ARRAY_SIZE (irq_pri_vic1)) + ? (irq_pri_vic1[irq] | VA_VECTORED) : 0; + (&VIC1_VECTCNTL0)[irq] + = (irq < ARRAY_SIZE (irq_pri_vic1)) + ? (irq_pri_vic1[irq] | VIC_CNTL_ENABLE) : 0; + (&VIC2_VAD0)[irq] + = (irq < ARRAY_SIZE (irq_pri_vic2)) + ? (irq_pri_vic2[irq] | VA_VECTORED) : 0; + (&VIC2_VECTCNTL0)[irq] + = (irq < ARRAY_SIZE (irq_pri_vic2)) + ? (irq_pri_vic2[irq] | VIC_CNTL_ENABLE) : 0; + } + + for (irq = 0; irq < NR_IRQS; ++irq) { + switch (irq) { + case IRQ_GPIO0INTR: + case IRQ_GPIO1INTR: + case IRQ_GPIO2INTR: + case IRQ_GPIO3INTR: + case IRQ_GPIO4INTR: + case IRQ_GPIO5INTR: + case IRQ_GPIO6INTR: + case IRQ_GPIO7INTR: + set_irq_chip (irq, irq < 32 + ? &lh7a404_gpio_vic1_chip + : &lh7a404_gpio_vic2_chip); + set_irq_handler (irq, do_level_IRQ); /* OK default */ + break; + default: + set_irq_chip (irq, irq < 32 + ? &lh7a404_vic1_chip + : &lh7a404_vic2_chip); + set_irq_handler (irq, do_level_IRQ); + } + set_irq_flags (irq, IRQF_VALID); + } + + lh7a40x_init_board_irq (); +} diff --git a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c new file mode 100644 index 000000000000..458a16a6f659 --- /dev/null +++ b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c @@ -0,0 +1,130 @@ +/* arch/arm/mach-lh7a40x/irq-lpd7a40x.c + * + * Copyright (C) 2004 Coastal Environmental Systems + * Copyright (C) 2004 Logic Product Development + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/ptrace.h> + +#include <asm/hardware.h> +#include <asm/irq.h> +#include <asm/mach/irq.h> +#include <asm/arch/irqs.h> + + +static void lh7a40x_ack_cpld_irq (u32 irq) +{ + /* CPLD doesn't have ack capability */ +} + +static void lh7a40x_mask_cpld_irq (u32 irq) +{ + switch (irq) { + case IRQ_LPD7A40X_ETH_INT: + CPLD_INTERRUPTS = CPLD_INTERRUPTS | 0x4; + break; + case IRQ_LPD7A400_TS: + CPLD_INTERRUPTS = CPLD_INTERRUPTS | 0x8; + break; + } +} + +static void lh7a40x_unmask_cpld_irq (u32 irq) +{ + switch (irq) { + case IRQ_LPD7A40X_ETH_INT: + CPLD_INTERRUPTS = CPLD_INTERRUPTS & ~ 0x4; + break; + case IRQ_LPD7A400_TS: + CPLD_INTERRUPTS = CPLD_INTERRUPTS & ~ 0x8; + break; + } +} + +static struct irqchip lh7a40x_cpld_chip = { + .ack = lh7a40x_ack_cpld_irq, + .mask = lh7a40x_mask_cpld_irq, + .unmask = lh7a40x_unmask_cpld_irq, +}; + +#define IRQ_DISPATCH(irq) irq_desc[irq].handle ((irq), &irq_desc[irq], regs) + +static void lh7a40x_cpld_handler (unsigned int irq, struct irqdesc *desc, + struct pt_regs *regs) +{ + unsigned int mask = CPLD_INTERRUPTS; + + desc->chip->ack (irq); + + if ((mask & 0x1) == 0) /* WLAN */ + IRQ_DISPATCH (IRQ_LPD7A40X_ETH_INT); + + if ((mask & 0x2) == 0) /* Touch */ + IRQ_DISPATCH (IRQ_LPD7A400_TS); + + desc->chip->unmask (irq); /* Level-triggered need this */ +} + + + /* IRQ initialization */ + +void __init lh7a40x_init_board_irq (void) +{ + int irq; + + /* Rev A (v2.8): PF0, PF1, PF2, and PF3 are available IRQs. + PF7 supports the CPLD. + Rev B (v3.4): PF0, PF1, and PF2 are available IRQs. + PF3 supports the CPLD. + (Some) LPD7A404 prerelease boards report a version + number of 0x16, but we force an override since the + hardware is of the newer variety. + */ + + unsigned char cpld_version = CPLD_REVISION; + int pinCPLD; + +#if defined CONFIG_MACH_LPD7A404 + cpld_version = 0x34; /* Override, for now */ +#endif + pinCPLD = (cpld_version == 0x28) ? 7 : 3; + + /* First, configure user controlled GPIOF interrupts */ + + GPIO_PFDD &= ~0x0f; /* PF0-3 are inputs */ + GPIO_INTTYPE1 &= ~0x0f; /* PF0-3 are level triggered */ + GPIO_INTTYPE2 &= ~0x0f; /* PF0-3 are active low */ + barrier (); + GPIO_GPIOFINTEN |= 0x0f; /* Enable PF0, PF1, PF2, and PF3 IRQs */ + + /* Then, configure CPLD interrupt */ + + CPLD_INTERRUPTS = 0x0c; /* Disable all CPLD interrupts */ + GPIO_PFDD &= ~(1 << pinCPLD); /* Make input */ + GPIO_INTTYPE1 |= (1 << pinCPLD); /* Edge triggered */ + GPIO_INTTYPE2 &= ~(1 << pinCPLD); /* Active low */ + barrier (); + GPIO_GPIOFINTEN |= (1 << pinCPLD); /* Enable */ + + /* Cascade CPLD interrupts */ + + for (irq = IRQ_BOARD_START; + irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) { + set_irq_chip (irq, &lh7a40x_cpld_chip); + set_irq_handler (irq, do_edge_IRQ); + set_irq_flags (irq, IRQF_VALID); + } + + set_irq_chained_handler ((cpld_version == 0x28) + ? IRQ_CPLD_V28 + : IRQ_CPLD_V34, + lh7a40x_cpld_handler); +} diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig index 3fb5e466a911..30bc6dff3ab0 100644 --- a/arch/arm/mach-omap/Kconfig +++ b/arch/arm/mach-omap/Kconfig @@ -1,34 +1,79 @@ menu "TI OMAP Implementations" -choice - prompt "OMAP Core Type" +comment "OMAP Core Type" + +config ARCH_OMAP730 depends on ARCH_OMAP - default ARCH_OMAP1510 + bool "OMAP730 Based System" + select CPU_ARM926T config ARCH_OMAP1510 - bool "OMAP-1510 Based System" + depends on ARCH_OMAP + default y + bool "OMAP1510 Based System" select CPU_ARM925T select CPU_DCACHE_WRITETHROUGH config ARCH_OMAP1610 - bool "OMAP-1610 Based System" + depends on ARCH_OMAP + bool "OMAP1610 Based System" select CPU_ARM926T -endchoice - -choice - prompt "OMAP Board Type" +config ARCH_OMAP5912 depends on ARCH_OMAP - default MACH_OMAP_INNOVATOR + bool "OMAP5912 Based System" + select CPU_ARM926T + +comment "OMAP Board Type" config MACH_OMAP_INNOVATOR bool "TI Innovator" + default y depends on ARCH_OMAP1510 || ARCH_OMAP1610 help TI OMAP 1510 or 1610 Innovator board support. Say Y here if you have such a board. +config MACH_OMAP_H2 + bool "TI H2 Support" + depends on ARCH_OMAP1610 + select MACH_OMAP_INNOVATOR + help + TI OMAP 1610 H2 board support. Say Y here if you have such + a board. + +config MACH_OMAP_H3 + bool "TI H3 Support" + depends on ARCH_OMAP1610 + help + TI OMAP 1610 H3 board support. Say Y here if you have such + a board. + +config MACH_OMAP_H4 + bool "TI H4 Support" + depends on ARCH_OMAP1610 + help + TI OMAP 1610 H4 board support. Say Y here if you have such + a board. + +config MACH_OMAP_OSK + bool "TI OSK Support" + depends on ARCH_OMAP5912 + help + TI OMAP 5912 OSK (OMAP Starter Kit) board support. Say Y here + if you have such a board. + +config MACH_OMAP_PERSEUS2 + bool "TI Perseus2" + depends on ARCH_OMAP730 + select LEDS + select LEDS_TIMER + select LEDS_CPU + help + Support for TI OMAP 730 Perseus2 board. Say Y here if you have such + a board. + config MACH_OMAP_GENERIC bool "Generic OMAP board" depends on ARCH_OMAP1510 || ARCH_OMAP1610 @@ -38,16 +83,15 @@ config MACH_OMAP_GENERIC custom OMAP boards. Say Y here if you have a custom board. -endchoice - comment "OMAP Feature Selections" -config MACH_OMAP_H2 - bool "TI H2 Support" - depends on ARCH_OMAP1610 && MACH_OMAP_INNOVATOR - help - TI OMAP 1610 H2 board support. Say Y here if you have such - a board. +#config OMAP_BOOT_TAG +# bool "OMAP bootloader information passing" +# depends on ARCH_OMAP +# default n +# help +# Say Y, if you have a bootloader which passes information +# about your board and its peripheral configuration. config OMAP_MUX bool "OMAP multiplexing support" @@ -67,6 +111,22 @@ config OMAP_MUX_DEBUG This is useful if you want to find out the correct values of the multiplexing registers. +choice + prompt "Low-level debug console UART" + depends on ARCH_OMAP + default OMAP_LL_DEBUG_UART1 + +config OMAP_LL_DEBUG_UART1 + bool "UART1" + +config OMAP_LL_DEBUG_UART2 + bool "UART2" + +config OMAP_LL_DEBUG_UART3 + bool "UART3" + +endchoice + config OMAP_ARM_195MHZ bool "OMAP ARM 195 MHz CPU" depends on ARCH_OMAP730 @@ -75,7 +135,7 @@ config OMAP_ARM_195MHZ config OMAP_ARM_192MHZ bool "OMAP ARM 192 MHz CPU" - depends on ARCH_OMAP1610 + depends on ARCH_OMAP1610 || ARCH_OMAP5912 help Enable 192MHz clock for OMAP CPU. If unsure, say N. @@ -87,7 +147,7 @@ config OMAP_ARM_182MHZ config OMAP_ARM_168MHZ bool "OMAP ARM 168 MHz CPU" - depends on ARCH_OMAP1510 || ARCH_OMAP1610 || ARCH_OMAP730 + depends on ARCH_OMAP1510 || ARCH_OMAP1610 || ARCH_OMAP730 || ARCH_OMAP5912 help Enable 168MHz clock for OMAP CPU. If unsure, say N. diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile index a70a9e03c2f6..272535091bc4 100644 --- a/arch/arm/mach-omap/Makefile +++ b/arch/arm/mach-omap/Makefile @@ -9,28 +9,28 @@ obj-n := obj- := led-y := leds.o -# OCPI interconnect support for 1610 -ifeq ($(CONFIG_ARCH_OMAP1610),y) -obj-y += ocpi.o -ifeq ($(CONFIG_OMAP_INNOVATOR),y) -obj-y += innovator1610.o -endif -endif - -ifeq ($(CONFIG_ARCH_OMAP1510),y) -ifeq ($(CONFIG_OMAP_INNOVATOR),y) -obj-y += innovator1510.o fpga.o -endif -endif - # Specific board support -obj-$(CONFIG_MACH_OMAP_GENERIC) += omap-generic.o -obj-$(CONFIG_MACH_OMAP_PERSEUS2) += omap-perseus2.o +obj-$(CONFIG_MACH_OMAP_INNOVATOR) += board-innovator.o +obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o +obj-$(CONFIG_MACH_OMAP_PERSEUS2) += board-perseus2.o +obj-$(CONFIG_MACH_OMAP_OSK) += board-osk.o + +# OCPI interconnect support for 1610 and 5912 +obj-$(CONFIG_ARCH_OMAP1610) += ocpi.o +obj-$(CONFIG_ARCH_OMAP5912) += ocpi.o # LEDs support -led-$(CONFIG_OMAP_INNOVATOR) += leds-innovator.o +led-$(CONFIG_MACH_OMAP_INNOVATOR) += leds-innovator.o led-$(CONFIG_MACH_OMAP_PERSEUS2) += leds-perseus2.o obj-$(CONFIG_LEDS) += $(led-y) +# Power Management +obj-$(CONFIG_PM) += pm.o sleep.o + +ifeq ($(CONFIG_ARCH_OMAP1510),y) +# Innovator-1510 FPGA +obj-$(CONFIG_MACH_OMAP_INNOVATOR) += fpga.o +endif + # kgdb support obj-$(CONFIG_KGDB_SERIAL) += kgdb-serial.o diff --git a/arch/arm/mach-omap/board-generic.c b/arch/arm/mach-omap/board-generic.c new file mode 100644 index 000000000000..b0b45337d0c4 --- /dev/null +++ b/arch/arm/mach-omap/board-generic.c @@ -0,0 +1,74 @@ +/* + * linux/arch/arm/mach-omap/board-generic.c + * + * Modified from board-innovator1510.c + * + * Code for generic OMAP board. Should work on many OMAP systems where + * the device drivers take care of all the necessary hardware initialization. + * Do not put any board specific code to this file; create a new machine + * type if you need custom low-level initializations. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/device.h> + +#include <asm/hardware.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include <asm/arch/clocks.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mux.h> + +#include "common.h" + +static void __init omap_generic_init_irq(void) +{ + omap_init_irq(); +} + +/* + * Muxes the serial ports on + */ +static void __init omap_early_serial_init(void) +{ + omap_cfg_reg(UART1_TX); + omap_cfg_reg(UART1_RTS); + + omap_cfg_reg(UART2_TX); + omap_cfg_reg(UART2_RTS); + + omap_cfg_reg(UART3_TX); + omap_cfg_reg(UART3_RX); +} + +static void __init omap_generic_init(void) +{ + /* + * Make sure the serial ports are muxed on at this point. + * You have to mux them off in device drivers later on + * if not needed. + */ + if (cpu_is_omap1510()) { + omap_early_serial_init(); + } +} + +static void __init omap_generic_map_io(void) +{ + omap_map_io(); +} + +MACHINE_START(OMAP_GENERIC, "Generic OMAP-1510/1610") + MAINTAINER("Tony Lindgren <tony@atomide.com>") + BOOT_MEM(0x10000000, 0xe0000000, 0xe0000000) + BOOT_PARAMS(0x10000100) + MAPIO(omap_generic_map_io) + INITIRQ(omap_generic_init_irq) + INIT_MACHINE(omap_generic_init) +MACHINE_END diff --git a/arch/arm/mach-omap/board-innovator.c b/arch/arm/mach-omap/board-innovator.c new file mode 100644 index 000000000000..ad32ad655829 --- /dev/null +++ b/arch/arm/mach-omap/board-innovator.c @@ -0,0 +1,157 @@ +/* + * linux/arch/arm/mach-omap/board-innovator.c + * + * Board specific inits for OMAP-1510 and OMAP-1610 Innovator + * + * Copyright (C) 2001 RidgeRun, Inc. + * Author: Greg Lonnon <glonnon@ridgerun.com> + * + * Copyright (C) 2002 MontaVista Software, Inc. + * + * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6 + * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/device.h> + +#include <asm/hardware.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include <asm/arch/clocks.h> +#include <asm/arch/gpio.h> +#include <asm/arch/fpga.h> + +#include "common.h" + +#ifdef CONFIG_ARCH_OMAP1510 + +extern int omap_gpio_init(void); + +/* Only FPGA needs to be mapped here. All others are done with ioremap */ +static struct map_desc innovator1510_io_desc[] __initdata = { +{ OMAP1510P1_FPGA_BASE, OMAP1510P1_FPGA_START, OMAP1510P1_FPGA_SIZE, + MT_DEVICE }, +}; + +static struct resource innovator1510_smc91x_resources[] = { + [0] = { + .start = OMAP1510P1_FPGA_ETHR_START, /* Physical */ + .end = OMAP1510P1_FPGA_ETHR_START + 16, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = INT_ETHER, + .end = INT_ETHER, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device innovator1510_smc91x_device = { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(innovator1510_smc91x_resources), + .resource = innovator1510_smc91x_resources, +}; + +static struct platform_device *innovator1510_devices[] __initdata = { + &innovator1510_smc91x_device, +}; + +#endif /* CONFIG_ARCH_OMAP1510 */ + +#ifdef CONFIG_ARCH_OMAP1610 + +static struct map_desc innovator1610_io_desc[] __initdata = { +{ OMAP1610_ETHR_BASE, OMAP1610_ETHR_START, OMAP1610_ETHR_SIZE,MT_DEVICE }, +{ OMAP1610_NOR_FLASH_BASE, OMAP1610_NOR_FLASH_START, OMAP1610_NOR_FLASH_SIZE, + MT_DEVICE }, +}; + +static struct resource innovator1610_smc91x_resources[] = { + [0] = { + .start = OMAP1610_ETHR_START, /* Physical */ + .end = OMAP1610_ETHR_START + SZ_4K, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 0, /* Really GPIO 0 */ + .end = 0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device innovator1610_smc91x_device = { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(innovator1610_smc91x_resources), + .resource = innovator1610_smc91x_resources, +}; + +static struct platform_device *innovator1610_devices[] __initdata = { + &innovator1610_smc91x_device, +}; + +#endif /* CONFIG_ARCH_OMAP1610 */ + +void innovator_init_irq(void) +{ + omap_init_irq(); +#ifdef CONFIG_ARCH_OMAP1510 + if (cpu_is_omap1510()) { + omap_gpio_init(); + fpga_init_irq(); + } +#endif +} + +static void __init innovator_init(void) +{ +#ifdef CONFIG_ARCH_OMAP1510 + if (cpu_is_omap1510()) { + platform_add_devices(innovator1510_devices, ARRAY_SIZE(innovator1510_devices)); + } +#endif +#ifdef CONFIG_ARCH_OMAP1610 + if (cpu_is_omap1610()) { + platform_add_devices(innovator1610_devices, ARRAY_SIZE(innovator1610_devices)); + } +#endif +} + +static void __init innovator_map_io(void) +{ + omap_map_io(); + +#ifdef CONFIG_ARCH_OMAP1510 + if (cpu_is_omap1510()) { + iotable_init(innovator1510_io_desc, ARRAY_SIZE(innovator1510_io_desc)); + + /* Dump the Innovator FPGA rev early - useful info for support. */ + printk("Innovator FPGA Rev %d.%d Board Rev %d\n", + fpga_read(OMAP1510P1_FPGA_REV_HIGH), + fpga_read(OMAP1510P1_FPGA_REV_LOW), + fpga_read(OMAP1510P1_FPGA_BOARD_REV)); + } +#endif +#ifdef CONFIG_ARCH_OMAP1610 + if (cpu_is_omap1610()) { + iotable_init(innovator1610_io_desc, ARRAY_SIZE(innovator1610_io_desc)); + } +#endif +} + +MACHINE_START(OMAP_INNOVATOR, "TI-Innovator") + MAINTAINER("MontaVista Software, Inc.") + BOOT_MEM(0x10000000, 0xe0000000, 0xe0000000) + BOOT_PARAMS(0x10000100) + MAPIO(innovator_map_io) + INITIRQ(innovator_init_irq) + INIT_MACHINE(innovator_init) +MACHINE_END diff --git a/arch/arm/mach-omap/board-osk.c b/arch/arm/mach-omap/board-osk.c new file mode 100644 index 000000000000..1dfa06e41995 --- /dev/null +++ b/arch/arm/mach-omap/board-osk.c @@ -0,0 +1,97 @@ +/* + * linux/arch/arm/mach-omap/board-osk.c + * + * Board specific init for OMAP5912 OSK + * + * Written by Dirk Behme <dirk.behme@de.bosch.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/device.h> + +#include <asm/hardware.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include <asm/arch/clocks.h> +#include <asm/arch/gpio.h> +#include <asm/arch/fpga.h> + +#include "common.h" + +static struct map_desc osk5912_io_desc[] __initdata = { +{ OMAP_OSK_ETHR_BASE, OMAP_OSK_ETHR_START, OMAP_OSK_ETHR_SIZE,MT_DEVICE }, +{ OMAP_OSK_NOR_FLASH_BASE, OMAP_OSK_NOR_FLASH_START, OMAP_OSK_NOR_FLASH_SIZE, + MT_DEVICE }, +}; + +static struct resource osk5912_smc91x_resources[] = { + [0] = { + .start = OMAP_OSK_ETHR_START, /* Physical */ + .end = OMAP_OSK_ETHR_START + SZ_4K, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 0, /* Really GPIO 0 */ + .end = 0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device osk5912_smc91x_device = { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(osk5912_smc91x_resources), + .resource = osk5912_smc91x_resources, +}; + +static struct platform_device *osk5912_devices[] __initdata = { + &osk5912_smc91x_device, +}; + +void osk_init_irq(void) +{ + omap_init_irq(); +} + +static void __init osk_init(void) +{ + platform_add_devices(osk5912_devices, ARRAY_SIZE(osk5912_devices)); +} + +static void __init osk_map_io(void) +{ + omap_map_io(); + iotable_init(osk5912_io_desc, ARRAY_SIZE(osk5912_io_desc)); + +} + +MACHINE_START(OMAP_OSK, "TI-OSK") + MAINTAINER("Dirk Behme <dirk.behme@de.bosch.com>") + BOOT_MEM(0x10000000, 0xe0000000, 0xe0000000) + BOOT_PARAMS(0x10000100) + MAPIO(osk_map_io) + INITIRQ(osk_init_irq) + INIT_MACHINE(osk_init) +MACHINE_END diff --git a/arch/arm/mach-omap/board-perseus2.c b/arch/arm/mach-omap/board-perseus2.c new file mode 100644 index 000000000000..5f38ed9ff80d --- /dev/null +++ b/arch/arm/mach-omap/board-perseus2.c @@ -0,0 +1,111 @@ +/* + * linux/arch/arm/mach-omap/board-perseus2.c + * + * Modified from board-generic.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/device.h> + +#include <asm/hardware.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include <asm/arch/clocks.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mux.h> + +#include "common.h" + +void omap_perseus2_init_irq(void) +{ + omap_init_irq(); +} + +static struct resource smc91x_resources[] = { + [0] = { + .start = OMAP730_FPGA_ETHR_START, /* Physical */ + .end = OMAP730_FPGA_ETHR_START + SZ_4K, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 0, + .end = 0, + .flags = INT_ETHER, + }, +}; + +static struct platform_device smc91x_device = { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, +}; + +static struct platform_device *devices[] __initdata = { + &smc91x_device, +}; + +static void __init omap_perseus2_init(void) +{ + (void) platform_add_devices(devices, ARRAY_SIZE(devices)); +} + +/* Only FPGA needs to be mapped here. All others are done with ioremap */ +static struct map_desc omap_perseus2_io_desc[] __initdata = { + {OMAP730_FPGA_BASE, OMAP730_FPGA_START, OMAP730_FPGA_SIZE, + MT_DEVICE}, +}; + +static void __init omap_perseus2_map_io(void) +{ + omap_map_io(); + iotable_init(omap_perseus2_io_desc, + ARRAY_SIZE(omap_perseus2_io_desc)); + + /* Early, board-dependent init */ + + /* + * Hold GSM Reset until needed + */ + omap_writew(omap_readw(OMAP730_DSP_M_CTL) & ~1, OMAP730_DSP_M_CTL); + + /* + * UARTs -> done automagically by 8250 driver + */ + + /* + * CSx timings, GPIO Mux ... setup + */ + + /* Flash: CS0 timings setup */ + omap_writel(0x0000fff3, OMAP730_FLASH_CFG_0); + omap_writel(0x00000088, OMAP730_FLASH_ACFG_0); + + /* + * Ethernet support trough the debug board + * CS1 timings setup + */ + omap_writel(0x0000fff3, OMAP730_FLASH_CFG_1); + omap_writel(0x00000000, OMAP730_FLASH_ACFG_1); + + /* + * Configure MPU_EXT_NIRQ IO in IO_CONF9 register, + * It is used as the Ethernet controller interrupt + */ + omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFFFFFF, OMAP730_IO_CONF_9); +} + +MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2") + MAINTAINER("Kevin Hilman <k-hilman@ti.com>") + BOOT_MEM(0x10000000, 0xe0000000, 0xe0000000) + BOOT_PARAMS(0x10000100) + MAPIO(omap_perseus2_map_io) + INITIRQ(omap_perseus2_init_irq) + INIT_MACHINE(omap_perseus2_init) +MACHINE_END diff --git a/arch/arm/mach-omap/bus.c b/arch/arm/mach-omap/bus.c index 23a44f6d0b39..2ad402d0df27 100644 --- a/arch/arm/mach-omap/bus.c +++ b/arch/arm/mach-omap/bus.c @@ -93,6 +93,8 @@ static struct bus_type omap_bus_types[OMAP_NR_BUSES] = { */ inline int dmadev_uses_omap_lbus(struct device * dev) { + if (dev == NULL || !cpu_is_omap1510()) + return 0; return dev->bus == &omap_bus_types[OMAP_BUS_LBUS] ? 1 : 0; } @@ -184,6 +186,9 @@ int omap_device_register(struct omap_dev *odev) if (odev->dma_mask) odev->dev.dma_mask = odev->dma_mask; + if (odev->coherent_dma_mask) + odev->dev.coherent_dma_mask = odev->coherent_dma_mask; + snprintf(odev->dev.bus_id, BUS_ID_SIZE, "%s%u", odev->name, odev->devid); diff --git a/arch/arm/mach-omap/clocks.c b/arch/arm/mach-omap/clocks.c index 8fd36a4a592b..382baee256ad 100644 --- a/arch/arm/mach-omap/clocks.c +++ b/arch/arm/mach-omap/clocks.c @@ -34,6 +34,7 @@ #include <asm/errno.h> #include <asm/io.h> #include <asm/arch/clocks.h> +#include <asm/arch/board.h> /* Input clock in MHz */ static unsigned int source_clock = 12; @@ -49,10 +50,10 @@ typedef struct { char *name; __u8 flags; ck_t parent; - volatile __u16 *rate_reg; /* Clock rate register */ - volatile __u16 *enbl_reg; /* Enable register */ - volatile __u16 *idle_reg; /* Idle register */ - volatile __u16 *slct_reg; /* Select register */ + unsigned long rate_reg; /* Clock rate register */ + unsigned long enbl_reg; /* Enable register */ + unsigned long idle_reg; /* Idle register */ + unsigned long slct_reg; /* Select register */ __s8 rate_shift; /* Clock rate bit shift */ __s8 enbl_shift; /* Clock enable bit shift */ __s8 idle_shift; /* Clock idle bit shift */ @@ -245,7 +246,7 @@ int ck_set_input(ck_t ck, ck_t input) { int ret = 0, shift; - volatile __u16 *reg; + unsigned short reg; unsigned long flags; if (!CK_IN_RANGE(ck) || !CK_CAN_SWITCH(ck)) { @@ -253,15 +254,17 @@ ck_set_input(ck_t ck, ck_t input) goto exit; } - reg = CK_SELECT_REG(ck); + reg = omap_readw(CK_SELECT_REG(ck)); shift = CK_SELECT_SHIFT(ck); spin_lock_irqsave(&clock_lock, flags); if (input == OMAP_CLKIN) { - *((volatile __u16 *) reg) &= ~(1 << shift); + reg &= ~(1 << shift); + omap_writew(reg, CK_SELECT_REG(ck)); goto exit; } else if (input == CK_PARENT(ck)) { - *((volatile __u16 *) reg) |= (1 << shift); + reg |= (1 << shift); + omap_writew(reg, CK_SELECT_REG(ck)); goto exit; } @@ -285,11 +288,11 @@ ck_get_input(ck_t ck, ck_t * input) spin_lock_irqsave(&clock_lock, flags); if (CK_CAN_SWITCH(ck)) { int shift; - volatile __u16 *reg; + unsigned short reg; - reg = CK_SELECT_REG(ck); + reg = omap_readw(CK_SELECT_REG(ck)); shift = CK_SELECT_SHIFT(ck); - if (*reg & (1 << shift)) { + if (reg & (1 << shift)) { *input = CK_PARENT(ck); goto exit; } @@ -305,7 +308,7 @@ ck_get_input(ck_t ck, ck_t * input) static int __ck_set_pll_rate(ck_t ck, int rate) { - volatile __u16 *pll; + unsigned short pll; unsigned long flags; if ((rate < 0) || (rate > CK_MAX_PLL_FREQ)) @@ -322,13 +325,16 @@ __ck_set_pll_rate(ck_t ck, int rate) } spin_lock_irqsave(&clock_lock, flags); - pll = (volatile __u16 *) CK_RATE_REG(ck); + pll = omap_readw(CK_RATE_REG(ck)); /* Clear the rate bits */ - *pll &= ~(0x1f << 5); + pll &= ~(0x1f << 5); /* Set the rate bits */ - *pll |= (ck_lookup_table[rate - 1] << 5); + pll |= (ck_lookup_table[rate - 1] << 5); + + omap_writew(pll, CK_RATE_REG(ck)); + spin_unlock_irqrestore(&clock_lock, flags); return 0; @@ -338,7 +344,7 @@ static int __ck_set_clkm_rate(ck_t ck, int rate) { int shift, prate, div, ret; - volatile __u16 *reg; + unsigned short reg; unsigned long flags; spin_lock_irqsave(&clock_lock, flags); @@ -390,10 +396,11 @@ __ck_set_clkm_rate(ck_t ck, int rate) * At last, we can set the divisor. Clear the old rate bits and * set the new ones. */ - reg = (volatile __u16 *) CK_RATE_REG(ck); + reg = omap_readw(CK_RATE_REG(ck)); shift = CK_RATE_SHIFT(ck); - *reg &= ~(3 << shift); - *reg |= (div << shift); + reg &= ~(3 << shift); + reg |= (div << shift); + omap_writew(reg, CK_RATE_REG(ck)); /* And return the new (actual, after rounding down) rate. */ ret = prate; @@ -432,7 +439,7 @@ __ck_get_pll_rate(ck_t ck) { int m, d; - __u16 pll = *((volatile __u16 *) CK_RATE_REG(ck)); + unsigned short pll = omap_readw(CK_RATE_REG(ck)); m = (pll & (0x1f << 7)) >> 7; m = m ? m : 1; @@ -448,7 +455,7 @@ __ck_get_clkm_rate(ck_t ck) static int bits2div[] = { 1, 2, 4, 8 }; int in, bits, reg, shift; - reg = *(CK_RATE_REG(ck)); + reg = omap_readw(CK_RATE_REG(ck)); shift = CK_RATE_SHIFT(ck); in = ck_get_rate(CK_PARENT(ck)); @@ -520,7 +527,7 @@ ck_get_rate(ck_t ck) int ck_enable(ck_t ck) { - volatile __u16 *reg; + unsigned short reg; int ret = -EINVAL, shift; unsigned long flags; @@ -537,9 +544,10 @@ ck_enable(ck_t ck) goto exit; spin_lock_irqsave(&clock_lock, flags); - reg = CK_ENABLE_REG(ck); + reg = omap_readw(CK_ENABLE_REG(ck)); shift = CK_ENABLE_SHIFT(ck); - *reg |= (1 << shift); + reg |= (1 << shift); + omap_writew(reg, CK_ENABLE_REG(ck)); spin_unlock_irqrestore(&clock_lock, flags); exit: @@ -549,7 +557,7 @@ ck_enable(ck_t ck) int ck_disable(ck_t ck) { - volatile __u16 *reg; + unsigned short reg; int ret = -EINVAL, shift; unsigned long flags; @@ -568,9 +576,10 @@ ck_disable(ck_t ck) return -EINVAL; spin_lock_irqsave(&clock_lock, flags); - reg = CK_ENABLE_REG(ck); + reg = omap_readw(CK_ENABLE_REG(ck)); shift = CK_ENABLE_SHIFT(ck); - *reg &= ~(1 << shift); + reg &= ~(1 << shift); + omap_writew(reg, CK_ENABLE_REG(ck)); spin_unlock_irqrestore(&clock_lock, flags); exit: @@ -606,54 +615,71 @@ __ck_make_lookup_table(void) int __init init_ck(void) { + const struct omap_clock_info *info; + int crystal_type = 0; /* Default 12 MHz */ + __ck_make_lookup_table(); + info = omap_get_per_info(OMAP_TAG_CLOCK, struct omap_clock_info); + if (info != NULL) { + if (!cpu_is_omap1510()) + crystal_type = info->system_clock_type; + } /* We want to be in syncronous scalable mode */ - *ARM_SYSST = 0x1000; + omap_writew(0x1000, ARM_SYSST); #if defined(CONFIG_OMAP_ARM_30MHZ) - *ARM_CKCTL = 0x1555; - *DPLL_CTL_REG = 0x2290; + omap_writew(0x1555, ARM_CKCTL); + omap_writew(0x2290, DPLL_CTL_REG); #elif defined(CONFIG_OMAP_ARM_60MHZ) - *ARM_CKCTL = 0x1005; - *DPLL_CTL_REG = 0x2290; + omap_writew(0x1005, ARM_CKCTL); + omap_writew(0x2290, DPLL_CTL_REG); #elif defined(CONFIG_OMAP_ARM_96MHZ) - *ARM_CKCTL = 0x1005; - *DPLL_CTL_REG = 0x2410; + omap_writew(0x1005, ARM_CKCTL); + omap_writew(0x2410, DPLL_CTL_REG); #elif defined(CONFIG_OMAP_ARM_120MHZ) - *ARM_CKCTL = 0x110a; - *DPLL_CTL_REG = 0x2510; + omap_writew(0x110a, ARM_CKCTL); + omap_writew(0x2510, DPLL_CTL_REG); #elif defined(CONFIG_OMAP_ARM_168MHZ) - *ARM_CKCTL = 0x110f; - *DPLL_CTL_REG = 0x2710; + omap_writew(0x110f, ARM_CKCTL); + omap_writew(0x2710, DPLL_CTL_REG); #elif defined(CONFIG_OMAP_ARM_182MHZ) && defined(CONFIG_ARCH_OMAP730) - *ARM_CKCTL = 0x250E; - *DPLL_CTL_REG = 0x2713; -#elif defined(CONFIG_OMAP_ARM_192MHZ) && defined(CONFIG_ARCH_OMAP1610) - *ARM_CKCTL = 0x110f; + omap_writew(0x250E, ARM_CKCTL); + omap_writew(0x2710, DPLL_CTL_REG); +#elif defined(CONFIG_OMAP_ARM_192MHZ) && (defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP5912)) + omap_writew(0x150f, ARM_CKCTL); if (crystal_type == 2) { source_clock = 13; /* MHz */ - *DPLL_CTL_REG = 0x2510; + omap_writew(0x2510, DPLL_CTL_REG); } else - *DPLL_CTL_REG = 0x2810; + omap_writew(0x2810, DPLL_CTL_REG); #elif defined(CONFIG_OMAP_ARM_195MHZ) && defined(CONFIG_ARCH_OMAP730) - *ARM_CKCTL = 0x250E; - *DPLL_CTL_REG = 0x2793; + omap_writew(0x250E, ARM_CKCTL); + omap_writew(0x2790, DPLL_CTL_REG); #else #error "OMAP MHZ not set, please run make xconfig" #endif +#ifdef CONFIG_MACH_OMAP_PERSEUS2 + /* Select slicer output as OMAP input clock */ + omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL_REG) & ~0x1, OMAP730_PCC_UPLD_CTRL_REG); +#endif + /* Turn off some other junk the bootloader might have turned on */ - *ARM_CKCTL &= 0x0fff; /* Turn off DSP, ARM_INTHCK, ARM_TIMXO */ - *ARM_RSTCT1 = 0; /* Put DSP/MPUI into reset until needed */ - *ARM_RSTCT2 = 1; - *ARM_IDLECT1 = 0x400; + + /* Turn off DSP, ARM_INTHCK, ARM_TIMXO */ + omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); + + /* Put DSP/MPUI into reset until needed */ + omap_writew(0, ARM_RSTCT1); + omap_writew(1, ARM_RSTCT2); + omap_writew(0x400, ARM_IDLECT1); /* * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8) * of the ARM_IDLECT2 register must be set to zero. The power-on * default value of this bit is one. */ - *ARM_IDLECT2 = 0x0000; /* Turn LCD clock off also */ + omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */ /* * Only enable those clocks we will need, let the drivers diff --git a/arch/arm/mach-omap/common.c b/arch/arm/mach-omap/common.c index 117927fa42a2..2ff74d1a4eef 100644 --- a/arch/arm/mach-omap/common.c +++ b/arch/arm/mach-omap/common.c @@ -13,29 +13,60 @@ #include <linux/init.h> #include <linux/delay.h> #include <linux/pm.h> +#include <linux/console.h> #include <asm/hardware.h> #include <asm/system.h> #include <asm/pgtable.h> #include <asm/mach/map.h> #include <asm/arch/clocks.h> +#include <asm/arch/board.h> #include <asm/io.h> -#include "common.h" - /* - * Common OMAP I/O mapping + * ---------------------------------------------------------------------------- + * OMAP I/O mapping * * The machine specific code may provide the extra mapping besides the * default mapping provided here. + * ---------------------------------------------------------------------------- */ -static struct map_desc standard_io_desc[] __initdata = { - { IO_BASE, IO_START, IO_SIZE, MT_DEVICE }, - { OMAP_DSP_BASE, OMAP_DSP_START, OMAP_DSP_SIZE, MT_DEVICE }, - { OMAP_DSPREG_BASE, OMAP_DSPREG_START, OMAP_DSPREG_SIZE, MT_DEVICE }, - { OMAP_SRAM_BASE, OMAP_SRAM_START, OMAP_SRAM_SIZE, MT_DEVICE } +static struct map_desc omap_io_desc[] __initdata = { + { IO_VIRT, IO_PHYS, IO_SIZE, MT_DEVICE }, +}; + +#ifdef CONFIG_ARCH_OMAP730 +static struct map_desc omap730_io_desc[] __initdata = { + { OMAP730_DSP_BASE, OMAP730_DSP_START, OMAP730_DSP_SIZE, MT_DEVICE }, + { OMAP730_DSPREG_BASE, OMAP730_DSPREG_START, OMAP730_DSPREG_SIZE, MT_DEVICE }, + { OMAP730_SRAM_BASE, OMAP730_SRAM_START, OMAP730_SRAM_SIZE, MT_DEVICE } }; +#endif + +#ifdef CONFIG_ARCH_OMAP1510 +static struct map_desc omap1510_io_desc[] __initdata = { + { OMAP1510_DSP_BASE, OMAP1510_DSP_START, OMAP1510_DSP_SIZE, MT_DEVICE }, + { OMAP1510_DSPREG_BASE, OMAP1510_DSPREG_START, OMAP1510_DSPREG_SIZE, MT_DEVICE }, + { OMAP1510_SRAM_BASE, OMAP1510_SRAM_START, OMAP1510_SRAM_SIZE, MT_DEVICE } +}; +#endif + +#ifdef CONFIG_ARCH_OMAP1610 +static struct map_desc omap1610_io_desc[] __initdata = { + { OMAP1610_DSP_BASE, OMAP1610_DSP_START, OMAP1610_DSP_SIZE, MT_DEVICE }, + { OMAP1610_DSPREG_BASE, OMAP1610_DSPREG_START, OMAP1610_DSPREG_SIZE, MT_DEVICE }, + { OMAP1610_SRAM_BASE, OMAP1610_SRAM_START, OMAP1610_SRAM_SIZE, MT_DEVICE } +}; +#endif + +#ifdef CONFIG_ARCH_OMAP5912 +static struct map_desc omap5912_io_desc[] __initdata = { + { OMAP5912_DSP_BASE, OMAP5912_DSP_START, OMAP5912_DSP_SIZE, MT_DEVICE }, + { OMAP5912_DSPREG_BASE, OMAP5912_DSPREG_START, OMAP5912_DSPREG_SIZE, MT_DEVICE }, + { OMAP5912_SRAM_BASE, OMAP5912_SRAM_START, OMAP5912_SRAM_SIZE, MT_DEVICE } +}; +#endif static int initialized = 0; @@ -43,13 +74,36 @@ static void __init _omap_map_io(void) { initialized = 1; - iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); + /* We have to initialize the IO space mapping before we can run + * cpu_is_omapxxx() macros. */ + iotable_init(omap_io_desc, ARRAY_SIZE(omap_io_desc)); + +#ifdef CONFIG_ARCH_OMAP730 + if (cpu_is_omap730()) { + iotable_init(omap730_io_desc, ARRAY_SIZE(omap730_io_desc)); + } +#endif +#ifdef CONFIG_ARCH_OMAP1510 + if (cpu_is_omap1510()) { + iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc)); + } +#endif +#ifdef CONFIG_ARCH_OMAP1610 + if (cpu_is_omap1610()) { + iotable_init(omap1610_io_desc, ARRAY_SIZE(omap1610_io_desc)); + } +#endif +#ifdef CONFIG_ARCH_OMAP5912 + if (cpu_is_omap5912()) { + iotable_init(omap5912_io_desc, ARRAY_SIZE(omap5912_io_desc)); + } +#endif /* REVISIT: Refer to OMAP5910 Errata, Advisory SYS_1: "Timeout Abort * on a Posted Write in the TIPB Bridge". */ - __raw_writew(0x0, MPU_PUBLIC_TIPB_CNTL_REG); - __raw_writew(0x0, MPU_PRIVATE_TIPB_CNTL_REG); + omap_writew(0x0, MPU_PUBLIC_TIPB_CNTL_REG); + omap_writew(0x0, MPU_PRIVATE_TIPB_CNTL_REG); /* Must init clocks early to assure that timer interrupt works */ @@ -65,5 +119,55 @@ void omap_map_io(void) _omap_map_io(); } -EXPORT_SYMBOL(omap_map_io); +extern int omap_bootloader_tag_len; +extern u8 omap_bootloader_tag[]; +const void *__omap_get_per_info(u16 tag, size_t len) +{ + struct omap_board_info_entry *info = NULL; + +#ifdef CONFIG_OMAP_BOOT_TAG + if (omap_bootloader_tag_len > 4) + info = (struct omap_board_info_entry *) omap_bootloader_tag; + while (info != NULL) { + u8 *next; + + if (info->tag == tag) + break; + + next = (u8 *) info + sizeof(*info) + info->len; + if (next >= omap_bootloader_tag + omap_bootloader_tag_len) + info = NULL; + else + info = (struct omap_board_info_entry *) next; + } +#endif + if (info == NULL) + return NULL; + if (info->len != len) { + printk(KERN_ERR "OMAP per_info: Length mismatch with tag %x (want %d, got %d)\n", + tag, len, info->len); + return NULL; + } + + return info->data; +} +EXPORT_SYMBOL(__omap_get_per_info); + +static int __init omap_add_serial_console(void) +{ + const struct omap_uart_info *info; + + info = omap_get_per_info(OMAP_TAG_UART, struct omap_uart_info); + if (info != NULL && info->console_uart) { + static char speed[11], *opt = NULL; + + if (info->console_speed) { + snprintf(speed, sizeof(speed), "%u", info->console_speed); + opt = speed; + } + return add_preferred_console("ttyS", info->console_uart - 1, opt); + } + return 0; +} +console_initcall(omap_add_serial_console); diff --git a/arch/arm/mach-omap/common.h b/arch/arm/mach-omap/common.h index b45d6cff7189..1cc559dd2f81 100644 --- a/arch/arm/mach-omap/common.h +++ b/arch/arm/mach-omap/common.h @@ -1,6 +1,34 @@ /* * linux/arch/arm/mach-omap/common.h + * + * Header for code common to all OMAP machines. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. */ +#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H +#define __ARCH_ARM_MACH_OMAP_COMMON_H + extern void omap_map_io(void); +#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ + + diff --git a/arch/arm/mach-omap/dma.c b/arch/arm/mach-omap/dma.c index 17c9ee3d7533..2c78324581a0 100644 --- a/arch/arm/mach-omap/dma.c +++ b/arch/arm/mach-omap/dma.c @@ -61,7 +61,7 @@ static inline int get_gdma_dev(int req) u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4; int shift = ((req - 1) % 5) * 6; - return ((__raw_readl(reg) >> shift) & 0x3f) + 1; + return ((omap_readl(reg) >> shift) & 0x3f) + 1; } static inline void set_gdma_dev(int req, int dev) @@ -70,10 +70,10 @@ static inline void set_gdma_dev(int req, int dev) int shift = ((req - 1) % 5) * 6; u32 l; - l = __raw_readl(reg); + l = omap_readl(reg); l &= ~(0x3f << shift); l |= (dev - 1) << shift; - __raw_writel(l, reg); + omap_writel(l, reg); } static void clear_lch_regs(int lch) @@ -82,7 +82,7 @@ static void clear_lch_regs(int lch) u32 lch_base = OMAP_DMA_BASE + lch * 0x40; for (i = 0; i < 0x2c; i += 2) - __raw_writew(0, lch_base + i); + omap_writew(0, lch_base + i); } void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, @@ -90,25 +90,25 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, { u16 w; - w = __raw_readw(OMAP_DMA_CSDP_REG(lch)); + w = omap_readw(OMAP_DMA_CSDP_REG(lch)); w &= ~0x03; w |= data_type; - __raw_writew(w, OMAP_DMA_CSDP_REG(lch)); + omap_writew(w, OMAP_DMA_CSDP_REG(lch)); - w = __raw_readw(OMAP_DMA_CCR_REG(lch)); + w = omap_readw(OMAP_DMA_CCR_REG(lch)); w &= ~(1 << 5); if (sync_mode == OMAP_DMA_SYNC_FRAME) w |= 1 << 5; - __raw_writew(w, OMAP_DMA_CCR_REG(lch)); + omap_writew(w, OMAP_DMA_CCR_REG(lch)); - w = __raw_readw(OMAP_DMA_CCR2_REG(lch)); + w = omap_readw(OMAP_DMA_CCR2_REG(lch)); w &= ~(1 << 2); if (sync_mode == OMAP_DMA_SYNC_BLOCK) w |= 1 << 2; - __raw_writew(w, OMAP_DMA_CCR2_REG(lch)); + omap_writew(w, OMAP_DMA_CCR2_REG(lch)); - __raw_writew(elem_count, OMAP_DMA_CEN_REG(lch)); - __raw_writew(frame_count, OMAP_DMA_CFN_REG(lch)); + omap_writew(elem_count, OMAP_DMA_CEN_REG(lch)); + omap_writew(frame_count, OMAP_DMA_CFN_REG(lch)); } @@ -117,18 +117,18 @@ void omap_set_dma_src_params(int lch, int src_port, int src_amode, { u16 w; - w = __raw_readw(OMAP_DMA_CSDP_REG(lch)); + w = omap_readw(OMAP_DMA_CSDP_REG(lch)); w &= ~(0x1f << 2); w |= src_port << 2; - __raw_writew(w, OMAP_DMA_CSDP_REG(lch)); + omap_writew(w, OMAP_DMA_CSDP_REG(lch)); - w = __raw_readw(OMAP_DMA_CCR_REG(lch)); + w = omap_readw(OMAP_DMA_CCR_REG(lch)); w &= ~(0x03 << 12); w |= src_amode << 12; - __raw_writew(w, OMAP_DMA_CCR_REG(lch)); + omap_writew(w, OMAP_DMA_CCR_REG(lch)); - __raw_writew(src_start >> 16, OMAP_DMA_CSSA_U_REG(lch)); - __raw_writew(src_start, OMAP_DMA_CSSA_L_REG(lch)); + omap_writew(src_start >> 16, OMAP_DMA_CSSA_U_REG(lch)); + omap_writew(src_start, OMAP_DMA_CSSA_L_REG(lch)); } void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, @@ -136,18 +136,18 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, { u16 w; - w = __raw_readw(OMAP_DMA_CSDP_REG(lch)); + w = omap_readw(OMAP_DMA_CSDP_REG(lch)); w &= ~(0x1f << 9); w |= dest_port << 9; - __raw_writew(w, OMAP_DMA_CSDP_REG(lch)); + omap_writew(w, OMAP_DMA_CSDP_REG(lch)); - w = __raw_readw(OMAP_DMA_CCR_REG(lch)); + w = omap_readw(OMAP_DMA_CCR_REG(lch)); w &= ~(0x03 << 14); w |= dest_amode << 14; - __raw_writew(w, OMAP_DMA_CCR_REG(lch)); + omap_writew(w, OMAP_DMA_CCR_REG(lch)); - __raw_writew(dest_start >> 16, OMAP_DMA_CDSA_U_REG(lch)); - __raw_writew(dest_start, OMAP_DMA_CDSA_L_REG(lch)); + omap_writew(dest_start >> 16, OMAP_DMA_CDSA_U_REG(lch)); + omap_writew(dest_start, OMAP_DMA_CDSA_L_REG(lch)); } void omap_start_dma(int lch) @@ -155,13 +155,13 @@ void omap_start_dma(int lch) u16 w; /* Read CSR to make sure it's cleared. */ - w = __raw_readw(OMAP_DMA_CSR_REG(lch)); + w = omap_readw(OMAP_DMA_CSR_REG(lch)); /* Enable some nice interrupts. */ - __raw_writew(dma_chan[lch].enabled_irqs, OMAP_DMA_CICR_REG(lch)); + omap_writew(dma_chan[lch].enabled_irqs, OMAP_DMA_CICR_REG(lch)); - w = __raw_readw(OMAP_DMA_CCR_REG(lch)); + w = omap_readw(OMAP_DMA_CCR_REG(lch)); w |= OMAP_DMA_CCR_EN; - __raw_writew(w, OMAP_DMA_CCR_REG(lch)); + omap_writew(w, OMAP_DMA_CCR_REG(lch)); dma_chan[lch].flags |= OMAP_DMA_ACTIVE; } @@ -170,11 +170,11 @@ void omap_stop_dma(int lch) u16 w; /* Disable all interrupts on the channel */ - __raw_writew(0, OMAP_DMA_CICR_REG(lch)); + omap_writew(0, OMAP_DMA_CICR_REG(lch)); - w = __raw_readw(OMAP_DMA_CCR_REG(lch)); + w = omap_readw(OMAP_DMA_CCR_REG(lch)); w &= ~OMAP_DMA_CCR_EN; - __raw_writew(w, OMAP_DMA_CCR_REG(lch)); + omap_writew(w, OMAP_DMA_CCR_REG(lch)); dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; } @@ -196,7 +196,7 @@ static int dma_handle_ch(int ch) csr = dma_chan[ch].saved_csr; dma_chan[ch].saved_csr = 0; } else - csr = __raw_readw(OMAP_DMA_CSR_REG(ch)); + csr = omap_readw(OMAP_DMA_CSR_REG(ch)); if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) { dma_chan[ch + 6].saved_csr = csr >> 7; csr &= 0x7f; @@ -274,7 +274,7 @@ int omap_request_dma(int dev_id, const char *dev_name, chan->data = data; chan->enabled_irqs = OMAP_DMA_TOUT_IRQ | OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ; - if (cpu_is_omap1610()) { + if (cpu_is_omap1610() || cpu_is_omap5912()) { /* If the sync device is set, configure it dynamically. */ if (dev_id != 0) { set_gdma_dev(free_ch + 1, dev_id); @@ -282,9 +282,9 @@ int omap_request_dma(int dev_id, const char *dev_name, } /* Disable the 1510 compatibility mode and set the sync device * id. */ - __raw_writew(dev_id | (1 << 10), OMAP_DMA_CCR_REG(free_ch)); + omap_writew(dev_id | (1 << 10), OMAP_DMA_CCR_REG(free_ch)); } else { - __raw_writew(dev_id, OMAP_DMA_CCR_REG(free_ch)); + omap_writew(dev_id, OMAP_DMA_CCR_REG(free_ch)); } *dma_ch_out = free_ch; @@ -305,9 +305,9 @@ void omap_free_dma(int ch) spin_unlock_irqrestore(&dma_chan_lock, flags); /* Disable all DMA interrupts for the channel. */ - __raw_writew(0, OMAP_DMA_CICR_REG(ch)); + omap_writew(0, OMAP_DMA_CICR_REG(ch)); /* Make sure the DMA transfer is stopped. */ - __raw_writew(0, OMAP_DMA_CCR_REG(ch)); + omap_writew(0, OMAP_DMA_CCR_REG(ch)); } int omap_dma_in_1510_mode(void) @@ -381,45 +381,45 @@ static void set_b1_regs(void) } if (omap_dma_in_1510_mode()) { - __raw_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U); - __raw_writew(top, OMAP1510_DMA_LCD_TOP_F1_L); - __raw_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U); - __raw_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L); + omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U); + omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L); + omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U); + omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L); return; } /* 1610 regs */ - __raw_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U); - __raw_writew(top, OMAP1610_DMA_LCD_TOP_B1_L); - __raw_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U); - __raw_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L); + omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U); + omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L); + omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U); + omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L); - __raw_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1); - __raw_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1); + omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1); + omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1); - w = __raw_readw(OMAP1610_DMA_LCD_CSDP); + w = omap_readw(OMAP1610_DMA_LCD_CSDP); w &= ~0x03; w |= lcd_dma.data_type; - __raw_writew(w, OMAP1610_DMA_LCD_CSDP); + omap_writew(w, OMAP1610_DMA_LCD_CSDP); if (!lcd_dma.rotate) return; /* Rotation stuff */ - l = __raw_readw(OMAP1610_DMA_LCD_CSDP); + l = omap_readw(OMAP1610_DMA_LCD_CSDP); /* Disable burst access */ l &= ~(0x03 << 7); - __raw_writew(l, OMAP1610_DMA_LCD_CSDP); + omap_writew(l, OMAP1610_DMA_LCD_CSDP); - l = __raw_readw(OMAP1610_DMA_LCD_CCR); + l = omap_readw(OMAP1610_DMA_LCD_CCR); /* Set the double-indexed addressing mode */ l |= (0x03 << 12); - __raw_writew(l, OMAP1610_DMA_LCD_CCR); + omap_writew(l, OMAP1610_DMA_LCD_CCR); - __raw_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1); - __raw_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U); - __raw_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L); + omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1); + omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U); + omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L); } void omap_set_lcd_dma_b1_rotation(int rotate) @@ -460,7 +460,7 @@ void omap_free_lcd_dma(void) return; } if (!enable_1510_mode) - __raw_writew(__raw_readw(OMAP1610_DMA_LCD_CCR) & ~1, OMAP1610_DMA_LCD_CCR); + omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1, OMAP1610_DMA_LCD_CCR); lcd_dma.reserved = 0; spin_unlock(&lcd_dma.lock); } @@ -469,19 +469,19 @@ void omap_start_lcd_dma(void) { if (!enable_1510_mode) { /* Set some reasonable defaults */ - __raw_writew(0x9102, OMAP1610_DMA_LCD_CSDP); - __raw_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL); - __raw_writew(0x5740, OMAP1610_DMA_LCD_CCR); + omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP); + omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL); + omap_writew(0x5740, OMAP1610_DMA_LCD_CCR); } set_b1_regs(); if (!enable_1510_mode) - __raw_writew(__raw_readw(OMAP1610_DMA_LCD_CCR) | 1, OMAP1610_DMA_LCD_CCR); + omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) | 1, OMAP1610_DMA_LCD_CCR); } void omap_stop_lcd_dma(void) { if (!enable_1510_mode) - __raw_writew(__raw_readw(OMAP1610_DMA_LCD_CCR) & ~1, OMAP1610_DMA_LCD_CCR); + omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1, OMAP1610_DMA_LCD_CCR); } static int __init omap_init_dma(void) @@ -492,21 +492,21 @@ static int __init omap_init_dma(void) printk(KERN_INFO "DMA support for OMAP1510 initialized\n"); dma_chan_count = 9; enable_1510_mode = 1; - } else if (cpu_is_omap1610()) { + } else if (cpu_is_omap1610() || cpu_is_omap5912()) { printk(KERN_INFO "OMAP DMA hardware version %d\n", - __raw_readw(OMAP_DMA_HW_ID_REG)); + omap_readw(OMAP_DMA_HW_ID_REG)); printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n", - (__raw_readw(OMAP_DMA_CAPS_0_U_REG) << 16) | __raw_readw(OMAP_DMA_CAPS_0_L_REG), - (__raw_readw(OMAP_DMA_CAPS_1_U_REG) << 16) | __raw_readw(OMAP_DMA_CAPS_1_L_REG), - __raw_readw(OMAP_DMA_CAPS_2_REG), __raw_readw(OMAP_DMA_CAPS_3_REG), - __raw_readw(OMAP_DMA_CAPS_4_REG)); + (omap_readw(OMAP_DMA_CAPS_0_U_REG) << 16) | omap_readw(OMAP_DMA_CAPS_0_L_REG), + (omap_readw(OMAP_DMA_CAPS_1_U_REG) << 16) | omap_readw(OMAP_DMA_CAPS_1_L_REG), + omap_readw(OMAP_DMA_CAPS_2_REG), omap_readw(OMAP_DMA_CAPS_3_REG), + omap_readw(OMAP_DMA_CAPS_4_REG)); if (!enable_1510_mode) { u16 w; /* Disable OMAP 3.0/3.1 compatibility mode. */ - w = __raw_readw(OMAP_DMA_GSCR_REG); + w = omap_readw(OMAP_DMA_GSCR_REG); w |= 1 << 3; - __raw_writew(w, OMAP_DMA_GSCR_REG); + omap_writew(w, OMAP_DMA_GSCR_REG); dma_chan_count = OMAP_LOGICAL_DMA_CH_COUNT; } else dma_chan_count = 9; diff --git a/arch/arm/mach-omap/fpga.c b/arch/arm/mach-omap/fpga.c index 50d06dfd4113..95b21e2f48fb 100644 --- a/arch/arm/mach-omap/fpga.c +++ b/arch/arm/mach-omap/fpga.c @@ -1,7 +1,7 @@ /* * linux/arch/arm/mach-omap/fpga.c * - * Interrupt handler for OMAP-1510 FPGA + * Interrupt handler for OMAP-1510 Innovator FPGA * * Copyright (C) 2001 RidgeRun, Inc. * Author: Greg Lonnon <glonnon@ridgerun.com> diff --git a/arch/arm/mach-omap/gpio.c b/arch/arm/mach-omap/gpio.c index 4b9589d0f640..71141199f778 100644 --- a/arch/arm/mach-omap/gpio.c +++ b/arch/arm/mach-omap/gpio.c @@ -93,9 +93,9 @@ struct gpio_bank { #define METHOD_MPUIO 0 #define METHOD_GPIO_1510 1 #define METHOD_GPIO_1610 2 -#define METHOD_GPIO_730 3 +#define METHOD_GPIO_730 3 -#ifdef CONFIG_ARCH_OMAP1610 +#if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP5912) static struct gpio_bank gpio_bank_1610[5] = { { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO}, { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 }, @@ -136,8 +136,8 @@ static inline struct gpio_bank *get_gpio_bank(int gpio) return &gpio_bank[1]; } #endif -#ifdef CONFIG_ARCH_OMAP1610 - if (cpu_is_omap1610()) { +#if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP5912) + if (cpu_is_omap1610() || cpu_is_omap5912()) { if (OMAP_GPIO_IS_MPUIO(gpio)) return &gpio_bank[0]; return &gpio_bank[1 + (gpio >> 4)]; @@ -173,11 +173,11 @@ static inline int gpio_valid(int gpio) if (cpu_is_omap1510() && gpio < 16) return 0; #endif -#ifdef CONFIG_ARCH_OMAP1610 - if (cpu_is_omap1610() && gpio < 64) +#if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP5912) + if ((cpu_is_omap1610() || cpu_is_omap5912()) && gpio < 64) return 0; #endif -#ifdef CONFIG_ARCH_OMAP1610 +#ifdef CONFIG_ARCH_OMAP730 if (cpu_is_omap730() && gpio < 192) return 0; #endif @@ -213,12 +213,12 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) reg += OMAP730_GPIO_DIR_CONTROL; break; } - l = __raw_readl(reg); + l = omap_readl(reg); if (is_input) l |= 1 << gpio; else l &= ~(1 << gpio); - __raw_writel(l, reg); + omap_writel(l, reg); } void omap_set_gpio_direction(int gpio, int is_input) @@ -241,7 +241,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) switch (bank->method) { case METHOD_MPUIO: reg += OMAP_MPUIO_OUTPUT_REG; - l = __raw_readl(reg); + l = omap_readl(reg); if (enable) l |= 1 << gpio; else @@ -249,7 +249,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) break; case METHOD_GPIO_1510: reg += OMAP1510_GPIO_DATA_OUTPUT; - l = __raw_readl(reg); + l = omap_readl(reg); if (enable) l |= 1 << gpio; else @@ -264,7 +264,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) break; case METHOD_GPIO_730: reg += OMAP730_GPIO_DATA_OUTPUT; - l = __raw_readl(reg); + l = omap_readl(reg); if (enable) l |= 1 << gpio; else @@ -274,7 +274,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) BUG(); return; } - __raw_writel(l, reg); + omap_writel(l, reg); } void omap_set_gpio_dataout(int gpio, int enable) @@ -312,7 +312,7 @@ int omap_get_gpio_datain(int gpio) BUG(); return -1; } - return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0; + return (omap_readl(reg) & (1 << get_gpio_index(gpio))) != 0; } static void _set_gpio_edge_ctrl(struct gpio_bank *bank, int gpio, int edge) @@ -323,21 +323,21 @@ static void _set_gpio_edge_ctrl(struct gpio_bank *bank, int gpio, int edge) switch (bank->method) { case METHOD_MPUIO: reg += OMAP_MPUIO_GPIO_INT_EDGE_REG; - l = __raw_readl(reg); + l = omap_readl(reg); if (edge == OMAP_GPIO_RISING_EDGE) l |= 1 << gpio; else l &= ~(1 << gpio); - __raw_writel(l, reg); + omap_writel(l, reg); break; case METHOD_GPIO_1510: reg += OMAP1510_GPIO_INT_CONTROL; - l = __raw_readl(reg); + l = omap_readl(reg); if (edge == OMAP_GPIO_RISING_EDGE) l |= 1 << gpio; else l &= ~(1 << gpio); - __raw_writel(l, reg); + omap_writel(l, reg); break; case METHOD_GPIO_1610: edge &= 0x03; @@ -346,19 +346,19 @@ static void _set_gpio_edge_ctrl(struct gpio_bank *bank, int gpio, int edge) else reg += OMAP1610_GPIO_EDGE_CTRL1; gpio &= 0x07; - l = __raw_readl(reg); + l = omap_readl(reg); l &= ~(3 << (gpio << 1)); l |= edge << (gpio << 1); - __raw_writel(l, reg); + omap_writel(l, reg); break; case METHOD_GPIO_730: reg += OMAP730_GPIO_INT_CONTROL; - l = __raw_readl(reg); + l = omap_readl(reg); if (edge == OMAP_GPIO_RISING_EDGE) l |= 1 << gpio; else l &= ~(1 << gpio); - __raw_writel(l, reg); + omap_writel(l, reg); break; default: BUG(); @@ -385,11 +385,11 @@ static int _get_gpio_edge_ctrl(struct gpio_bank *bank, int gpio) switch (bank->method) { case METHOD_MPUIO: - l = __raw_readl(reg + OMAP_MPUIO_GPIO_INT_EDGE_REG); + l = omap_readl(reg + OMAP_MPUIO_GPIO_INT_EDGE_REG); return (l & (1 << gpio)) ? OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE; case METHOD_GPIO_1510: - l = __raw_readl(reg + OMAP1510_GPIO_INT_CONTROL); + l = omap_readl(reg + OMAP1510_GPIO_INT_CONTROL); return (l & (1 << gpio)) ? OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE; case METHOD_GPIO_1610: @@ -397,9 +397,9 @@ static int _get_gpio_edge_ctrl(struct gpio_bank *bank, int gpio) reg += OMAP1610_GPIO_EDGE_CTRL2; else reg += OMAP1610_GPIO_EDGE_CTRL1; - return (__raw_readl(reg) >> ((gpio & 0x07) << 1)) & 0x03; + return (omap_readl(reg) >> ((gpio & 0x07) << 1)) & 0x03; case METHOD_GPIO_730: - l = __raw_readl(reg + OMAP730_GPIO_INT_CONTROL); + l = omap_readl(reg + OMAP730_GPIO_INT_CONTROL); return (l & (1 << gpio)) ? OMAP_GPIO_RISING_EDGE : OMAP_GPIO_FALLING_EDGE; default: @@ -430,7 +430,7 @@ static void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) BUG(); return; } - __raw_writel(1 << get_gpio_index(gpio), reg); + omap_writel(1 << get_gpio_index(gpio), reg); } static void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) @@ -441,7 +441,7 @@ static void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) switch (bank->method) { case METHOD_MPUIO: reg += OMAP_MPUIO_GPIO_MASKIT; - l = __raw_readl(reg); + l = omap_readl(reg); if (enable) l &= ~(1 << gpio); else @@ -449,7 +449,7 @@ static void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) break; case METHOD_GPIO_1510: reg += OMAP1510_GPIO_INT_MASK; - l = __raw_readl(reg); + l = omap_readl(reg); if (enable) l &= ~(1 << gpio); else @@ -465,7 +465,7 @@ static void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) break; case METHOD_GPIO_730: reg += OMAP730_GPIO_INT_MASK; - l = __raw_readl(reg); + l = omap_readl(reg); if (enable) l &= ~(1 << gpio); else @@ -475,7 +475,7 @@ static void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) BUG(); return; } - __raw_writel(l, reg); + omap_writel(l, reg); } int omap_request_gpio(int gpio) @@ -500,7 +500,7 @@ int omap_request_gpio(int gpio) /* Claim the pin for the ARM */ reg = bank->base + OMAP1510_GPIO_PIN_CONTROL; - __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg); + omap_writel(omap_readl(reg) | (1 << get_gpio_index(gpio)), reg); } #endif spin_unlock(&bank->lock); @@ -555,7 +555,7 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc, if (bank->method == METHOD_GPIO_1510) isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS; #endif -#ifdef CONFIG_ARCH_OMAP1610 +#if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP5912) if (bank->method == METHOD_GPIO_1610) isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1; #endif @@ -564,7 +564,7 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc, isr_reg = bank->base + OMAP730_GPIO_INT_STATUS; #endif for (;;) { - u32 isr = __raw_readl(isr_reg); + u32 isr = omap_readl(isr_reg); unsigned int gpio_irq; if (!isr) @@ -587,15 +587,15 @@ static void gpio_ack_irq(unsigned int irq) #ifdef CONFIG_ARCH_OMAP1510 if (bank->method == METHOD_GPIO_1510) - __raw_writew(1 << gpio, bank->base + OMAP1510_GPIO_INT_STATUS); + omap_writew(1 << gpio, bank->base + OMAP1510_GPIO_INT_STATUS); #endif -#ifdef CONFIG_ARCH_OMAP1610 +#if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP5912) if (bank->method == METHOD_GPIO_1610) - __raw_writew(1 << gpio, bank->base + OMAP1610_GPIO_IRQSTATUS1); + omap_writew(1 << gpio, bank->base + OMAP1610_GPIO_IRQSTATUS1); #endif #ifdef CONFIG_ARCH_OMAP730 if (bank->method == METHOD_GPIO_730) - __raw_writel(1 << gpio, bank->base + OMAP730_GPIO_INT_STATUS); + omap_writel(1 << gpio, bank->base + OMAP730_GPIO_INT_STATUS); #endif } @@ -669,13 +669,13 @@ static int __init _omap_gpio_init(void) gpio_bank = gpio_bank_1510; } #endif -#ifdef CONFIG_ARCH_OMAP1610 - if (cpu_is_omap1610()) { +#if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP5912) + if (cpu_is_omap1610() || cpu_is_omap5912()) { int rev; gpio_bank_count = 5; gpio_bank = gpio_bank_1610; - rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); + rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", (rev >> 4) & 0x0f, rev & 0x0f); } @@ -694,24 +694,24 @@ static int __init _omap_gpio_init(void) bank->reserved_map = 0; spin_lock_init(&bank->lock); if (bank->method == METHOD_MPUIO) { - __raw_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT); + omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT); } #ifdef CONFIG_ARCH_OMAP1510 if (bank->method == METHOD_GPIO_1510) { - __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK); - __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS); + omap_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK); + omap_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS); } #endif -#ifdef CONFIG_ARCH_OMAP1610 +#if defined(CONFIG_ARCH_OMAP1610) || defined(CONFIG_ARCH_OMAP5912) if (bank->method == METHOD_GPIO_1610) { - __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1); - __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); + omap_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1); + omap_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); } #endif #ifdef CONFIG_ARCH_OMAP730 if (bank->method == METHOD_GPIO_730) { - __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK); - __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS); + omap_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK); + omap_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS); gpio_count = 32; /* 730 has 32-bit GPIOs */ } @@ -732,7 +732,7 @@ static int __init _omap_gpio_init(void) /* Enable system clock for GPIO module. * The CAM_CLK_CTRL_REG *is* really the right place. */ if (cpu_is_omap1610()) - __raw_writel(__raw_readl(ULPD_CAM_CLK_CTRL_REG) | 0x04, ULPD_CAM_CLK_CTRL_REG); + omap_writel(omap_readl(ULPD_CAM_CLK_CTRL_REG) | 0x04, ULPD_CAM_CLK_CTRL_REG); return 0; } diff --git a/arch/arm/mach-omap/irq.c b/arch/arm/mach-omap/irq.c index c563a2f03f72..c2441572a354 100644 --- a/arch/arm/mach-omap/irq.c +++ b/arch/arm/mach-omap/irq.c @@ -1,13 +1,18 @@ /* * linux/arch/arm/mach-omap/irq.c * - * Interrupt handler for OMAP-1510 and 1610 + * Interrupt handler for all OMAP boards * - * Copyright (C) 2001 RidgeRun, Inc. - * Author: Greg Lonnon <glonnon@ridgerun.com> + * Copyright (C) 2004 Nokia Corporation + * Written by Tony Lindgren <tony@atomide.com> * - * Modified for OMAP-1610 by Tony Lindgren <tony.lindgren@nokia.com> - * GPIO interrupt handler moved to gpio.c for OMAP-1610 by Juha Yrjola + * Completely re-written to support various OMAP chips with bank specific + * interrupt handlers. + * + * Some snippets of the code taken from the older OMAP interrupt handler + * Copyright (C) 2001 RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com> + * + * GPIO interrupt handler moved to gpio.c by Juha Yrjola * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -25,8 +30,8 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ @@ -44,181 +49,226 @@ #include <asm/io.h> -#define NUM_IRQS IH_BOARD_BASE +#include "irq.h" -static void mask_irq(unsigned int irq); -static void unmask_irq(unsigned int irq); -static void ack_irq(unsigned int irq); +static unsigned int banks = 0; +static struct omap_irq_bank irq_banks[MAX_NR_IRQ_BANKS]; -static inline void -write_ih(int level, int reg, u32 value) +static inline unsigned int irq_bank_readl(int bank, int offset) { - if (cpu_is_omap1510()) { - __raw_writel(value, - (IO_ADDRESS((level ? OMAP_IH2_BASE : OMAP_IH1_BASE) + - (reg)))); - } else { - if (level) { - __raw_writel(value, - IO_ADDRESS(OMAP_IH2_BASE + ((level - 1) << 8) + - reg)); - } else { - __raw_writel(value, IO_ADDRESS(OMAP_IH1_BASE + reg)); - } - } + return omap_readl(irq_banks[bank].base_reg + offset); } -static inline u32 -read_ih(int level, int reg) +static inline void irq_bank_writel(unsigned long value, int bank, int offset) { - if (cpu_is_omap1510()) { - return __raw_readl((IO_ADDRESS((level ? OMAP_IH2_BASE : OMAP_IH1_BASE) - + (reg)))); - } else { - if (level) { - return __raw_readl(IO_ADDRESS(OMAP_IH2_BASE + - ((level - 1) << 8) + reg)); - } else { - return __raw_readl(IO_ADDRESS(OMAP_IH1_BASE + reg)); - } - } + omap_writel(value, irq_banks[bank].base_reg + offset); } -static inline int -get_level(int irq) +/* + * Ack routine for chips with register offsets of 0x100 + */ +static void omap_offset_ack_irq(unsigned int irq) { - if (cpu_is_omap1510()) { - return (((irq) < IH2_BASE) ? 0 : 1); + if (irq > 31) + omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG); + + omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG); +} + +/* + * Mask routine for chips with register offsets of 0x100 + */ +static void omap_offset_mask_irq(unsigned int irq) +{ + int bank = IRQ_TO_BANK(irq); + + if (bank) { + omap_writel( + omap_readl(OMAP_IH2_BASE + BANK_OFFSET(bank) + IRQ_MIR) + | (1 << IRQ_BIT(irq)), + OMAP_IH2_BASE + BANK_OFFSET(bank) + IRQ_MIR); } else { - if (irq < IH2_BASE) - return 0; - else { - return (irq >> 5); - } + omap_writel( + omap_readl(OMAP_IH1_BASE + IRQ_MIR) + | (1 << IRQ_BIT(irq)), + OMAP_IH1_BASE + IRQ_MIR); } } -static inline int -get_irq_num(int irq) +/* + * Unmask routine for chips with register offsets of 0x100 + */ +static void omap_offset_unmask_irq(unsigned int irq) { - if (cpu_is_omap1510()) { - return (((irq) < IH2_BASE) ? irq : irq - IH2_BASE); + int bank = IRQ_TO_BANK(irq); + + if (bank) { + omap_writel( + omap_readl(OMAP_IH2_BASE + BANK_OFFSET(bank) + IRQ_MIR) + & ~(1 << IRQ_BIT(irq)), + OMAP_IH2_BASE + BANK_OFFSET(bank) + IRQ_MIR); } else { - return irq & 0x1f; + omap_writel( + omap_readl(OMAP_IH1_BASE + IRQ_MIR) + & ~(1 << IRQ_BIT(irq)), + OMAP_IH1_BASE + IRQ_MIR); } } -static void -mask_irq(unsigned int irq) +static void omap_offset_mask_ack_irq(unsigned int irq) { - int level = get_level(irq); - int irq_num = get_irq_num(irq); - u32 mask = read_ih(level, IRQ_MIR) | (1 << irq_num); - write_ih(level, IRQ_MIR, mask); + omap_offset_mask_irq(irq); + omap_offset_ack_irq(irq); } -static void -ack_irq(unsigned int irq) +/* + * Given the irq number returns the bank number + */ +signed int irq_get_bank(unsigned int irq) { - int level = get_level(irq); - - if (level > 1) - level = 1; - do { - write_ih(level, IRQ_CONTROL_REG, 0x1); - /* - * REVISIT: So says the TRM: - * if (level) write_ih(0, ITR, 0); - */ - } while (level--); + int i; + + for (i = 0; i < banks; i++) { + if (irq >= irq_banks[i].start_irq + && irq <= irq_banks[i].start_irq + BANK_NR_IRQS) { + return i; + } + } + + printk(KERN_ERR "No irq handler found for irq %i\n", irq); + + return -ENODEV; } -void -unmask_irq(unsigned int irq) +/* + * Given the bank and irq number returns the irq bit at the bank register + */ +signed int irq_bank_get_bit(int bank, unsigned int irq) { - int level = get_level(irq); - int irq_num = get_irq_num(irq); - u32 mask = read_ih(level, IRQ_MIR) & ~(1 << irq_num); + if (irq_banks[bank].start_irq > irq) { + printk(KERN_ERR "Incorrect irq %i: bank %i offset %i\n", + irq, bank, irq_banks[bank].start_irq); + return -ENODEV; + } - write_ih(level, IRQ_MIR, mask); + return irq - irq_banks[bank].start_irq; } -static void -mask_ack_irq(unsigned int irq) +/* + * Allows tuning the IRQ type and priority + * + * NOTE: There is currently no OMAP fiq handler for Linux. Read the + * mailing list threads on FIQ handlers if you are planning to + * add a FIQ handler for OMAP. + */ +void omap_irq_set_cfg(int irq, int fiq, int priority, int irq_level) { - mask_irq(irq); - ack_irq(irq); + signed int bank; + unsigned int irq_bit; + unsigned long val, offset; + + + bank = irq_get_bank(irq); + + if (bank < 0) + return; + + irq_bit = irq_bank_get_bit(bank, irq); + + if (irq_bit < 0) + return; + + /* FIQ is only availabe on bank 0 interrupts */ + fiq = bank ? 0 : (fiq & 0x1); + + val = fiq | ((priority & 0x1f) << 2) | ((irq_level & 0x1) << 1); + + offset = IRQ_ILR0 + irq_bit * 0x4; + + irq_bank_writel(val, bank, offset); } -static struct irqchip omap_normal_irq = { - .ack = mask_ack_irq, - .mask = mask_irq, - .unmask = unmask_irq, +static struct omap_irq_desc *irq_bank_desc[] __initdata = { + &omap730_bank0_irqs, + &omap730_bank1_irqs, + &omap730_bank2_irqs, + &omap1510_bank0_irqs, + &omap1510_bank1_irqs, + &omap1610_bank0_irqs, + &omap1610_bank1_irqs, + &omap1610_bank2_irqs, + &omap1610_bank3_irqs, + NULL, }; -static void -irq_priority(int irq, int fiq, int priority, int trigger) +void __init omap_init_irq(void) { - int level, irq_num; - unsigned long reg_value, reg_addr; - - level = get_level(irq); - irq_num = get_irq_num(irq); - /* FIQ is only available on level 0 interrupts */ - fiq = level ? 0 : (fiq & 0x1); - reg_value = (fiq) | ((priority & 0x1f) << 2) | - ((trigger & 0x1) << 1); - reg_addr = (IRQ_ILR0 + irq_num * 0x4); - write_ih(level, reg_addr, reg_value); -} + int i,j, board_irq_type = 0, interrupts = 0; + struct omap_irq_desc *entry; -void __init -omap_init_irq(void) -{ - int i, irq_count, irq_bank_count = 0; - uint *trigger; - - if (cpu_is_omap1510()) { - static uint trigger_1510[2] = { - 0xb3febfff, 0xffbfffed - }; - irq_bank_count = 2; - irq_count = 64; - trigger = trigger_1510; - } - if (cpu_is_omap1610()) { - static uint trigger_1610[5] = { - 0xb3fefe8f, 0xfffff7ff, 0xffffffff - }; - irq_bank_count = 5; - irq_count = 160; - trigger = trigger_1610; - } if (cpu_is_omap730()) { - static uint trigger_730[] = { - 0xb3f8e22f, 0xfdb9c1f2, 0x800040f3 - }; - irq_bank_count = 3; - irq_count = 96; - trigger = trigger_730; + board_irq_type = OMAP_IRQ_TYPE730; + } else if (cpu_is_omap1510()) { + board_irq_type = OMAP_IRQ_TYPE1510; + } else if (cpu_is_omap1610() || cpu_is_omap5912()) { + board_irq_type = OMAP_IRQ_TYPE1610; } - for (i = 0; i < irq_bank_count; i++) { - /* Mask and clear all interrupts */ - write_ih(i, IRQ_MIR, ~0x0); - write_ih(i, IRQ_ITR, 0x0); + if (board_irq_type == 0) { + printk("Could not detect OMAP type\n"); + return; + } + + /* Scan through the interrupt bank maps and copy the right data */ + for (i = 0; (entry = irq_bank_desc[i]) != NULL; i++) { + if (entry->cpu_type == board_irq_type) { + printk("Type %i IRQs from %3i to %3i base at 0x%lx\n", + board_irq_type, entry->start_irq, + entry->start_irq + BANK_NR_IRQS, entry->base_reg); + + irq_banks[banks].start_irq = entry->start_irq; + irq_banks[banks].level_map = entry->level_map; + irq_banks[banks].base_reg = entry->base_reg; + irq_banks[banks].mask_reg = entry->mask_reg; + irq_banks[banks].ack_reg = entry->ack_reg; + irq_banks[banks].handler = entry->handler; + + interrupts += BANK_NR_IRQS; + banks++; + } } - /* Clear any pending interrupts */ - write_ih(1, IRQ_CONTROL_REG, 3); - write_ih(0, IRQ_CONTROL_REG, 3); + printk("Found total of %i interrupts in %i interrupt banks\n", + interrupts, banks); + + /* Mask and clear all interrupts */ + for (i = 0; i < banks; i++) { + irq_bank_writel(~0x0, i, IRQ_MIR); + irq_bank_writel(0x0, i, IRQ_ITR); + } - for (i = 0; i < irq_count; i++) { - set_irq_chip(i, &omap_normal_irq); - set_irq_handler(i, do_level_IRQ); - set_irq_flags(i, IRQF_VALID); + /* + * Clear any pending interrupts + */ + irq_bank_writel(3, 0, IRQ_CONTROL_REG); + irq_bank_writel(3, 1, IRQ_CONTROL_REG); - irq_priority(i, 0, 0, trigger[get_level(i)] >> get_irq_num(i) & 1); + /* Install the interrupt handlers for each bank */ + for (i = 0; i < banks; i++) { + for (j = irq_banks[i].start_irq; + j <= irq_banks[i].start_irq + BANK_NR_IRQS; j++) { + int irq_level; + set_irq_chip(j, irq_banks[i].handler); + set_irq_handler(j, do_level_IRQ); + set_irq_flags(j, IRQF_VALID); + irq_level = irq_banks[i].level_map + >> (j - irq_banks[i].start_irq) & 1; + omap_irq_set_cfg(j, 0, 0, irq_level); + } } - unmask_irq(INT_IH2_IRQ); + + /* Unmask level 2 handler */ + omap_writel(0, irq_banks[0].mask_reg); } + +EXPORT_SYMBOL(omap_irq_set_cfg); diff --git a/arch/arm/mach-omap/irq.h b/arch/arm/mach-omap/irq.h new file mode 100644 index 000000000000..8e1aa7810162 --- /dev/null +++ b/arch/arm/mach-omap/irq.h @@ -0,0 +1,172 @@ +/* + * linux/arch/arm/mach-omap/irq.h + * + * OMAP specific interrupt bank definitions + * + * Copyright (C) 2004 Nokia Corporation + * Written by Tony Lindgren <tony@atomide.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#define OMAP_IRQ_TYPE710 1 +#define OMAP_IRQ_TYPE730 2 +#define OMAP_IRQ_TYPE1510 3 +#define OMAP_IRQ_TYPE1610 4 +#define OMAP_IRQ_TYPE1710 5 + +#define MAX_NR_IRQ_BANKS 4 + +#define BANK_NR_IRQS 32 + +struct omap_irq_desc { + unsigned int cpu_type; + unsigned int start_irq; + unsigned long level_map; + unsigned long base_reg; + unsigned long mask_reg; + unsigned long ack_reg; + struct irqchip *handler; +}; + +struct omap_irq_bank { + unsigned int start_irq; + unsigned long level_map; + unsigned long base_reg; + unsigned long mask_reg; + unsigned long ack_reg; + struct irqchip *handler; +}; + +static void omap_offset_ack_irq(unsigned int irq); +static void omap_offset_mask_irq(unsigned int irq); +static void omap_offset_unmask_irq(unsigned int irq); +static void omap_offset_mask_ack_irq(unsigned int irq); + +/* NOTE: These will not work if irq bank offset != 0x100 */ +#define IRQ_TO_BANK(irq) (irq >> 5) +#define IRQ_BIT(irq) (irq & 0x1f) +#define BANK_OFFSET(bank) ((bank - 1) * 0x100) + +static struct irqchip omap_offset_irq = { + .ack = omap_offset_mask_ack_irq, + .mask = omap_offset_mask_irq, + .unmask = omap_offset_unmask_irq, +}; + +/* + * OMAP-730 interrupt banks + */ +static struct omap_irq_desc omap730_bank0_irqs __initdata = { + .cpu_type = OMAP_IRQ_TYPE730, + .start_irq = 0, + .level_map = 0xb3f8e22f, + .base_reg = OMAP_IH1_BASE, + .mask_reg = OMAP_IH1_BASE + IRQ_MIR, + .ack_reg = OMAP_IH1_BASE + IRQ_CONTROL_REG, + .handler = &omap_offset_irq, /* IH2 regs at 0x100 offsets */ +}; + +static struct omap_irq_desc omap730_bank1_irqs __initdata = { + .cpu_type = OMAP_IRQ_TYPE730, + .start_irq = 32, + .level_map = 0xfdb9c1f2, + .base_reg = OMAP_IH2_BASE, + .mask_reg = OMAP_IH2_BASE + IRQ_MIR, + .ack_reg = OMAP_IH2_BASE + IRQ_CONTROL_REG, + .handler = &omap_offset_irq, /* IH2 regs at 0x100 offsets */ +}; + +static struct omap_irq_desc omap730_bank2_irqs __initdata = { + .cpu_type = OMAP_IRQ_TYPE730, + .start_irq = 64, + .level_map = 0x800040f3, + .base_reg = OMAP_IH2_BASE + 0x100, + .mask_reg = OMAP_IH2_BASE + 0x100 + IRQ_MIR, + .ack_reg = OMAP_IH2_BASE + IRQ_CONTROL_REG, /* Not replicated */ + .handler = &omap_offset_irq, /* IH2 regs at 0x100 offsets */ +}; + +/* + * OMAP-1510 interrupt banks + */ +static struct omap_irq_desc omap1510_bank0_irqs __initdata = { + .cpu_type = OMAP_IRQ_TYPE1510, + .start_irq = 0, + .level_map = 0xb3febfff, + .base_reg = OMAP_IH1_BASE, + .mask_reg = OMAP_IH1_BASE + IRQ_MIR, + .ack_reg = OMAP_IH1_BASE + IRQ_CONTROL_REG, + .handler = &omap_offset_irq, /* IH2 regs at 0x100 offsets */ +}; + +static struct omap_irq_desc omap1510_bank1_irqs __initdata = { + .cpu_type = OMAP_IRQ_TYPE1510, + .start_irq = 32, + .level_map = 0xffbfffed, + .base_reg = OMAP_IH2_BASE, + .mask_reg = OMAP_IH2_BASE + IRQ_MIR, + .ack_reg = OMAP_IH2_BASE + IRQ_CONTROL_REG, + .handler = &omap_offset_irq, /* IH2 regs at 0x100 offsets */ +}; + +/* + * OMAP-1610 interrupt banks + */ +static struct omap_irq_desc omap1610_bank0_irqs __initdata = { + .cpu_type = OMAP_IRQ_TYPE1610, + .start_irq = 0, + .level_map = 0xb3fefe8f, + .base_reg = OMAP_IH1_BASE, + .mask_reg = OMAP_IH1_BASE + IRQ_MIR, + .ack_reg = OMAP_IH1_BASE + IRQ_CONTROL_REG, + .handler = &omap_offset_irq, /* IH2 regs at 0x100 offsets */ +}; + +static struct omap_irq_desc omap1610_bank1_irqs __initdata = { + .cpu_type = OMAP_IRQ_TYPE1610, + .start_irq = 32, + .level_map = 0xfffff7ff, + .base_reg = OMAP_IH2_BASE, + .mask_reg = OMAP_IH2_BASE + IRQ_MIR, + .ack_reg = OMAP_IH2_BASE + IRQ_CONTROL_REG, + .handler = &omap_offset_irq, /* IH2 regs at 0x100 offsets */ +}; + +static struct omap_irq_desc omap1610_bank2_irqs __initdata = { + .cpu_type = OMAP_IRQ_TYPE1610, + .start_irq = 64, + .level_map = 0xffffffff, + .base_reg = OMAP_IH2_BASE + 0x100, + .mask_reg = OMAP_IH2_BASE + 0x100 + IRQ_MIR, + .ack_reg = OMAP_IH2_BASE + IRQ_CONTROL_REG, /* Not replicated */ + .handler = &omap_offset_irq, /* IH2 regs at 0x100 offsets */ +}; + +static struct omap_irq_desc omap1610_bank3_irqs __initdata = { + .cpu_type = OMAP_IRQ_TYPE1610, + .start_irq = 96, + .level_map = 0xffffffff, + .base_reg = OMAP_IH2_BASE + 0x200, + .mask_reg = OMAP_IH2_BASE + 0x200 + IRQ_MIR, + .ack_reg = OMAP_IH2_BASE + IRQ_CONTROL_REG, /* Not replicated */ + .handler = &omap_offset_irq, /* IH2 regs at 0x100 offsets */ +}; diff --git a/arch/arm/mach-omap/leds-perseus2.c b/arch/arm/mach-omap/leds-perseus2.c index f73b5ddc3dd9..7a24b3b205c5 100644 --- a/arch/arm/mach-omap/leds-perseus2.c +++ b/arch/arm/mach-omap/leds-perseus2.c @@ -14,7 +14,6 @@ #include <asm/hardware.h> #include <asm/leds.h> #include <asm/system.h> -#include <asm/arch/omap-perseus2.h> #include "leds.h" @@ -97,7 +96,7 @@ void perseus2_leds_event(led_event_t evt) /* * Actually burn the LEDs */ - __raw_writew(~hw_led_state & 0xffff, OMAP730_FPGA_LEDS); + omap_writew(~hw_led_state & 0xffff, OMAP730_FPGA_LEDS); local_irq_restore(flags); } diff --git a/arch/arm/mach-omap/leds.c b/arch/arm/mach-omap/leds.c index 4cbc48f3f550..e3f378b4a699 100644 --- a/arch/arm/mach-omap/leds.c +++ b/arch/arm/mach-omap/leds.c @@ -13,9 +13,13 @@ static int __init omap1510_leds_init(void) { - if (machine_is_innovator()) + if (machine_is_omap_innovator()) leds_event = innovator_leds_event; + else if (machine_is_omap_perseus2()) { + leds_event = perseus2_leds_event; + } + leds_event(led_start); return 0; } diff --git a/arch/arm/mach-omap/mux.c b/arch/arm/mach-omap/mux.c index 1b186c9fd534..70665dfafeee 100644 --- a/arch/arm/mach-omap/mux.c +++ b/arch/arm/mach-omap/mux.c @@ -32,14 +32,14 @@ #define __MUX_C__ #include <asm/arch/mux.h> -static spinlock_t mux_spin_lock = SPIN_LOCK_UNLOCKED; - /* * Sets the Omap MUX and PULL_DWN registers based on the table */ int omap_cfg_reg(const reg_cfg_t reg_cfg) { #ifdef CONFIG_OMAP_MUX + static spinlock_t mux_spin_lock = SPIN_LOCK_UNLOCKED; + unsigned long flags; reg_cfg_set *cfg; unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0, @@ -56,20 +56,20 @@ int omap_cfg_reg(const reg_cfg_t reg_cfg) /* Check the mux register in question */ if (cfg->mux_reg) { - reg_orig = __raw_readl(cfg->mux_reg); + reg_orig = omap_readl(cfg->mux_reg); /* The mux registers always seem to be 3 bits long */ reg = reg_orig & ~(0x7 << cfg->mask_offset); reg |= (cfg->mask << cfg->mask_offset); - __raw_writel(reg, cfg->mux_reg); + omap_writel(reg, cfg->mux_reg); } /* Check for pull up or pull down selection on 1610 */ if (!cpu_is_omap1510()) { if (cfg->pu_pd_reg && cfg->pull_val) { - pu_pd_orig = __raw_readl(cfg->pu_pd_reg); + pu_pd_orig = omap_readl(cfg->pu_pd_reg); if (cfg->pu_pd_val) { /* Use pull up */ pu_pd = pu_pd_orig | (1 << cfg->pull_bit); @@ -77,13 +77,13 @@ int omap_cfg_reg(const reg_cfg_t reg_cfg) /* Use pull down */ pu_pd = pu_pd_orig & ~(1 << cfg->pull_bit); } - __raw_writel(pu_pd, cfg->pu_pd_reg); + omap_writel(pu_pd, cfg->pu_pd_reg); } } /* Check for an associated pull down register */ if (cfg->pull_reg) { - pull_orig = __raw_readl(cfg->pull_reg); + pull_orig = omap_readl(cfg->pull_reg); if (cfg->pull_val) { /* Low bit = pull enabled */ @@ -93,7 +93,7 @@ int omap_cfg_reg(const reg_cfg_t reg_cfg) pull = pull_orig | (1 << cfg->pull_bit); } - __raw_writel(pull, cfg->pull_reg); + omap_writel(pull, cfg->pull_reg); } #ifdef CONFIG_OMAP_MUX_DEBUG @@ -110,8 +110,9 @@ int omap_cfg_reg(const reg_cfg_t reg_cfg) } } - printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n", - cfg->pull_name, cfg->pull_reg, pull_orig, pull); + if (cfg->pull_reg) + printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n", + cfg->pull_name, cfg->pull_reg, pull_orig, pull); } #endif diff --git a/arch/arm/mach-omap/ocpi.c b/arch/arm/mach-omap/ocpi.c index 977c0d29addf..e7087bc24ab7 100644 --- a/arch/arm/mach-omap/ocpi.c +++ b/arch/arm/mach-omap/ocpi.c @@ -1,7 +1,7 @@ /* * linux/arch/arm/mach-omap/ocpi.c * - * Minimal OCP bus support for OMAP-1610 + * Minimal OCP bus support for OMAP-1610 and OMAP-5912 * * Copyright (C) 2003 - 2004 Nokia Corporation * Written by Tony Lindgren <tony@atomide.com> @@ -58,28 +58,40 @@ int ocpi_enable(void) unsigned int val; /* Make sure there's clock for OCPI */ - val = __raw_readl(ARM_IDLECT3); - val |= EN_OCPI_CK; - val &= ~IDLOCPI_ARM; - __raw_writel(val, ARM_IDLECT3); +#ifdef CONFIG_ARCH_OMAP1610 + if (cpu_is_omap1610()) { + val = omap_readl(OMAP1610_ARM_IDLECT3); + val |= EN_OCPI_CK; + val &= ~IDLOCPI_ARM; + omap_writel(val, OMAP1610_ARM_IDLECT3); + } +#endif +#ifdef CONFIG_ARCH_OMAP5912 + if (cpu_is_omap5912()) { + val = omap_readl(OMAP5912_ARM_IDLECT3); + val |= EN_OCPI_CK; + val &= ~IDLOCPI_ARM; + omap_writel(val, OMAP5912_ARM_IDLECT3); + } +#endif /* Enable access for OHCI in OCPI */ - val = __raw_readl(OCPI_PROT); + val = omap_readl(OCPI_PROT); val &= ~0xff; //val &= (1 << 0); /* Allow access only to EMIFS */ - __raw_writel(val, OCPI_PROT); + omap_writel(val, OCPI_PROT); - val = __raw_readl(OCPI_SEC); + val = omap_readl(OCPI_SEC); val &= ~0xff; - __raw_writel(val, OCPI_SEC); + omap_writel(val, OCPI_SEC); - val = __raw_readl(OCPI_SEC); + val = omap_readl(OCPI_SEC); val |= 0; - __raw_writel(val, OCPI_SEC); + omap_writel(val, OCPI_SEC); - val = __raw_readl(OCPI_SINT0); + val = omap_readl(OCPI_SINT0); val |= 0; - __raw_writel(val, OCPI_SINT1); + omap_writel(val, OCPI_SINT1); return 0; } @@ -89,8 +101,8 @@ int ocpi_status(void) { printk("OCPI: addr: 0x%08x cmd: 0x%08x\n" " ohci-addr: 0x%08x ohci-status: 0x%08x\n", - __raw_readl(OCPI_FAULT), __raw_readl(OCPI_CMD_FAULT), - __raw_readl(HOSTUEADDR), __raw_readl(HOSTUESTATUS)); + omap_readl(OCPI_FAULT), omap_readl(OCPI_CMD_FAULT), + omap_readl(HOSTUEADDR), omap_readl(HOSTUESTATUS)); return 1; } diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index d7968d6896ee..54efc6721c0f 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -79,7 +79,7 @@ config CPU_ARM920T # ARM922T config CPU_ARM922T bool - depends on ARCH_CAMELOT + depends on ARCH_CAMELOT || ARCH_LH7A40X default y select CPU_32v4 select CPU_ABRT_EV4T @@ -115,7 +115,7 @@ config CPU_ARM925T # ARM926T config CPU_ARM926T bool "Support ARM926T processor" if ARCH_INTEGRATOR - depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || ARCH_OMAP1610 + depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || ARCH_OMAP730 || ARCH_OMAP1610 || ARCH_OMAP5912 default y if ARCH_VERSATILE_PB select CPU_32v5 select CPU_ABRT_EV5TJ diff --git a/arch/arm/mm/discontig.c b/arch/arm/mm/discontig.c index 5d67df4a6073..0d097bb1bc4d 100644 --- a/arch/arm/mm/discontig.c +++ b/arch/arm/mm/discontig.c @@ -15,8 +15,8 @@ #include <linux/init.h> #include <linux/bootmem.h> -#if MAX_NUMNODES != 4 -#error Fix Me Please +#if MAX_NUMNODES != 4 && MAX_NUMNODES != 16 +# error Fix Me Please #endif /* @@ -29,8 +29,21 @@ pg_data_t discontig_node_data[MAX_NUMNODES] = { { .bdata = &node_bootmem_data[0] }, { .bdata = &node_bootmem_data[1] }, { .bdata = &node_bootmem_data[2] }, - { .bdata = &node_bootmem_data[3] } + { .bdata = &node_bootmem_data[3] }, +#if MAX_NUMNODES == 16 + { .bdata = &node_bootmem_data[4] }, + { .bdata = &node_bootmem_data[5] }, + { .bdata = &node_bootmem_data[6] }, + { .bdata = &node_bootmem_data[7] }, + { .bdata = &node_bootmem_data[8] }, + { .bdata = &node_bootmem_data[9] }, + { .bdata = &node_bootmem_data[10] }, + { .bdata = &node_bootmem_data[11] }, + { .bdata = &node_bootmem_data[12] }, + { .bdata = &node_bootmem_data[13] }, + { .bdata = &node_bootmem_data[14] }, + { .bdata = &node_bootmem_data[15] }, +#endif }; EXPORT_SYMBOL(discontig_node_data); - diff --git a/arch/x86_64/kernel/mce.c b/arch/x86_64/kernel/mce.c index 8dfd18ca3741..922d62fcf782 100644 --- a/arch/x86_64/kernel/mce.c +++ b/arch/x86_64/kernel/mce.c @@ -71,17 +71,19 @@ static void mce_log(struct mce *mce) static void print_mce(struct mce *m) { - printk("CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n", + printk(KERN_EMERG + "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n", m->cpu, m->mcgstatus, m->bank, m->status); if (m->rip) { - printk("RIP%s %02x:<%016Lx> ", + printk(KERN_EMERG + "RIP%s %02x:<%016Lx> ", !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", m->cs, m->rip); if (m->cs == __KERNEL_CS) print_symbol("{%s}", m->rip); printk("\n"); } - printk("TSC %Lx ", m->tsc); + printk(KERN_EMERG "TSC %Lx ", m->tsc); if (m->addr) printk("ADDR %Lx ", m->addr); if (m->misc) @@ -177,9 +179,14 @@ void do_machine_check(struct pt_regs * regs, long error_code) int user_space = (m.rip && (m.cs & 3)); /* When the machine was in user space and the CPU didn't get - confused it's normally not necessary to panic, unless you are - paranoid (tolerant == 0) */ - if (!user_space && (panic_on_oops || tolerant < 2)) + confused it's normally not necessary to panic, unless you + are paranoid (tolerant == 0) + + RED-PEN could be more tolerant for MCEs in idle, + but most likely they occur at boot anyways, where + it is best to just halt the machine. */ + if ((!user_space && (panic_on_oops || tolerant < 2)) || + (unsigned)current->pid <= 1) mce_panic("Uncorrected machine check", &m, mcestart); /* do_exit takes an awful lot of locks and has as slight risk diff --git a/arch/x86_64/kernel/pci-gart.c b/arch/x86_64/kernel/pci-gart.c index 292b675293e5..8eb20a7dc299 100644 --- a/arch/x86_64/kernel/pci-gart.c +++ b/arch/x86_64/kernel/pci-gart.c @@ -618,6 +618,7 @@ EXPORT_SYMBOL(pci_dma_supported); EXPORT_SYMBOL(no_iommu); EXPORT_SYMBOL(force_iommu); EXPORT_SYMBOL(bad_dma_address); +EXPORT_SYMBOL(iommu_merge); static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size) { diff --git a/arch/x86_64/kernel/pci-nommu.c b/arch/x86_64/kernel/pci-nommu.c index 278c626badd8..00fb2645c510 100644 --- a/arch/x86_64/kernel/pci-nommu.c +++ b/arch/x86_64/kernel/pci-nommu.c @@ -5,6 +5,10 @@ #include <asm/proto.h> int iommu_merge = 0; +EXPORT_SYMBOL(iommu_merge); + +dma_addr_t bad_dma_address; +EXPORT_SYMBOL(bad_dma_address); /* * Dummy IO MMU functions diff --git a/drivers/acpi/processor.c b/drivers/acpi/processor.c index d0c50022573c..99c02080f3a5 100644 --- a/drivers/acpi/processor.c +++ b/drivers/acpi/processor.c @@ -2225,6 +2225,16 @@ acpi_processor_get_info ( object.processor.pblk_address + 4; pr->power.states[ACPI_STATE_C3].address = object.processor.pblk_address + 5; + + /* + * We don't care about error returns - we just try to mark + * these reserved so that nobody else is confused into thinking + * that this region might be unused.. + * + * (In particular, allocating the IO range for Cardbus) + */ + request_region(pr->throttling.address, 6, "ACPI CPU throttle"); + request_region(acpi_fadt.xpm_tmr_blk.address, 4, "ACPI timer"); } acpi_processor_get_power_info(pr); diff --git a/drivers/isdn/hardware/eicon/idifunc.c b/drivers/isdn/hardware/eicon/idifunc.c index 7824cf95bd95..f3427aad634b 100644 --- a/drivers/isdn/hardware/eicon/idifunc.c +++ b/drivers/isdn/hardware/eicon/idifunc.c @@ -1,4 +1,4 @@ -/* $Id: idifunc.c,v 1.14 2004/03/21 18:13:43 armin Exp $ +/* $Id: idifunc.c,v 1.14.4.2 2004/05/09 16:42:20 armin Exp $ * * Driver for Eicon DIVA Server ISDN cards. * User Mode IDI Interface @@ -137,14 +137,14 @@ static void um_remove_card(DESCRIPTOR * d) static void DIVA_EXIT_FUNCTION remove_all_idi_proc(void) { udiva_card *card; - struct list_head *tmp; diva_os_spin_lock_magic_t old_irql; rescan: diva_os_enter_spin_lock(&ll_lock, &old_irql, "remove all"); - list_for_each(tmp, &cards) { - card = list_entry(tmp, udiva_card, list); - diva_os_leave_spin_lock(&ll_lock, &old_irql, "remove all"); + if (!list_empty(&cards)) { + card = list_entry(cards.next, udiva_card, list); + list_del(&card->list); + diva_os_leave_spin_lock(&ll_lock, &old_irql, "remove all"); diva_user_mode_idi_remove_adapter(card->Id); diva_os_free(0, card); goto rescan; diff --git a/include/asm-arm/arch-lh7a40x/constants.h b/include/asm-arm/arch-lh7a40x/constants.h new file mode 100644 index 000000000000..52c1cb9c39c6 --- /dev/null +++ b/include/asm-arm/arch-lh7a40x/constants.h @@ -0,0 +1,88 @@ +/* include/asm-arm/arch-lh7a40x/constants.h + * + * Copyright (C) 2004 Coastal Environmental Systems + * Copyright (C) 2004 Logic Product Development + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +#ifndef __ASM_ARCH_CONSTANTS_H +#define __ASM_ARCH_CONSTANTS_H + +#include <linux/config.h> + +/* Addressing constants */ + + /* SoC CPU IO addressing */ +#define IO_PHYS (0x80000000) +#define IO_VIRT (0xf8000000) +#define IO_SIZE (0x0000B000) + +#ifdef CONFIG_MACH_KEV7A400 +# define CPLD_PHYS (0x20000000) +# define CPLD_VIRT (0xf2000000) +# define CPLD_SIZE PAGE_SIZE +#endif + +#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) + +# define IOBARRIER_PHYS 0xc0000000 /* Start of SDRAM */ +/*# define IOBARRIER_PHYS 0x00000000 */ /* Start of flash */ +# define IOBARRIER_VIRT 0xf0000000 +# define IOBARRIER_SIZE PAGE_SIZE + +# define CF_PHYS 0x60200000 +# define CF_VIRT 0xf6020000 +# define CF_SIZE (8*1024) + + /* The IO mappings for the LPD CPLD are, unfortunately, sparse. */ +# define CPLDX_PHYS(x) (0x70000000 | ((x) << 20)) +# define CPLDX_VIRT(x) (0xf7000000 | ((x) << 16)) +# define CPLD00_PHYS CPLDX_PHYS (0x00) /* Wired LAN */ +# define CPLD00_VIRT CPLDX_VIRT (0x00) +# define CPLD00_SIZE PAGE_SIZE +# define CPLD02_PHYS CPLDX_PHYS (0x02) +# define CPLD02_VIRT CPLDX_VIRT (0x02) +# define CPLD02_SIZE PAGE_SIZE +# define CPLD06_PHYS CPLDX_PHYS (0x06) +# define CPLD06_VIRT CPLDX_VIRT (0x06) +# define CPLD06_SIZE PAGE_SIZE +# define CPLD08_PHYS CPLDX_PHYS (0x08) +# define CPLD08_VIRT CPLDX_VIRT (0x08) +# define CPLD08_SIZE PAGE_SIZE +# define CPLD0C_PHYS CPLDX_PHYS (0x0c) +# define CPLD0C_VIRT CPLDX_VIRT (0x0c) +# define CPLD0C_SIZE PAGE_SIZE +# define CPLD0E_PHYS CPLDX_PHYS (0x0e) +# define CPLD0E_VIRT CPLDX_VIRT (0x0e) +# define CPLD0E_SIZE PAGE_SIZE +# define CPLD10_PHYS CPLDX_PHYS (0x10) +# define CPLD10_VIRT CPLDX_VIRT (0x10) +# define CPLD10_SIZE PAGE_SIZE +# define CPLD12_PHYS CPLDX_PHYS (0x12) +# define CPLD12_VIRT CPLDX_VIRT (0x12) +# define CPLD12_SIZE PAGE_SIZE +# define CPLD14_PHYS CPLDX_PHYS (0x14) +# define CPLD14_VIRT CPLDX_VIRT (0x14) +# define CPLD14_SIZE PAGE_SIZE +# define CPLD16_PHYS CPLDX_PHYS (0x16) +# define CPLD16_VIRT CPLDX_VIRT (0x16) +# define CPLD16_SIZE PAGE_SIZE +# define CPLD18_PHYS CPLDX_PHYS (0x18) +# define CPLD18_VIRT CPLDX_VIRT (0x18) +# define CPLD18_SIZE PAGE_SIZE +# define CPLD1A_PHYS CPLDX_PHYS (0x1a) +# define CPLD1A_VIRT CPLDX_VIRT (0x1a) +# define CPLD1A_SIZE PAGE_SIZE +#endif + + /* Timing constants */ + +#define XTAL_IN 14745600 /* 14.7456 MHz crystal */ +#define PLL_CLOCK (XTAL_IN * 21) /* 309 MHz PLL clock */ +#define MAX_HCLK_KHZ 100000 /* HCLK max limit ~100MHz */ + +#endif /* __ASM_ARCH_CONSTANTS_H */ diff --git a/include/asm-arm/arch-lh7a40x/dma.h b/include/asm-arm/arch-lh7a40x/dma.h new file mode 100644 index 000000000000..5797f01e1844 --- /dev/null +++ b/include/asm-arm/arch-lh7a40x/dma.h @@ -0,0 +1,17 @@ +/* include/asm-arm/arch-lh7a40x/dma.h + * + * Copyright (C) 2003 Coastal Environmental Systems + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +#ifndef __ASM_ARCH_DMA_H +#define __ASM_ARCH_DMA_H + +#define MAX_DMA_ADDRESS 0xffffffff +#define MAX_DMA_CHANNELS 0 /* All DMA is internal to CPU */ + +#endif /* _ASM_ARCH_DMA_H */ diff --git a/include/asm-arm/arch-lh7a40x/hardware.h b/include/asm-arm/arch-lh7a40x/hardware.h new file mode 100644 index 000000000000..2d75c6d74a20 --- /dev/null +++ b/include/asm-arm/arch-lh7a40x/hardware.h @@ -0,0 +1,60 @@ +/* include/asm-arm/arch-lh7a40x/hardware.h + * + * Copyright (C) 2004 Coastal Environmental Systems + * + * [ Substantially cribbed from include/asm-arm/arch-pxa/hardware.h ] + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include <asm/mach-types.h> + +#define io_p2v(x) (0xf0000000 | (((x) & 0xfff00000) >> 4) | ((x) & 0x0000ffff)) +#define io_v2p(x) ( (((x) & 0x0fff0000) << 4) | ((x) & 0x0000ffff)) + +#ifdef __ASSEMBLY__ + +# define __REG(x) io_p2v(x) +# define __PREG(x) io_v2p(x) + +#else + +# if 0 +# define __REG(x) (*((volatile u32 *)io_p2v(x))) +# else +/* + * This __REG() version gives the same results as the one above, except + * that we are fooling gcc somehow so it generates far better and smaller + * assembly code for access to contigous registers. It's a shame that gcc + * doesn't guess this by itself. + */ +#include <asm/types.h> +typedef struct { volatile u32 offset[4096]; } __regbase; +# define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2] +# define __REG(x) __REGP(io_p2v(x)) +typedef struct { volatile u16 offset[4096]; } __regbase16; +# define __REGP16(x) ((__regbase16 *)((x)&~4095))->offset[((x)&4095)>>2] +# define __REG16(x) __REGP16(io_p2v(x)) +typedef struct { volatile u8 offset[4096]; } __regbase8; +# define __REGP8(x) ((__regbase8 *)((x)&~4095))->offset[((x)&4095)>>2] +# define __REG8(x) __REGP8(io_p2v(x)) +#endif + +/* Let's kick gcc's ass again... */ +# define __REG2(x,y) \ + ( __builtin_constant_p(y) ? (__REG((x) + (y))) \ + : (*(volatile u32 *)((u32)&__REG(x) + (y))) ) + +# define __PREG(x) (io_v2p((u32)&(x))) + +#endif + +#include "registers.h" + +#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-lh7a40x/ide.h b/include/asm-arm/arch-lh7a40x/ide.h new file mode 100644 index 000000000000..7a461d166052 --- /dev/null +++ b/include/asm-arm/arch-lh7a40x/ide.h @@ -0,0 +1,76 @@ +/* include/asm-arm/arch-lh7a40x/ide.h + * + * Copyright (C) 2004 Logic Product Development + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +#ifndef __ASM_ARCH_IDE_H +#define __ASM_ARCH_IDE_H + +#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) + +/* This implementation of ide.h only applies to the LPD CardEngines. + * Thankfully, there is less to do for the KEV. + */ + +#include <linux/config.h> +#include <asm/irq.h> +#include <asm/hardware.h> +#include <asm/arch/registers.h> + +#define IDE_REG_LINE (1<<12) /* A12 drives !REG */ +#define IDE_ALT_LINE (1<<11) /* Unused A11 allows non-overlapping regions */ +#define IDE_CONTROLREG_OFFSET (0xe) + +void lpd7a40x_hwif_ioops (struct hwif_s* hwif); + +static __inline__ void ide_init_hwif_ports (hw_regs_t *hw, int data_port, + int ctrl_port, int *irq) +{ + ide_ioreg_t reg; + int i; + int regincr = 1; + + memset (hw, 0, sizeof (*hw)); + + reg = (ide_ioreg_t) data_port; + + for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { + hw->io_ports[i] = reg; + reg += regincr; + } + + hw->io_ports[IDE_CONTROL_OFFSET] = (ide_ioreg_t) ctrl_port; + + if (irq) + *irq = IDE_NO_IRQ; +} + +static __inline__ void ide_init_default_hwifs (void) +{ + hw_regs_t hw; + struct hwif_s* hwif; + + ide_init_hwif_ports (&hw, + CF_VIRT + IDE_REG_LINE, + CF_VIRT + IDE_REG_LINE + IDE_ALT_LINE + + IDE_CONTROLREG_OFFSET, + NULL); + + ide_register_hw (&hw, &hwif); + lpd7a40x_hwif_ioops (hwif); /* Override IO routines */ +} + +#else + +static __inline__ void ide_init_hwif_ports (hw_regs_t *hw, int data_port, + int ctrl_port, int *irq) {} +static __inline__ void ide_init_default_hwifs (void) {} + +#endif + +#endif diff --git a/include/asm-arm/arch-lh7a40x/io.h b/include/asm-arm/arch-lh7a40x/io.h new file mode 100644 index 000000000000..eeb2a3b6027c --- /dev/null +++ b/include/asm-arm/arch-lh7a40x/io.h @@ -0,0 +1,21 @@ +/* include/asm-arm/arch-lh7a40x/io.h + * + * Copyright (C) 2004 Coastal Environmental Systems + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +/* No ISA or PCI bus on this machine. */ +#define __io(a) (a) +#define __mem_pci(a) ((unsigned long)(a)) +#define __mem_isa(a) ((unsigned long)(a)) + +#endif /* __ASM_ARCH_IO_H */ diff --git a/include/asm-arm/arch-lh7a40x/irq.h b/include/asm-arm/arch-lh7a40x/irq.h new file mode 100644 index 000000000000..0f5f0b10f6ca --- /dev/null +++ b/include/asm-arm/arch-lh7a40x/irq.h @@ -0,0 +1,11 @@ +/* include/asm-arm/arch-lh7a40x/irq.h + * + * Copyright (C) 2004 Logic Product Development + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +void __init lh7a40x_init_board_irq (void); diff --git a/include/asm-arm/arch-lh7a40x/irqs.h b/include/asm-arm/arch-lh7a40x/irqs.h new file mode 100644 index 000000000000..f91f3e59f3ab --- /dev/null +++ b/include/asm-arm/arch-lh7a40x/irqs.h @@ -0,0 +1,196 @@ +/* include/asm-arm/arch-lh7a40x/irqs.h + * + * Copyright (C) 2004 Coastal Environmental Systems + * Copyright (C) 2004 Logic Product Development + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +/* It is to be seen whether or not we can build a kernel for more than + * one board. For the time being, these macros assume that we cannot. + * Thus, it is OK to ifdef machine/board specific IRQ assignments. + */ + + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +#include <linux/config.h> + +#define FIQ_START 80 + +#if defined (CONFIG_ARCH_LH7A400) + + /* FIQs */ + +# define IRQ_GPIO0FIQ 0 /* GPIO External FIQ Interrupt on F0 */ +# define IRQ_BLINT 1 /* Battery Low */ +# define IRQ_WEINT 2 /* Watchdog Timer, WDT overflow */ +# define IRQ_MCINT 3 /* Media Change, MEDCHG pin rising */ + + /* IRQs */ + +# define IRQ_CSINT 4 /* Audio Codec (ACI) */ +# define IRQ_GPIO1INTR 5 /* GPIO External IRQ Interrupt on F1 */ +# define IRQ_GPIO2INTR 6 /* GPIO External IRQ Interrupt on F2 */ +# define IRQ_GPIO3INTR 7 /* GPIO External IRQ Interrupt on F3 */ +# define IRQ_T1UI 8 /* Timer 1 underflow */ +# define IRQ_T2UI 9 /* Timer 2 underflow */ +# define IRQ_RTCMI 10 +# define IRQ_TINTR 11 /* Clock State Controller 64 Hz tick (CSC) */ +# define IRQ_UART1INTR 12 +# define IRQ_UART2INTR 13 +# define IRQ_LCDINTR 14 +# define IRQ_SSIEOT 15 /* Synchronous Serial Interface (SSI) */ +# define IRQ_UART3INTR 16 +# define IRQ_SCIINTR 17 /* Smart Card Interface (SCI) */ +# define IRQ_AACINTR 18 /* Advanced Audio Codec (AAC) */ +# define IRQ_MMCINTR 19 /* Multimedia Card (MMC) */ +# define IRQ_USBINTR 20 +# define IRQ_DMAINTR 21 +# define IRQ_T3UI 22 /* Timer 3 underflow */ +# define IRQ_GPIO4INTR 23 /* GPIO External IRQ Interrupt on F4 */ +# define IRQ_GPIO5INTR 24 /* GPIO External IRQ Interrupt on F5 */ +# define IRQ_GPIO6INTR 25 /* GPIO External IRQ Interrupt on F6 */ +# define IRQ_GPIO7INTR 26 /* GPIO External IRQ Interrupt on F7 */ +# define IRQ_BMIINTR 27 /* Battery Monitor Interface (BMI) */ + +# define NR_IRQ_CPU 28 /* IRQs directly recognized by CPU */ + + /* Given IRQ, return GPIO interrupt number 0-7 */ +# define IRQ_TO_GPIO(i) ((i) \ + - (((i) > IRQ_GPIO3INTR) ? IRQ_GPIO4INTR - IRQ_GPIO3INTR - 1 : 0)\ + - (((i) > IRQ_GPIO0INTR) ? IRQ_GPIO1INTR - IRQ_GPIO0INTR - 1 : 0)) + +#endif + +#if defined (CONFIG_ARCH_LH7A404) + +# define IRQ_BROWN 0 /* Brownout */ +# define IRQ_WDTINTR 1 /* Watchdog Timer */ +# define IRQ_COMMRX 2 /* ARM Comm Rx for Debug */ +# define IRQ_COMMTX 3 /* ARM Comm Tx for Debug */ +# define IRQ_T1UI 4 /* Timer 1 underflow */ +# define IRQ_T2UI 5 /* Timer 2 underflow */ +# define IRQ_CSINT 6 /* Codec Interrupt (shared by AAC on 404) */ +# define IRQ_DMAM2P0 7 /* -- DMA Memory to Peripheral */ +# define IRQ_DMAM2P1 8 +# define IRQ_DMAM2P2 9 +# define IRQ_DMAM2P3 10 +# define IRQ_DMAM2P4 11 +# define IRQ_DMAM2P5 12 +# define IRQ_DMAM2P6 13 +# define IRQ_DMAM2P7 14 +# define IRQ_DMAM2P8 15 +# define IRQ_DMAM2P9 16 +# define IRQ_DMAM2M0 17 /* -- DMA Memory to Memory */ +# define IRQ_DMAM2M1 18 +# define IRQ_GPIO0INTR 19 /* -- GPIOF Interrupt */ +# define IRQ_GPIO1INTR 20 +# define IRQ_GPIO2INTR 21 +# define IRQ_GPIO3INTR 22 +# define IRQ_SOFT_V1_23 23 /* -- Unassigned */ +# define IRQ_SOFT_V1_24 24 +# define IRQ_SOFT_V1_25 25 +# define IRQ_SOFT_V1_26 26 +# define IRQ_SOFT_V1_27 27 +# define IRQ_SOFT_V1_28 28 +# define IRQ_SOFT_V1_29 29 +# define IRQ_SOFT_V1_30 30 +# define IRQ_SOFT_V1_31 31 + +# define IRQ_BLINT 32 /* Battery Low */ +# define IRQ_BMIINTR 33 /* Battery Monitor */ +# define IRQ_MCINTR 34 /* Media Change */ +# define IRQ_TINTR 35 /* 64Hz Tick */ +# define IRQ_WEINT 36 /* Watchdog Expired */ +# define IRQ_RTCMI 37 /* Real-time Clock Match */ +# define IRQ_UART1INTR 38 /* UART1 Interrupt (including error) */ +# define IRQ_UART1ERR 39 /* UART1 Error */ +# define IRQ_UART2INTR 40 /* UART2 Interrupt (including error) */ +# define IRQ_UART2ERR 41 /* UART2 Error */ +# define IRQ_UART3INTR 42 /* UART3 Interrupt (including error) */ +# define IRQ_UART3ERR 43 /* UART3 Error */ +# define IRQ_SCIINTR 44 /* Smart Card */ +# define IRQ_TSCINTR 45 /* Touchscreen */ +# define IRQ_KMIINTR 46 /* Keyboard/Mouse (PS/2) */ +# define IRQ_GPIO4INTR 47 /* -- GPIOF Interrupt */ +# define IRQ_GPIO5INTR 48 +# define IRQ_GPIO6INTR 49 +# define IRQ_GPIO7INTR 50 +# define IRQ_T3UI 51 /* Timer 3 underflow */ +# define IRQ_LCDINTR 52 /* LCD Controller */ +# define IRQ_SSPINTR 53 /* Synchronous Serial Port */ +# define IRQ_SDINTR 54 /* Secure Digital Port (MMC) */ +# define IRQ_USBINTR 55 /* USB Device Port */ +# define IRQ_USHINTR 56 /* USB Host Port */ +# define IRQ_SOFT_V2_25 57 /* -- Unassigned */ +# define IRQ_SOFT_V2_26 58 +# define IRQ_SOFT_V2_27 59 +# define IRQ_SOFT_V2_28 60 +# define IRQ_SOFT_V2_29 61 +# define IRQ_SOFT_V2_30 62 +# define IRQ_SOFT_V2_31 63 + +# define NR_IRQ_CPU 64 /* IRQs directly recognized by CPU */ + + /* Given IRQ, return GPIO interrupt number 0-7 */ +# define IRQ_TO_GPIO(i) ((i) \ + - (((i) > IRQ_GPIO3INTR) ? IRQ_GPIO4INTR - IRQ_GPIO3INTR - 1 : 0)\ + - IRQ_GPIO0INTR) + + /* Vector Address constants */ +# define VA_VECTORED 0x100 /* Set for vectored interrupt */ +# define VA_VIC1DEFAULT 0x200 /* Set as default VECTADDR for VIC1 */ +# define VA_VIC2DEFAULT 0x400 /* Set as default VECTADDR for VIC2 */ + +#endif + + /* IRQ aliases */ + +#if !defined (IRQ_GPIO0INTR) +# define IRQ_GPIO0INTR IRQ_GPIO0FIQ +#endif +#define IRQ_TICK IRQ_TINTR +#define IRQ_PCC1_RDY IRQ_GPIO6INTR /* PCCard 1 ready */ +#define IRQ_PCC2_RDY IRQ_GPIO7INTR /* PCCard 2 ready */ + +#ifdef CONFIG_MACH_KEV7A400 +# define IRQ_TS IRQ_GPIOFIQ /* Touchscreen */ +# define IRQ_CPLD IRQ_GPIO1INTR /* CPLD cascade */ +# define IRQ_PCC1_CD IRQ_GPIO_F2 /* PCCard 1 card detect */ +# define IRQ_PCC2_CD IRQ_GPIO_F3 /* PCCard 2 card detect */ +#endif + +#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) +# define IRQ_CPLD_V28 IRQ_GPIO7INTR /* CPLD cascade through GPIO_PF7 */ +# define IRQ_CPLD_V34 IRQ_GPIO3INTR /* CPLD cascade through GPIO_PF3 */ +#endif + + /* System specific IRQs */ + +#define IRQ_BOARD_START NR_IRQ_CPU + +#ifdef CONFIG_MACH_KEV7A400 +# define IRQ_KEV7A400_CPLD IRQ_BOARD_START +# define NR_IRQ_BOARD 5 +# define IRQ_KEV7A400_MMC_CD IRQ_KEV7A400_CPLD + 0 /* MMC Card Detect */ +# define IRQ_KEV7A400_RI2 IRQ_KEV7A400_CPLD + 1 /* Ring Indicator 2 */ +# define IRQ_KEV7A400_IDE_CF IRQ_KEV7A400_CPLD + 2 /* Compact Flash (?) */ +# define IRQ_KEV7A400_ETH_INT IRQ_KEV7A400_CPLD + 3 /* Ethernet chip */ +# define IRQ_KEV7A400_INT IRQ_KEV7A400_CPLD + 4 +#endif + +#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) +# define IRQ_LPD7A40X_CPLD IRQ_BOARD_START +# define NR_IRQ_BOARD 2 +# define IRQ_LPD7A40X_ETH_INT IRQ_LPD7A40X_CPLD + 0 /* Ethernet chip */ +# define IRQ_LPD7A400_TS IRQ_LPD7A40X_CPLD + 1 /* Touch screen */ +#endif + +#define NR_IRQS (NR_IRQ_CPU + NR_IRQ_BOARD) + +#endif diff --git a/include/asm-arm/arch-lh7a40x/memory.h b/include/asm-arm/arch-lh7a40x/memory.h new file mode 100644 index 000000000000..2632ae73c078 --- /dev/null +++ b/include/asm-arm/arch-lh7a40x/memory.h @@ -0,0 +1,146 @@ +/* include/asm-arm/arch-lh7a40x/memory.h + * + * Copyright (C) 2004 Coastal Environmental Systems + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + + +#define BANKS_PER_NODE 1 /* Define as either 1 or 2 */ + +/* + * Task size: 3GB + */ +#define TASK_SIZE (0xbf000000UL) /* 0xc0000000? */ +#define TASK_SIZE_26 (0x04000000UL) + +/* + * This decides where the kernel will search for a free chunk of vm + * space during mmap's. + */ +#define TASK_UNMAPPED_BASE (0x40000000) + +/* + * Page offset: 3GB + */ +#define PAGE_OFFSET (0xc0000000UL) + +/* + * Physical DRAM offset. + */ +#define PHYS_OFFSET (0xc0000000UL) + +/* + * physical vs virtual ram conversion + */ +#define __virt_to_phys__is_a_macro +#define __phys_to_virt__is_a_macro +#define __virt_to_phys(x) ((x) - PAGE_OFFSET + PHYS_OFFSET) +#define __phys_to_virt(x) ((x) - PHYS_OFFSET + PAGE_OFFSET) + +/* + * Virtual view <-> DMA view memory address translations + * virt_to_bus: Used to translate the virtual address to an + * address suitable to be passed to set_dma_addr + * bus_to_virt: Used to convert an address for DMA operations + * to an address that the kernel can use. + */ +#define __virt_to_bus__is_a_macro +#define __bus_to_virt__is_a_macro +#define __virt_to_bus(x) __virt_to_phys(x) +#define __bus_to_virt(x) __phys_to_virt(x) + +#ifdef CONFIG_DISCONTIGMEM +/* + * Because of the wide memory address space between physical RAM + * banks, it's convenient to use Linux's NUMA support to represent our + * memory map. Assuming all memory nodes have equal access + * characteristics, we then have a generic discontiguous memory setup. + * + * Of course, all this isn't mandatory for implementations with only + * one used memory bank. For those, simply undefine + * CONFIG_DISCONTIGMEM. However, keep in mind that a featurefull + * system will need more than 4MiB of RAM. + * + * The contiguous memory blocks are small enough that it pays to + * aggregate two banks into one node. Setting BANKS_PER_NODE to 2 + * puts pairs of banks into a node. + * + * A typical layout would start like this: + * + * node 0: 0xc0000000 + * 0xc1000000 + * node 1: 0xc4000000 + * 0xc5000000 + * node 2: 0xc8000000 + * 0xc9000000 + * + * The proximity of the pairs of blocks makes it feasible to combine them. + * + */ + +/* + * Given a kernel address, find the home node of the underlying memory. + */ + +#if BANKS_PER_NODE==1 +#define KVADDR_TO_NID(addr) \ + ( ((((unsigned long) (addr) - PAGE_OFFSET) >> 24) & 1)\ + | ((((unsigned long) (addr) - PAGE_OFFSET) >> 25) & ~1)) +#else /* 2 banks per node */ +#define KVADDR_TO_NID(addr) \ + ((unsigned long) (addr) - PAGE_OFFSET) >> 26) +#endif + +/* + * Given a page frame number, convert it to a node id. + */ + +#if BANKS_PER_NODE==1 +#define PFN_TO_NID(pfn) \ + (((((pfn) - PHYS_PFN_OFFSET) >> (24 - PAGE_SHIFT)) & 1)\ + | ((((pfn) - PHYS_PFN_OFFSET) >> (25 - PAGE_SHIFT)) & ~1)) +#else /* 2 banks per node */ +#define PFN_TO_NID(addr) \ + (((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT)) +#endif + +/* + * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory + * and return the mem_map of that node. + */ +#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr)) + +/* + * Given a page frame number, find the owning node of the memory + * and return the mem_map of that node. + */ +#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn)) + +/* + * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory + * and returns the index corresponding to the appropriate page in the + * node's mem_map. + */ + +#if BANKS_PER_NODE==1 +#define LOCAL_MAP_NR(addr) \ + (((unsigned long)(addr) & 0x003fffff) >> PAGE_SHIFT) +#else /* 2 banks per node */ +#define LOCAL_MAP_NR(addr) \ + (((unsigned long)(addr) & 0x01ffffff) >> PAGE_SHIFT) +#endif + +#else + +#define PFN_TO_NID(addr) (0) + +#endif + +#endif diff --git a/include/asm-arm/arch-lh7a40x/param.h b/include/asm-arm/arch-lh7a40x/param.h new file mode 100644 index 000000000000..acad0bc5deba --- /dev/null +++ b/include/asm-arm/arch-lh7a40x/param.h @@ -0,0 +1,9 @@ +/* include/asm-arm/arch-lh7a40x/param.h + * + * Copyright (C) 2004 Coastal Environmental Systems + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ diff --git a/include/asm-arm/arch-lh7a40x/registers.h b/include/asm-arm/arch-lh7a40x/registers.h new file mode 100644 index 000000000000..2edb22e35450 --- /dev/null +++ b/include/asm-arm/arch-lh7a40x/registers.h @@ -0,0 +1,193 @@ +/* include/asm-arm/arch-lh7a40x/registers.h + * + * Copyright (C) 2004 Coastal Environmental Systems + * Copyright (C) 2004 Logic Product Development + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +#include <linux/config.h> +#include <asm/arch/constants.h> + +#ifndef __ASM_ARCH_REGISTERS_H +#define __ASM_ARCH_REGISTERS_H + + + /* Physical register base addresses */ + +#define AC97_PHYS (0x80000000) /* AC97 Controller */ +#define MMC_PHYS (0x80000100) /* Multimedia Card Controller */ +#define USB_PHYS (0x80000200) /* USB Client */ +#define SCI_PHYS (0x80000300) /* Secure Card Interface */ +#define CSC_PHYS (0x80000400) /* Clock/State Controller */ +#define INTC_PHYS (0x80000500) /* Interrupt Controller */ +#define UART1_PHYS (0x80000600) /* UART1 Controller */ +#define SIR_PHYS (0x80000600) /* IR Controller, same are UART1 */ +#define UART2_PHYS (0x80000700) /* UART2 Controller */ +#define UART3_PHYS (0x80000800) /* UART3 Controller */ +#define DCDC_PHYS (0x80000900) /* DC to DC Controller */ +#define ACI_PHYS (0x80000a00) /* Audio Codec Interface */ +#define SSP_PHYS (0x80000b00) /* Synchronous ... */ +#define TIMER_PHYS (0x80000c00) /* Timer Controller */ +#define RTC_PHYS (0x80000d00) /* Real-time Clock */ +#define GPIO_PHYS (0x80000e00) /* General Purpose IO */ +#define BMI_PHYS (0x80000f00) /* Battery Monitor Interface */ +#define WDT_PHYS (0x80001400) /* Watchdog Timer */ +#define SMC_PHYS (0x80002000) /* Static Memory Controller */ +#define SDRC_PHYS (0x80002400) /* SDRAM Controller */ +#define DMAC_PHYS (0x80002800) /* DMA Controller */ +#define CLCDC_PHYS (0x80003000) /* Color LCD Controller */ + + /* Physical registers of the LH7A404 */ + +#define VIC1_PHYS (0x80008000) /* Vectored Interrupt Controller 1 */ +#define USBH_PHYS (0x80009000) /* USB OHCI host controller */ +#define VIC2_PHYS (0x8000a000) /* Vectored Interrupt Controller 2 */ + +/*#define KBD_PHYS (0x80000e00) */ +/*#define LCDICP_PHYS (0x80001000) */ + + + /* Clock/State Controller register */ + +#define CSC_PWRCNT __REG(CSC_PHYS + 0x04) /* Power control */ + +#define CSC_PWRCNT_USBH_EN (1<<28) /* USB Host power enable */ + + + /* Interrupt Controller registers */ + +#define INTC_INTSR __REG(INTC_PHYS + 0x00) /* Status */ +#define INTC_INTRSR __REG(INTC_PHYS + 0x04) /* Raw Status */ +#define INTC_INTENS __REG(INTC_PHYS + 0x08) /* Enable Set */ +#define INTC_INTENC __REG(INTC_PHYS + 0x0c) /* Enable Clear */ + + + /* Vectored Interrupted Controller registers */ + +#define VIC1_IRQSTATUS __REG(VIC1_PHYS + 0x00) +#define VIC1_FIQSTATUS __REG(VIC1_PHYS + 0x04) +#define VIC1_RAWINTR __REG(VIC1_PHYS + 0x08) +#define VIC1_INTSEL __REG(VIC1_PHYS + 0x0c) +#define VIC1_INTEN __REG(VIC1_PHYS + 0x10) +#define VIC1_INTENCLR __REG(VIC1_PHYS + 0x14) +#define VIC1_SOFTINT __REG(VIC1_PHYS + 0x18) +#define VIC1_SOFTINTCLR __REG(VIC1_PHYS + 0x1c) +#define VIC1_PROTECT __REG(VIC1_PHYS + 0x20) +#define VIC1_VECTADDR __REG(VIC1_PHYS + 0x30) +#define VIC1_NVADDR __REG(VIC1_PHYS + 0x34) +#define VIC1_VAD0 __REG(VIC1_PHYS + 0x100) +#define VIC1_VECTCNTL0 __REG(VIC1_PHYS + 0x200) +#define VIC2_IRQSTATUS __REG(VIC2_PHYS + 0x00) +#define VIC2_FIQSTATUS __REG(VIC2_PHYS + 0x04) +#define VIC2_RAWINTR __REG(VIC2_PHYS + 0x08) +#define VIC2_INTSEL __REG(VIC2_PHYS + 0x0c) +#define VIC2_INTEN __REG(VIC2_PHYS + 0x10) +#define VIC2_INTENCLR __REG(VIC2_PHYS + 0x14) +#define VIC2_SOFTINT __REG(VIC2_PHYS + 0x18) +#define VIC2_SOFTINTCLR __REG(VIC2_PHYS + 0x1c) +#define VIC2_PROTECT __REG(VIC2_PHYS + 0x20) +#define VIC2_VECTADDR __REG(VIC2_PHYS + 0x30) +#define VIC2_NVADDR __REG(VIC2_PHYS + 0x34) +#define VIC2_VAD0 __REG(VIC2_PHYS + 0x100) +#define VIC2_VECTCNTL0 __REG(VIC2_PHYS + 0x200) + +#define VIC_CNTL_ENABLE (0x20) + + /* USB Host registers (Open HCI compatible) */ + +#define USBH_CMDSTATUS __REG(USBH_PHYS + 0x08) + + + /* GPIO registers */ + +#define GPIO_INTTYPE1 __REG(GPIO_PHYS + 0x4c) /* Interrupt Type 1 (Edge) */ +#define GPIO_INTTYPE2 __REG(GPIO_PHYS + 0x50) /* Interrupt Type 2 */ +#define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */ +#define GPIO_GPIOINTEN __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */ +#define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */ + + + /* Static Memory Controller registers */ + +#define SMC_BCR0 __REG(SMC_PHYS + 0x00) /* Bank 0 Configuration */ +#define SMC_BCR1 __REG(SMC_PHYS + 0x04) /* Bank 1 Configuration */ +#define SMC_BCR2 __REG(SMC_PHYS + 0x08) /* Bank 2 Configuration */ +#define SMC_BCR3 __REG(SMC_PHYS + 0x0C) /* Bank 3 Configuration */ +#define SMC_BCR6 __REG(SMC_PHYS + 0x18) /* Bank 6 Configuration */ +#define SMC_BCR7 __REG(SMC_PHYS + 0x1c) /* Bank 7 Configuration */ + + +#ifdef CONFIG_MACH_KEV7A400 +# define CPLD_RD_OPT_DIP_SW __REG16(CPLD_PHYS + 0x00) /* Read Option SW */ +# define CPLD_WR_IO_BRD_CTL __REG16(CPLD_PHYS + 0x00) /* Write Control */ +# define CPLD_RD_PB_KEYS __REG16(CPLD_PHYS + 0x02) /* Read Btn Keys */ +# define CPLD_LATCHED_INTS __REG16(CPLD_PHYS + 0x04) /* Read INTR stat. */ +# define CPLD_CL_INT __REG16(CPLD_PHYS + 0x04) /* Clear INTR stat */ +# define CPLD_BOOT_MMC_STATUS __REG16(CPLD_PHYS + 0x06) /* R/O */ +# define CPLD_RD_KPD_ROW_SENSE __REG16(CPLD_PHYS + 0x08) +# define CPLD_WR_PB_INT_MASK __REG16(CPLD_PHYS + 0x08) +# define CPLD_RD_BRD_DISP_SW __REG16(CPLD_PHYS + 0x0a) +# define CPLD_WR_EXT_INT_MASK __REG16(CPLD_PHYS + 0x0a) +# define CPLD_LCD_PWR_CNTL __REG16(CPLD_PHYS + 0x0c) +# define CPLD_SEVEN_SEG __REG16(CPLD_PHYS + 0x0e) /* 7 seg. LED mask */ + +#endif + +#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) +# define CPLD_CONTROL __REG8(CPLD02_PHYS) +# define CPLD_SPI_DATA __REG8(CPLD06_PHYS) +# define CPLD_SPI_CONTROL __REG8(CPLD08_PHYS) +# define CPLD_SPI_EEPROM __REG8(CPLD0A_PHYS) +# define CPLD_INTERRUPTS __REG8(CPLD0C_PHYS) /* IRQ mask/status */ +# define CPLD_BOOT_MODE __REG8(CPLD0E_PHYS) +# define CPLD_FLASH __REG8(CPLD10_PHYS) +# define CPLD_POWER_MGMT __REG8(CPLD12_PHYS) +# define CPLD_REVISION __REG8(CPLD14_PHYS) +# define CPLD_GPIO_EXT __REG8(CPLD16_PHYS) +# define CPLD_GPIO_DATA __REG8(CPLD18_PHYS) +# define CPLD_GPIO_DIR __REG8(CPLD1A_PHYS) +#endif + + + /* Timer registers */ + +#define TIMER_LOAD1 __REG(TIMER_PHYS + 0x00) /* Timer 1 initial value */ +#define TIMER_VALUE1 __REG(TIMER_PHYS + 0x04) /* Timer 1 current value */ +#define TIMER_CONTROL1 __REG(TIMER_PHYS + 0x08) /* Timer 1 control word */ +#define TIMER_EOI1 __REG(TIMER_PHYS + 0x0c) /* Timer 1 interrupt clear */ + +#define TIMER_LOAD2 __REG(TIMER_PHYS + 0x20) /* Timer 2 initial value */ +#define TIMER_VALUE2 __REG(TIMER_PHYS + 0x24) /* Timer 2 current value */ +#define TIMER_CONTROL2 __REG(TIMER_PHYS + 0x28) /* Timer 2 control word */ +#define TIMER_EOI2 __REG(TIMER_PHYS + 0x2c) /* Timer 2 interrupt clear */ + +#define TIMER_BUZZCON __REG(TIMER_PHYS + 0x40) /* Buzzer configuration */ + +#define TIMER_LOAD3 __REG(TIMER_PHYS + 0x80) /* Timer 3 initial value */ +#define TIMER_VALUE3 __REG(TIMER_PHYS + 0x84) /* Timer 3 current value */ +#define TIMER_CONTROL3 __REG(TIMER_PHYS + 0x88) /* Timer 3 control word */ +#define TIMER_EOI3 __REG(TIMER_PHYS + 0x8c) /* Timer 3 interrupt clear */ + +#define TIMER_C_ENABLE (1<<7) +#define TIMER_C_PERIODIC (1<<6) +#define TIMER_C_FREERUNNING (0) +#define TIMER_C_2KHZ (0x00) /* 1.986 kHz */ +#define TIMER_C_508KHZ (0x08) + + /* GPIO registers */ + +#define GPIO_PFDD __REG(GPIO_PHYS + 0x34) /* PF direction */ +#define GPIO_INTTYPE1 __REG(GPIO_PHYS + 0x4c) /* IRQ edge or lvl */ +#define GPIO_INTTYPE2 __REG(GPIO_PHYS + 0x50) /* IRQ activ hi/lo */ +#define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIOF end of IRQ */ +#define GPIO_GPIOFINTEN __REG(GPIO_PHYS + 0x58) /* GPIOF IRQ enable */ +#define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIOF IRQ latch */ +#define GPIO_RAWINTSTATUS __REG(GPIO_PHYS + 0x60) /* GPIOF IRQ raw */ + + +#endif /* _ASM_ARCH_REGISTERS_H */ + diff --git a/include/asm-arm/arch-lh7a40x/serial.h b/include/asm-arm/arch-lh7a40x/serial.h new file mode 100644 index 000000000000..64783c05fb92 --- /dev/null +++ b/include/asm-arm/arch-lh7a40x/serial.h @@ -0,0 +1,25 @@ +/* include/asm-arm/arch-lh7a40x/serial.h + * + * Copyright (C) 2004 Coastal Environmental Systems + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +#ifndef __ASM_ARCH_SERIAL_H +#define __ASM_ARCH_SERIAL_H + +#include <asm/arch/registers.h> + +#define UART_R_DATA (0x00) +#define UART_R_FCON (0x04) +#define UART_R_BRCON (0x08) +#define UART_R_CON (0x0c) +#define UART_R_STATUS (0x10) +#define UART_R_RAWISR (0x14) +#define UART_R_INTEN (0x18) +#define UART_R_ISR (0x1c) + +#endif /* _ASM_ARCH_SERIAL_H */ diff --git a/include/asm-arm/arch-lh7a40x/system.h b/include/asm-arm/arch-lh7a40x/system.h new file mode 100644 index 000000000000..e1df8aa460f2 --- /dev/null +++ b/include/asm-arm/arch-lh7a40x/system.h @@ -0,0 +1,19 @@ +/* include/asm-arm/arch-lh7a40x/system.h + * + * Copyright (C) 2004 Coastal Environmental Systems + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +static inline void arch_idle(void) +{ + cpu_do_idle (); +} + +static inline void arch_reset(char mode) +{ + cpu_reset (0); +} diff --git a/include/asm-arm/arch-lh7a40x/time.h b/include/asm-arm/arch-lh7a40x/time.h new file mode 100644 index 000000000000..5f1cf4f9b2c7 --- /dev/null +++ b/include/asm-arm/arch-lh7a40x/time.h @@ -0,0 +1,53 @@ +/* include/asm-arm/arch-lh7a40x/time.h + * + * Copyright (C) 2004 Logic Product Development + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +#if HZ < 100 +# define TIMER_CONTROL TIMER_CONTROL1 +# define TIMER_LOAD TIMER_LOAD1 +# define TIMER_CONSTANT (508469/HZ) +# define TIMER_MODE (TIMER_C_ENABLE | TIMER_C_PERIODIC | TIMER_C_508KHZ) +# define TIMER_EOI TIMER_EOI1 +# define TIMER_IRQ IRQ_T1UI +#else +# define TIMER_CONTROL TIMER_CONTROL3 +# define TIMER_LOAD TIMER_LOAD3 +# define TIMER_CONSTANT (3686400/HZ) +# define TIMER_MODE (TIMER_C_ENABLE | TIMER_C_PERIODIC) +# define TIMER_EOI TIMER_EOI3 +# define TIMER_IRQ IRQ_T3UI +#endif + +static irqreturn_t +lh7a40x_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + TIMER_EOI = 0; + do_profile (regs); + do_leds(); + do_set_rtc(); + do_timer (regs); + + return IRQ_HANDLED; +} + +void __init time_init(void) +{ + /* Stop/disable all timers */ + TIMER_CONTROL1 = 0; + TIMER_CONTROL2 = 0; + TIMER_CONTROL3 = 0; + + timer_irq.handler = lh7a40x_timer_interrupt; + timer_irq.flags |= SA_INTERRUPT; + setup_irq (TIMER_IRQ, &timer_irq); + + TIMER_LOAD = TIMER_CONSTANT; + TIMER_CONTROL = TIMER_MODE; +} + diff --git a/include/asm-arm/arch-lh7a40x/timex.h b/include/asm-arm/arch-lh7a40x/timex.h new file mode 100644 index 000000000000..e9c296ec5961 --- /dev/null +++ b/include/asm-arm/arch-lh7a40x/timex.h @@ -0,0 +1,18 @@ +/* include/asm-arm/arch-lh7a40x/timex.h + * + * Copyright (C) 2004 Coastal Environmental Systems + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +#include <asm/arch/constants.h> + +#define CLOCK_TICK_RATE (PLL_CLOCK/6/16) + +/* +#define CLOCK_TICK_RATE 3686400 +#define CLOCK_TICK_FACTOR 80 +*/ diff --git a/include/asm-arm/arch-lh7a40x/uncompress.h b/include/asm-arm/arch-lh7a40x/uncompress.h new file mode 100644 index 000000000000..c31796f78592 --- /dev/null +++ b/include/asm-arm/arch-lh7a40x/uncompress.h @@ -0,0 +1,43 @@ +/* include/asm-arm/arch-lh7a40x/uncompress.h + * + * Copyright (C) 2004 Coastal Environmental Systems + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +#include <asm/arch/registers.h> + +#ifndef UART_R_DATA +# define UART_R_DATA (0x00) +#endif +#ifndef UART_R_STATUS +# define UART_R_STATUS (0x10) +#endif +#define nTxRdy (0x20) /* Not TxReady (literally Tx FIFO full) */ + + /* Access UART with physical addresses before MMU is setup */ +#define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS)) +#define UART_DATA (*(volatile unsigned long*) (UART2_PHYS + UART_R_DATA)) + +static __inline__ void putc (char ch) +{ + while (UART_STATUS & nTxRdy) + ; + UART_DATA = ch; +} + +static void puts (const char* sz) +{ + for (; *sz; ++sz) { + putc (*sz); + if (*sz == '\n') + putc ('\r'); + } +} + + /* NULL functions; we don't presently need them */ +#define arch_decomp_setup() +#define arch_decomp_wdog() diff --git a/include/asm-arm/arch-lh7a40x/vmalloc.h b/include/asm-arm/arch-lh7a40x/vmalloc.h new file mode 100644 index 000000000000..5ac607925bea --- /dev/null +++ b/include/asm-arm/arch-lh7a40x/vmalloc.h @@ -0,0 +1,21 @@ +/* include/asm-arm/arch-lh7a40x/vmalloc.h + * + * Copyright (C) 2004 Coastal Environmental Systems + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +/* + * Just any arbitrary offset to the start of the vmalloc VM area: the + * current 8MB value just means that there will be a 8MB "hole" after + * the physical memory until the kernel virtual memory starts. That + * means that any out-of-bounds memory accesses will hopefully be + * caught. The vmalloc() routines leaves a hole of 4kB (one page) + * between each vmalloced area for the same reason. ;) + */ +#define VMALLOC_OFFSET (8*1024*1024) +#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) +#define VMALLOC_END (0xe8000000) diff --git a/include/asm-arm/arch-omap/board-h2.h b/include/asm-arm/arch-omap/board-h2.h new file mode 100644 index 000000000000..fe2c06ddedbf --- /dev/null +++ b/include/asm-arm/arch-omap/board-h2.h @@ -0,0 +1,35 @@ +/* + * linux/include/asm-arm/arch-omap/board-h2.h + * + * Hardware definitions for TI OMAP1610 H2 board. + * + * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_ARCH_OMAP_H2_H +#define __ASM_ARCH_OMAP_H2_H + +/* Placeholder for H2 specific defines */ + +#endif /* __ASM_ARCH_OMAP_H2_H */ + diff --git a/include/asm-arm/arch-omap/board-h3.h b/include/asm-arm/arch-omap/board-h3.h new file mode 100644 index 000000000000..f08276f89652 --- /dev/null +++ b/include/asm-arm/arch-omap/board-h3.h @@ -0,0 +1,35 @@ +/* + * linux/include/asm-arm/arch-omap/board-h3.h + * + * Hardware definitions for TI OMAP1610 H3 board. + * + * Initial creation by Dirk Behme <dirk.behme@de.bosch.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_ARCH_OMAP_H3_H +#define __ASM_ARCH_OMAP_H3_H + +/* Placeholder for H3 specific defines */ + +#endif /* __ASM_ARCH_OMAP_H3_H */ + diff --git a/include/asm-arm/arch-omap/board-h4.h b/include/asm-arm/arch-omap/board-h4.h new file mode 100644 index 000000000000..eb2a5d81a5d6 --- /dev/null +++ b/include/asm-arm/arch-omap/board-h4.h @@ -0,0 +1,35 @@ +/* + * linux/include/asm-arm/arch-omap/board-h4.h + * + * Hardware definitions for TI OMAP1610 H4 board. + * + * Initial creation by Dirk Behme <dirk.behme@de.bosch.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_ARCH_OMAP_H4_H +#define __ASM_ARCH_OMAP_H4_H + +/* Placeholder for H4 specific defines */ + +#endif /* __ASM_ARCH_OMAP_H4_H */ + diff --git a/include/asm-arm/arch-omap/board-innovator.h b/include/asm-arm/arch-omap/board-innovator.h new file mode 100644 index 000000000000..beb50550fdd6 --- /dev/null +++ b/include/asm-arm/arch-omap/board-innovator.h @@ -0,0 +1,202 @@ +/* + * linux/include/asm-arm/arch-omap/board-innovator.h + * + * Copyright (C) 2001 RidgeRun, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef __ASM_ARCH_OMAP_INNOVATOR_H +#define __ASM_ARCH_OMAP_INNOVATOR_H + +#if defined (CONFIG_ARCH_OMAP1510) + +/* + * --------------------------------------------------------------------------- + * OMAP-1510 FPGA + * --------------------------------------------------------------------------- + */ +#define OMAP1510P1_FPGA_BASE 0xE8000000 /* Virtual */ +#define OMAP1510P1_FPGA_SIZE SZ_4K +#define OMAP1510P1_FPGA_START 0x08000000 /* Physical */ + +/* Revision */ +#define OMAP1510P1_FPGA_REV_LOW (OMAP1510P1_FPGA_BASE + 0x0) +#define OMAP1510P1_FPGA_REV_HIGH (OMAP1510P1_FPGA_BASE + 0x1) + +#define OMAP1510P1_FPGA_LCD_PANEL_CONTROL (OMAP1510P1_FPGA_BASE + 0x2) +#define OMAP1510P1_FPGA_LED_DIGIT (OMAP1510P1_FPGA_BASE + 0x3) +#define INNOVATOR_FPGA_HID_SPI (OMAP1510P1_FPGA_BASE + 0x4) +#define OMAP1510P1_FPGA_POWER (OMAP1510P1_FPGA_BASE + 0x5) + +/* Interrupt status */ +#define OMAP1510P1_FPGA_ISR_LO (OMAP1510P1_FPGA_BASE + 0x6) +#define OMAP1510P1_FPGA_ISR_HI (OMAP1510P1_FPGA_BASE + 0x7) + +/* Interrupt mask */ +#define OMAP1510P1_FPGA_IMR_LO (OMAP1510P1_FPGA_BASE + 0x8) +#define OMAP1510P1_FPGA_IMR_HI (OMAP1510P1_FPGA_BASE + 0x9) + +/* Reset registers */ +#define OMAP1510P1_FPGA_HOST_RESET (OMAP1510P1_FPGA_BASE + 0xa) +#define OMAP1510P1_FPGA_RST (OMAP1510P1_FPGA_BASE + 0xb) + +#define OMAP1510P1_FPGA_AUDIO (OMAP1510P1_FPGA_BASE + 0xc) +#define OMAP1510P1_FPGA_DIP (OMAP1510P1_FPGA_BASE + 0xe) +#define OMAP1510P1_FPGA_FPGA_IO (OMAP1510P1_FPGA_BASE + 0xf) +#define OMAP1510P1_FPGA_UART1 (OMAP1510P1_FPGA_BASE + 0x14) +#define OMAP1510P1_FPGA_UART2 (OMAP1510P1_FPGA_BASE + 0x15) +#define OMAP1510P1_FPGA_OMAP1510_STATUS (OMAP1510P1_FPGA_BASE + 0x16) +#define OMAP1510P1_FPGA_BOARD_REV (OMAP1510P1_FPGA_BASE + 0x18) +#define OMAP1510P1_PPT_DATA (OMAP1510P1_FPGA_BASE + 0x100) +#define OMAP1510P1_PPT_STATUS (OMAP1510P1_FPGA_BASE + 0x101) +#define OMAP1510P1_PPT_CONTROL (OMAP1510P1_FPGA_BASE + 0x102) + +#define OMAP1510P1_FPGA_TOUCHSCREEN (OMAP1510P1_FPGA_BASE + 0x204) + +#define INNOVATOR_FPGA_INFO (OMAP1510P1_FPGA_BASE + 0x205) +#define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510P1_FPGA_BASE + 0x206) +#define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510P1_FPGA_BASE + 0x207) +#define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510P1_FPGA_BASE + 0x208) +#define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510P1_FPGA_BASE + 0x209) +#define INNOVATOR_FPGA_LED_RED_LO (OMAP1510P1_FPGA_BASE + 0x20a) +#define INNOVATOR_FPGA_LED_RED_HI (OMAP1510P1_FPGA_BASE + 0x20b) +#define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510P1_FPGA_BASE + 0x20c) +#define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510P1_FPGA_BASE + 0x20d) +#define INNOVATOR_FPGA_ISR2 (OMAP1510P1_FPGA_BASE + 0x20e) +#define INNOVATOR_FPGA_IMR2 (OMAP1510P1_FPGA_BASE + 0x210) + +#define OMAP1510P1_FPGA_ETHR_START (OMAP1510P1_FPGA_START + 0x300) +#define OMAP1510P1_FPGA_ETHR_BASE (OMAP1510P1_FPGA_BASE + 0x300) + +/* + * Power up Giga UART driver, turn on HID clock. + * Turn off BT power, since we're not using it and it + * draws power. + */ +#define OMAP1510P1_FPGA_RESET_VALUE 0x42 + +#define OMAP1510P1_FPGA_PCR_IF_PD0 (1 << 7) +#define OMAP1510P1_FPGA_PCR_COM2_EN (1 << 6) +#define OMAP1510P1_FPGA_PCR_COM1_EN (1 << 5) +#define OMAP1510P1_FPGA_PCR_EXP_PD0 (1 << 4) +#define OMAP1510P1_FPGA_PCR_EXP_PD1 (1 << 3) +#define OMAP1510P1_FPGA_PCR_48MHZ_CLK (1 << 2) +#define OMAP1510P1_FPGA_PCR_4MHZ_CLK (1 << 1) +#define OMAP1510P1_FPGA_PCR_RSRVD_BIT0 (1 << 0) + +/* + * Innovator/OMAP1510 FPGA HID register bit definitions + */ +#define FPGA_HID_SCLK (1<<0) /* output */ +#define FPGA_HID_MOSI (1<<1) /* output */ +#define FPGA_HID_nSS (1<<2) /* output 0/1 chip idle/select */ +#define FPGA_HID_nHSUS (1<<3) /* output 0/1 host active/suspended */ +#define FPGA_HID_MISO (1<<4) /* input */ +#define FPGA_HID_ATN (1<<5) /* input 0/1 chip idle/ATN */ +#define FPGA_HID_rsrvd (1<<6) +#define FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */ + +#ifndef OMAP_SDRAM_DEVICE +#define OMAP_SDRAM_DEVICE D256M_1X16_4B +#endif + +#define OMAP1510P1_IMIF_PRI_VALUE 0x00 +#define OMAP1510P1_EMIFS_PRI_VALUE 0x00 +#define OMAP1510P1_EMIFF_PRI_VALUE 0x00 + +/* + * These definitions define an area of FLASH set aside + * for the use of MTD/JFFS2. This is the area of flash + * that a JFFS2 filesystem will reside which is mounted + * at boot with the "root=/dev/mtdblock/0 rw" + * command line option. The flash address used here must + * fall within the legal range defined by rrload for storing + * the filesystem component. This address will be sufficiently + * deep into the overall flash range to avoid the other + * components also stored in flash such as the bootloader, + * the bootloader params, and the kernel. + * The SW2 settings for the map below are: + * 1 off, 2 off, 3 on, 4 off. + */ + +/* Intel flash_0, partitioned as expected by rrload */ +#define OMAP_FLASH_0_BASE 0xD8000000 +#define OMAP_FLASH_0_START 0x00000000 +#define OMAP_FLASH_0_SIZE SZ_16M + +/* Intel flash_1, used for cramfs or other flash file systems */ +#define OMAP_FLASH_1_BASE 0xD9000000 +#define OMAP_FLASH_1_START 0x01000000 +#define OMAP_FLASH_1_SIZE SZ_16M + +/* The FPGA IRQ is cascaded through GPIO_13 */ +#define INT_FPGA (IH_GPIO_BASE + 13) + +/* IRQ Numbers for interrupts muxed through the FPGA */ +#define IH_FPGA_BASE IH_BOARD_BASE +#define INT_FPGA_ATN (IH_FPGA_BASE + 0) +#define INT_FPGA_ACK (IH_FPGA_BASE + 1) +#define INT_FPGA2 (IH_FPGA_BASE + 2) +#define INT_FPGA3 (IH_FPGA_BASE + 3) +#define INT_FPGA4 (IH_FPGA_BASE + 4) +#define INT_FPGA5 (IH_FPGA_BASE + 5) +#define INT_FPGA6 (IH_FPGA_BASE + 6) +#define INT_FPGA7 (IH_FPGA_BASE + 7) +#define INT_FPGA8 (IH_FPGA_BASE + 8) +#define INT_FPGA9 (IH_FPGA_BASE + 9) +#define INT_FPGA10 (IH_FPGA_BASE + 10) +#define INT_FPGA11 (IH_FPGA_BASE + 11) +#define INT_FPGA12 (IH_FPGA_BASE + 12) +#define INT_ETHER (IH_FPGA_BASE + 13) +#define INT_FPGAUART1 (IH_FPGA_BASE + 14) +#define INT_FPGAUART2 (IH_FPGA_BASE + 15) +#define INT_FPGA_TS (IH_FPGA_BASE + 16) +#define INT_FPGA17 (IH_FPGA_BASE + 17) +#define INT_FPGA_CAM (IH_FPGA_BASE + 18) +#define INT_FPGA_RTC_A (IH_FPGA_BASE + 19) +#define INT_FPGA_RTC_B (IH_FPGA_BASE + 20) +#define INT_FPGA_CD (IH_FPGA_BASE + 21) +#define INT_FPGA22 (IH_FPGA_BASE + 22) +#define INT_FPGA23 (IH_FPGA_BASE + 23) + +#define NR_FPGA_IRQS 24 + +#ifndef __ASSEMBLY__ +void fpga_write(unsigned char val, int reg); +unsigned char fpga_read(int reg); +#endif + +#endif /* CONFIG_ARCH_OMAP1510 */ + +#if defined (CONFIG_ARCH_OMAP1610) + +/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ +#define OMAP1610_ETHR_BASE 0xE8000000 +#define OMAP1610_ETHR_SIZE SZ_4K +#define OMAP1610_ETHR_START 0x04000000 + +/* Intel STRATA NOR flash at CS3 */ +#define OMAP1610_NOR_FLASH_BASE 0xD8000000 +#define OMAP1610_NOR_FLASH_SIZE SZ_32M +#define OMAP1610_NOR_FLASH_START 0x0C000000 + +#endif /* CONFIG_ARCH_OMAP1610 */ +#endif /* __ASM_ARCH_OMAP_INNOVATOR_H */ diff --git a/include/asm-arm/arch-omap/board-osk.h b/include/asm-arm/arch-omap/board-osk.h new file mode 100644 index 000000000000..839928da4620 --- /dev/null +++ b/include/asm-arm/arch-omap/board-osk.h @@ -0,0 +1,43 @@ +/* + * linux/include/asm-arm/arch-omap/board-osk.h + * + * Hardware definitions for TI OMAP5912 OSK board. + * + * Written by Dirk Behme <dirk.behme@de.bosch.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_ARCH_OMAP_OSK_H +#define __ASM_ARCH_OMAP_OSK_H + +/* At OMAP5912 OSK the Ethernet is directly connected to CS1 */ +#define OMAP_OSK_ETHR_BASE 0xE8800000 +#define OMAP_OSK_ETHR_SIZE SZ_4K +#define OMAP_OSK_ETHR_START 0x04800000 + +/* Micron NOR flash at CS3 mapped to address 0x0 if BM bit is 1 */ +#define OMAP_OSK_NOR_FLASH_BASE 0xD8000000 +#define OMAP_OSK_NOR_FLASH_SIZE SZ_32M +#define OMAP_OSK_NOR_FLASH_START 0x00000000 + +#endif /* __ASM_ARCH_OMAP_OSK_H */ + diff --git a/include/asm-arm/arch-omap/board-perseus2.h b/include/asm-arm/arch-omap/board-perseus2.h new file mode 100644 index 000000000000..4839c44511c0 --- /dev/null +++ b/include/asm-arm/arch-omap/board-perseus2.h @@ -0,0 +1,107 @@ +/* + * linux/include/asm-arm/arch-omap/board-perseus2.h + * + * Copyright 2003 by Texas Instruments Incorporated + * OMAP730 / P2-sample additions + * Author: Jean Pihet + * + * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com) + * Author: RidgeRun, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef __ASM_ARCH_OMAP_P2SAMPLE_H +#define __ASM_ARCH_OMAP_P2SAMPLE_H + +#if defined(CONFIG_ARCH_OMAP730) && defined (CONFIG_MACH_OMAP_PERSEUS2) + +/* + * NOTE: ALL DEFINITIONS IN THIS FILE NEED TO BE PREFIXED BY IDENTIFIER + * P2SAMPLE_ since they are specific to the EVM and not the chip. + */ + +/* --------------------------------------------------------------------------- + * OMAP730 Debug Board FPGA + * --------------------------------------------------------------------------- + */ + +/* maps in the FPGA registers and the ETHR registers */ +#define OMAP730_FPGA_BASE 0xE8000000 /* VA */ +#define OMAP730_FPGA_SIZE SZ_4K /* SIZE */ +#define OMAP730_FPGA_START 0x04000000 /* PA */ + +#define OMAP730_FPGA_ETHR_START OMAP730_FPGA_START +#define OMAP730_FPGA_ETHR_BASE OMAP730_FPGA_BASE +#define OMAP730_FPGA_FPGA_REV (OMAP730_FPGA_BASE + 0x10) /* FPGA Revision */ +#define OMAP730_FPGA_BOARD_REV (OMAP730_FPGA_BASE + 0x12) /* Board Revision */ +#define OMAP730_FPGA_GPIO (OMAP730_FPGA_BASE + 0x14) /* GPIO outputs */ +#define OMAP730_FPGA_LEDS (OMAP730_FPGA_BASE + 0x16) /* LEDs outputs */ +#define OMAP730_FPGA_MISC_INPUTS (OMAP730_FPGA_BASE + 0x18) /* Misc inputs */ +#define OMAP730_FPGA_LAN_STATUS (OMAP730_FPGA_BASE + 0x1A) /* LAN Status line */ +#define OMAP730_FPGA_LAN_RESET (OMAP730_FPGA_BASE + 0x1C) /* LAN Reset line */ + +// LEDs definition on debug board (16 LEDs) +#define OMAP730_FPGA_LED_CLAIMRELEASE (1 << 15) +#define OMAP730_FPGA_LED_STARTSTOP (1 << 14) +#define OMAP730_FPGA_LED_HALTED (1 << 13) +#define OMAP730_FPGA_LED_IDLE (1 << 12) +#define OMAP730_FPGA_LED_TIMER (1 << 11) +// cpu0 load-meter LEDs +#define OMAP730_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ... +#define OMAP730_FPGA_LOAD_METER_SIZE 11 +#define OMAP730_FPGA_LOAD_METER_MASK ((1 << OMAP730_FPGA_LOAD_METER_SIZE) - 1) + +#ifndef OMAP_SDRAM_DEVICE +#define OMAP_SDRAM_DEVICE D256M_1X16_4B +#endif + +/* + * These definitions define an area of FLASH set aside + * for the use of MTD/JFFS2. This is the area of flash + * that a JFFS2 filesystem will reside which is mounted + * at boot with the "root=/dev/mtdblock/0 rw" + * command line option. + */ + +/* Intel flash_0, partitioned as expected by rrload */ +#define OMAP_FLASH_0_BASE 0xD8000000 /* VA */ +#define OMAP_FLASH_0_START 0x00000000 /* PA */ +#define OMAP_FLASH_0_SIZE SZ_32M + +/* The Ethernet Controller IRQ is cascaded to MPU_EXT_nIRQ througb the FPGA */ +#define INT_ETHER INT_730_MPU_EXT_NIRQ + +#define MAXIRQNUM IH_BOARD_BASE +#define MAXFIQNUM MAXIRQNUM +#define MAXSWINUM MAXIRQNUM + +#define NR_IRQS (MAXIRQNUM + 1) + +#ifndef __ASSEMBLY__ +void fpga_write(unsigned char val, int reg); +unsigned char fpga_read(int reg); +#endif + +#else +#error "Only OMAP730 Perseus2 supported!" +#endif + +#endif diff --git a/include/asm-arm/arch-omap/board.h b/include/asm-arm/arch-omap/board.h new file mode 100644 index 000000000000..fe21fc817749 --- /dev/null +++ b/include/asm-arm/arch-omap/board.h @@ -0,0 +1,48 @@ +/* + * linux/include/asm-arm/arch-omap/board.h + * + * Information structures for board-specific data + * + * Copyright (C) 2004 Nokia Corporation + * Written by Juha Yrjölä <juha.yrjola@nokia.com> + */ + +#ifndef _OMAP_BOARD_H +#define _OMAP_BOARD_H + +#include <linux/config.h> +#include <linux/types.h> + +/* Different peripheral ids */ +#define OMAP_TAG_CLOCK 0x4f01 +#define OMAP_TAG_MMC 0x4f02 +#define OMAP_TAG_UART 0x4f03 + +struct omap_clock_info { + /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */ + u8 system_clock_type; +}; + +struct omap_mmc_info { + u8 mmc_blocks; + s8 mmc1_power_pin, mmc2_power_pin; + s8 mmc1_switch_pin, mmc2_switch_pin; +}; + +struct omap_uart_info { + u8 console_uart; + u32 console_speed; +}; + +struct omap_board_info_entry { + u16 tag; + u16 len; + u8 data[0]; +}; + +extern const void *__omap_get_per_info(u16 tag, size_t len); + +#define omap_get_per_info(tag, type) \ + ((const type *) __omap_get_per_info((tag), sizeof(type))) + +#endif diff --git a/include/asm-arm/arch-omap/bus.h b/include/asm-arm/arch-omap/bus.h index 310b682a6418..ff3594797387 100644 --- a/include/asm-arm/arch-omap/bus.h +++ b/include/asm-arm/arch-omap/bus.h @@ -43,6 +43,7 @@ struct omap_dev { void *mapbase; /* OMAP physical address */ unsigned int irq[6]; /* OMAP interrupts */ u64 *dma_mask; /* Used by USB OHCI only */ + u64 coherent_dma_mask; /* Used by USB OHCI only */ }; #define OMAP_DEV(_d) container_of((_d), struct omap_dev, dev) diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h index 94e202f1a87c..826539d69f91 100644 --- a/include/asm-arm/arch-omap/hardware.h +++ b/include/asm-arm/arch-omap/hardware.h @@ -47,66 +47,42 @@ * I/O mapping * ---------------------------------------------------------------------------- */ -#define IO_BASE 0xFFFB0000 /* Virtual */ +#define IO_PHYS 0xFFFB0000 +#define IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */ +#define IO_VIRT (IO_PHYS - IO_OFFSET) #define IO_SIZE 0x40000 -#define IO_START 0xFFFB0000 /* Physical */ +#define IO_ADDRESS(x) ((x) - IO_OFFSET) #define PCIO_BASE 0 -#define IO_ADDRESS(x) ((x)) +#define io_p2v(x) ((x) - IO_OFFSET) +#define io_v2p(x) ((x) + IO_OFFSET) -/* - * --------------------------------------------------------------------------- - * Processor differentiation - * --------------------------------------------------------------------------- - */ +#ifndef __ASSEMBLER__ -#ifdef CONFIG_ARCH_OMAP730 -#include "omap730.h" -#define cpu_is_omap730() (1) -#else -#define cpu_is_omap730() (0) -#endif +/* 16 bit uses LDRH/STRH, base +/- offset_8 */ +typedef struct { volatile u16 offset[256]; } __regbase16; +#define __REGV16(vaddr) ((__regbase16 *)((vaddr)&~0xff)) \ + ->offset[((vaddr)&0xff)>>1] +#define __REG16(paddr) __REGV16(io_p2v(paddr)) -#ifdef CONFIG_ARCH_OMAP1510 -#include "omap1510.h" -#define cpu_is_omap1510() (1) -#else -#define cpu_is_omap1510() (0) -#endif +/* 8/32 bit uses LDR/STR, base +/- offset_12 */ +typedef struct { volatile u8 offset[4096]; } __regbase8; +#define __REGV8(vaddr) ((__regbase8 *)((paddr)&~4095)) \ + ->offset[((paddr)&4095)>>0] +#define __REG8(paddr) __REGV8(io_p2v(paddr)) -#ifdef CONFIG_ARCH_OMAP1610 -#include "omap1610.h" -#define cpu_is_omap1610() (1) -#else -#define cpu_is_omap1610() (0) -#endif +typedef struct { volatile u32 offset[4096]; } __regbase32; +#define __REGV32(vaddr) ((__regbase32 *)((vaddr)&~4095)) \ + ->offset[((vaddr)&4095)>>2] +#define __REG32(paddr) __REGV32(io_p2v(paddr)) -/* - * --------------------------------------------------------------------------- - * Board differentiation - * --------------------------------------------------------------------------- - */ - -#ifdef CONFIG_OMAP_INNOVATOR -#include "omap-innovator.h" -#define omap_is_innovator() (1) #else -#define omap_is_innovator() (0) -#endif -#ifdef CONFIG_MACH_OMAP_H2 -#include "omap-h2.h" -#define omap_is_h2() (1) -#else -#define omap_is_h2() (0) -#endif +#define __REG8(paddr) io_p2v(paddr) +#define __REG16(paddr) io_p2v(paddr) +#define __REG32(paddr) io_p2v(paddr) -#ifdef CONFIG_MACH_OMAP_PERSEUS2 -#include "omap-perseus2.h" -#define omap_is_perseus2() (1) -#else -#define omap_is_perseus2() (0) #endif /* @@ -119,33 +95,17 @@ /* * ---------------------------------------------------------------------------- - * Base addresses - * ---------------------------------------------------------------------------- - */ - -/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ - -#define OMAP_DSP_BASE 0xE0000000 -#define OMAP_DSP_SIZE 0x50000 -#define OMAP_DSP_START 0xE0000000 - -#define OMAP_DSPREG_BASE 0xE1000000 -#define OMAP_DSPREG_SIZE SZ_128K -#define OMAP_DSPREG_START 0xE1000000 - -/* - * ---------------------------------------------------------------------------- * Clocks * ---------------------------------------------------------------------------- */ #define CLKGEN_RESET_BASE (0xfffece00) -#define ARM_CKCTL (volatile __u16 *)(CLKGEN_RESET_BASE + 0x0) -#define ARM_IDLECT1 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x4) -#define ARM_IDLECT2 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x8) -#define ARM_EWUPCT (volatile __u16 *)(CLKGEN_RESET_BASE + 0xC) -#define ARM_RSTCT1 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x10) -#define ARM_RSTCT2 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x14) -#define ARM_SYSST (volatile __u16 *)(CLKGEN_RESET_BASE + 0x18) +#define ARM_CKCTL (CLKGEN_RESET_BASE + 0x0) +#define ARM_IDLECT1 (CLKGEN_RESET_BASE + 0x4) +#define ARM_IDLECT2 (CLKGEN_RESET_BASE + 0x8) +#define ARM_EWUPCT (CLKGEN_RESET_BASE + 0xC) +#define ARM_RSTCT1 (CLKGEN_RESET_BASE + 0x10) +#define ARM_RSTCT2 (CLKGEN_RESET_BASE + 0x14) +#define ARM_SYSST (CLKGEN_RESET_BASE + 0x18) #define CK_RATEF 1 #define CK_IDLEF 2 @@ -154,19 +114,19 @@ #define SETARM_IDLE_SHIFT /* DPLL control registers */ -#define DPLL_CTL_REG (volatile __u16 *)(0xfffecf00) -#define CK_DPLL1 (volatile __u16 *)(0xfffecf00) +#define DPLL_CTL_REG (0xfffecf00) +#define CK_DPLL1 (0xfffecf00) /* ULPD */ #define ULPD_REG_BASE (0xfffe0800) -#define ULPD_IT_STATUS_REG (volatile __u16 *)(ULPD_REG_BASE + 0x14) -#define ULPD_CLOCK_CTRL_REG (volatile __u16 *)(ULPD_REG_BASE + 0x30) -#define ULPD_SOFT_REQ_REG (volatile __u16 *)(ULPD_REG_BASE + 0x34) -#define ULPD_DPLL_CTRL_REG (volatile __u16 *)(ULPD_REG_BASE + 0x3c) -#define ULPD_STATUS_REQ_REG (volatile __u16 *)(ULPD_REG_BASE + 0x40) -#define ULPD_APLL_CTRL_REG (volatile __u16 *)(ULPD_REG_BASE + 0x4c) -#define ULPD_POWER_CTRL_REG (volatile __u16 *)(ULPD_REG_BASE + 0x50) -#define ULPD_CAM_CLK_CTRL_REG (volatile __u16 *)(ULPD_REG_BASE + 0x7c) +#define ULPD_IT_STATUS_REG (ULPD_REG_BASE + 0x14) +#define ULPD_CLOCK_CTRL_REG (ULPD_REG_BASE + 0x30) +#define ULPD_SOFT_REQ_REG (ULPD_REG_BASE + 0x34) +#define ULPD_DPLL_CTRL_REG (ULPD_REG_BASE + 0x3c) +#define ULPD_STATUS_REQ_REG (ULPD_REG_BASE + 0x40) +#define ULPD_APLL_CTRL_REG (ULPD_REG_BASE + 0x4c) +#define ULPD_POWER_CTRL_REG (ULPD_REG_BASE + 0x50) +#define ULPD_CAM_CLK_CTRL_REG (ULPD_REG_BASE + 0x7c) /* * --------------------------------------------------------------------------- @@ -261,6 +221,7 @@ * ---------------------------------------------------------------------------- */ #define MOD_CONF_CTRL_0 0xfffe1080 +#define MOD_CONF_CTRL_1 0xfffe1110 /* * ---------------------------------------------------------------------------- @@ -315,13 +276,89 @@ * ---------------------------------------------------------------------------- */ /* MPUI Interface Registers */ -#define MPUI_CTRL_REG (volatile __u32 *)(0xfffec900) -#define MPUI_DEBUG_ADDR (volatile __u32 *)(0xfffec904) -#define MPUI_DEBUG_DATA (volatile __u32 *)(0xfffec908) -#define MPUI_DEBUG_FLAG (volatile __u16 *)(0xfffec90c) -#define MPUI_STATUS_REG (volatile __u16 *)(0xfffec910) -#define MPUI_DSP_STATUS_REG (volatile __u16 *)(0xfffec914) -#define MPUI_DSP_BOOT_CONFIG (volatile __u16 *)(0xfffec918) -#define MPUI_DSP_API_CONFIG (volatile __u16 *)(0xfffec91c) +#define MPUI_CTRL_REG (0xfffec900) +#define MPUI_DEBUG_ADDR (0xfffec904) +#define MPUI_DEBUG_DATA (0xfffec908) +#define MPUI_DEBUG_FLAG (0xfffec90c) +#define MPUI_STATUS_REG (0xfffec910) +#define MPUI_DSP_STATUS_REG (0xfffec914) +#define MPUI_DSP_BOOT_CONFIG (0xfffec918) +#define MPUI_DSP_API_CONFIG (0xfffec91c) + + +#ifndef __ASSEMBLER__ + +/* + * --------------------------------------------------------------------------- + * Processor differentiation + * --------------------------------------------------------------------------- + */ +#define OMAP_ID_REG __REG32(0xfffed404) + +#ifdef CONFIG_ARCH_OMAP730 +#include "omap730.h" +#define cpu_is_omap730() (((OMAP_ID_REG >> 12) & 0xffff) == 0xB55F) +#else +#define cpu_is_omap730() 0 +#endif + +#ifdef CONFIG_ARCH_OMAP1510 +#include "omap1510.h" +#define cpu_is_omap1510() (((OMAP_ID_REG >> 12) & 0xffff) == 0xB470) +#else +#define cpu_is_omap1510() 0 +#endif + +#ifdef CONFIG_ARCH_OMAP1610 +#include "omap1610.h" +#define cpu_is_omap1710() (((OMAP_ID_REG >> 12) & 0xffff) == 0xB5F7) +/* Detect 1710 as 1610 for now */ +#define cpu_is_omap1610() (((OMAP_ID_REG >> 12) & 0xffff) == 0xB576 || \ + cpu_is_omap1710()) +#else +#define cpu_is_omap1610() 0 +#define cpu_is_omap1710() 0 +#endif + +#ifdef CONFIG_ARCH_OMAP5912 +#include "omap5912.h" +#define cpu_is_omap5912() (((OMAP_ID_REG >> 12) & 0xffff) == 0xB58C) +#else +#define cpu_is_omap5912() 0 +#endif + +/* + * --------------------------------------------------------------------------- + * Board differentiation + * --------------------------------------------------------------------------- + */ + +#ifdef CONFIG_MACH_OMAP_INNOVATOR +#include "board-innovator.h" +#endif + +#ifdef CONFIG_MACH_OMAP_H2 +#include "board-h2.h" +#endif + +#ifdef CONFIG_MACH_OMAP_PERSEUS2 +#include "board-perseus2.h" +#endif + +#ifdef CONFIG_MACH_OMAP_H3 +#include "board-h3.h" +#error "Support for H3 board not yet implemented." +#endif + +#ifdef CONFIG_MACH_OMAP_H4 +#include "board-h4.h" +#error "Support for H4 board not yet implemented." +#endif + +#ifdef CONFIG_MACH_OMAP_OSK +#include "board-osk.h" +#endif + +#endif /* !__ASSEMBLER__ */ #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h index c517c61c543e..86c1cb3fbcd3 100644 --- a/include/asm-arm/arch-omap/io.h +++ b/include/asm-arm/arch-omap/io.h @@ -21,4 +21,21 @@ #define __mem_pci(a) ((unsigned long)(a)) #define __mem_isa(a) ((unsigned long)(a)) +/* + * Functions to access the OMAP IO region + * + * NOTE: - Use omap_read/write[bwl] for physical register addresses + * - Use __raw_read/write[bwl]() for virtual register addresses + * - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses + * - DO NOT use hardcoded virtual addresses to allow changing the + * IO address space again if needed + */ +#define omap_readb(a) (*(volatile unsigned char *)IO_ADDRESS(a)) +#define omap_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a)) +#define omap_readl(a) (*(volatile unsigned int *)IO_ADDRESS(a)) + +#define omap_writeb(v,a) (*(volatile unsigned char *)IO_ADDRESS(a) = (v)) +#define omap_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) +#define omap_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v)) + #endif diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h index af24a4756db2..7cf577496b66 100644 --- a/include/asm-arm/arch-omap/irqs.h +++ b/include/asm-arm/arch-omap/irqs.h @@ -259,4 +259,8 @@ extern void omap_init_irq(void); */ #include <asm/arch/hardware.h> +#ifndef NR_IRQS +#define NR_IRQS 256 +#endif + #endif diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h index 5c8ea6f86212..b1a0a6f9a8e0 100644 --- a/include/asm-arm/arch-omap/mux.h +++ b/include/asm-arm/arch-omap/mux.h @@ -40,7 +40,8 @@ #ifndef __ASM_ARCH_MUX_H #define __ASM_ARCH_MUX_H -#define PU_PD_SEL_NA 0 /* No pu_pd reg availabe */ +#define PU_PD_SEL_NA 0 /* No pu_pd reg available */ +#define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */ #define DEBUG_MUX @@ -278,9 +279,12 @@ typedef enum { E19_1610_KBR4, N19_1610_KBR5, + /* Power management */ + T20_1610_LOW_PWR, + } reg_cfg_t; -#ifdef __MUX_C__ +#if defined(__MUX_C__) && defined(CONFIG_OMAP_MUX) /* * Table of various FUNC_MUX and PULL_DWN combinations for each device. @@ -401,14 +405,14 @@ MUX_CFG("U18_1610_UWIRE_SDI", 8, 0, 0, 1, 18, 0, 1, 1, 1) MUX_CFG("W21_1610_UWIRE_SDO", 8, 3, 0, 1, 19, 0, 1, 1, 1) MUX_CFG("N14_1610_UWIRE_CS0", 8, 9, 1, 1, 21, 0, 1, 1, 1) MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1) -MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 0, 0, 0, 0, 0, 0) +MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, NA, 0, 0, NA, 0, 0) /* First MMC interface, same on 1510 and 1610 */ MUX_CFG("MMC_CMD", A, 27, 0, 2, 15, 1, 2, 1, 1) MUX_CFG("MMC_DAT1", A, 24, 0, 2, 14, 1, 2, 1, 1) MUX_CFG("MMC_DAT2", A, 18, 0, 2, 12, 1, 2, 1, 1) MUX_CFG("MMC_DAT0", B, 0, 0, 2, 16, 1, 2, 1, 1) -MUX_CFG("MMC_CLK", A, 21, 0, 0, 0, 0, 0, 0, 1) +MUX_CFG("MMC_CLK", A, 21, 0, NA, 0, 0, NA, 0, 1) MUX_CFG("MMC_DAT3", 10, 15, 0, 3, 8, 1, 3, 1, 1) /* OMAP-1610 USB0 alternate configuration */ @@ -422,12 +426,12 @@ MUX_CFG("V9_USB0_SPEED", B, 12, 5, 2, 20, 0, 2, 0, 1) MUX_CFG("Y10_USB0_SUSP", B, 3, 5, 2, 17, 0, 2, 0, 1) /* USB2 interface */ -MUX_CFG("W9_USB2_TXEN", B, 9, 1, 0, 0, 0, NA, 0, 1) -MUX_CFG("AA9_USB2_VP", B, 6, 1, 0, 0, 0, NA, 0, 1) -MUX_CFG("Y5_USB2_RCV", C, 21, 1, 0, 0, 0, NA, 0, 1) -MUX_CFG("R8_USB2_VM", C, 18, 1, 0, 0, 0, NA, 0, 1) -MUX_CFG("V6_USB2_TXD", C, 27, 2, 0, 0, 0, NA, 0, 1) -MUX_CFG("W5_USB2_SE0", C, 24, 2, 0, 0, 0, NA, 0, 1) +MUX_CFG("W9_USB2_TXEN", B, 9, 1, NA, 0, 0, NA, 0, 1) +MUX_CFG("AA9_USB2_VP", B, 6, 1, NA, 0, 0, NA, 0, 1) +MUX_CFG("Y5_USB2_RCV", C, 21, 1, NA, 0, 0, NA, 0, 1) +MUX_CFG("R8_USB2_VM", C, 18, 1, NA, 0, 0, NA, 0, 1) +MUX_CFG("V6_USB2_TXD", C, 27, 2, NA, 0, 0, NA, 0, 1) +MUX_CFG("W5_USB2_SE0", C, 24, 2, NA, 0, 0, NA, 0, 1) /* UART1 */ @@ -437,8 +441,8 @@ MUX_CFG("R14_1610_UART1_CTS", 9, 15, 0, 2, 1, 0, 2, 1, 1) MUX_CFG("AA15_1610_UART1_RTS", 9, 12, 1, 2, 0, 0, 2, 0, 1) /* I2C interface */ -MUX_CFG("I2C_SCL", 7, 24, 0, 0, 0, 0, 0, 0, 0) -MUX_CFG("I2C_SDA", 7, 27, 0, 0, 0, 0, 0, 0, 0) +MUX_CFG("I2C_SCL", 7, 24, 0, NA, 0, 0, NA, 0, 0) +MUX_CFG("I2C_SDA", 7, 27, 0, NA, 0, 0, NA, 0, 0) /* Keypad */ MUX_CFG("F18_1610_KBC0", 3, 15, 0, 0, 5, 1, 0, 0, 0) @@ -453,6 +457,8 @@ MUX_CFG("E20_1610_KBR3", 3, 21, 0, 0, 7, 1, 0, 1, 0) MUX_CFG("E19_1610_KBR4", 3, 18, 0, 0, 6, 1, 0, 1, 0) MUX_CFG("N19_1610_KBR5", 6, 12, 1, 1, 2, 1, 1, 1, 0) +/* Power management */ +MUX_CFG("T20_1610_LOW_PWR", 7, 12, 1, 0, 0, 0, NA, 0, 0) }; #endif /* __MUX_C__ */ diff --git a/include/asm-arm/arch-omap/omap1510.h b/include/asm-arm/arch-omap/omap1510.h index d6c12ec49699..b13584662a68 100644 --- a/include/asm-arm/arch-omap/omap1510.h +++ b/include/asm-arm/arch-omap/omap1510.h @@ -36,19 +36,27 @@ /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ -#define OMAP_SRAM_BASE 0xD0000000 -#define OMAP_SRAM_SIZE (SZ_128K + SZ_64K) -#define OMAP_SRAM_START 0x20000000 +#define OMAP1510_SRAM_BASE 0xD0000000 +#define OMAP1510_SRAM_SIZE (SZ_128K + SZ_64K) +#define OMAP1510_SRAM_START 0x20000000 -#define OMAP_MCBSP1_BASE 0xE1011000 -#define OMAP_MCBSP1_SIZE SZ_4K -#define OMAP_MCBSP1_START 0xE1011000 +#define OMAP1510_MCBSP1_BASE 0xE1011000 +#define OMAP1510_MCBSP1_SIZE SZ_4K +#define OMAP1510_MCBSP1_START 0xE1011000 -#define OMAP_MCBSP2_BASE 0xFFFB1000 +#define OMAP1510_MCBSP2_BASE 0xFFFB1000 -#define OMAP_MCBSP3_BASE 0xE1017000 -#define OMAP_MCBSP3_SIZE SZ_4K -#define OMAP_MCBSP3_START 0xE1017000 +#define OMAP1510_MCBSP3_BASE 0xE1017000 +#define OMAP1510_MCBSP3_SIZE SZ_4K +#define OMAP1510_MCBSP3_START 0xE1017000 + +#define OMAP1510_DSP_BASE 0xE0000000 +#define OMAP1510_DSP_SIZE 0x28000 +#define OMAP1510_DSP_START 0xE0000000 + +#define OMAP1510_DSPREG_BASE 0xE1000000 +#define OMAP1510_DSPREG_SIZE SZ_128K +#define OMAP1510_DSPREG_START 0xE1000000 #endif /* __ASM_ARCH_OMAP1510_H */ diff --git a/include/asm-arm/arch-omap/omap1610.h b/include/asm-arm/arch-omap/omap1610.h index 1cd6054c7adc..c2ef7c32c96c 100644 --- a/include/asm-arm/arch-omap/omap1610.h +++ b/include/asm-arm/arch-omap/omap1610.h @@ -36,9 +36,22 @@ /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ -#define OMAP_SRAM_BASE 0xD0000000 -#define OMAP_SRAM_SIZE (SZ_16K) -#define OMAP_SRAM_START 0x20000000 +#define OMAP1610_SRAM_BASE 0xD0000000 +#define OMAP1610_SRAM_SIZE (SZ_16K) +#define OMAP1610_SRAM_START 0x20000000 + +#define OMAP1610_DSP_BASE 0xE0000000 +#define OMAP1610_DSP_SIZE 0x28000 +#define OMAP1610_DSP_START 0xE0000000 + +#define OMAP1610_DSPREG_BASE 0xE1000000 +#define OMAP1610_DSPREG_SIZE SZ_128K +#define OMAP1610_DSPREG_START 0xE1000000 + +#define OMAP_IH2_0_BASE 0xfffe0000 +#define OMAP_IH2_1_BASE 0xfffe0100 +#define OMAP_IH2_2_BASE 0xfffe0200 +#define OMAP_IH2_3_BASE 0xfffe0300 /* * ---------------------------------------------------------------------------- @@ -46,14 +59,14 @@ * ---------------------------------------------------------------------------- */ -#define OMAP_RESET_CONTROL 0xfffe1140 -#define ARM_IDLECT3 (CLKGEN_RESET_BASE + 0x24) -#define CONF_VOLTAGE_CTRL_0 0xfffe1060 -#define CONF_VOLTAGE_VDDSHV6 (1 << 8) -#define CONF_VOLTAGE_VDDSHV7 (1 << 9) -#define CONF_VOLTAGE_VDDSHV8 (1 << 10) -#define CONF_VOLTAGE_VDDSHV9 (1 << 11) -#define SUBLVDS_CONF_VALID (1 << 13) +#define OMAP1610_RESET_CONTROL 0xfffe1140 +#define OMAP1610_ARM_IDLECT3 (CLKGEN_RESET_BASE + 0x24) +#define OMAP1610_CONF_VOLTAGE_CTRL_0 0xfffe1060 +#define OMAP1610_CONF_VOLTAGE_VDDSHV6 (1 << 8) +#define OMAP1610_CONF_VOLTAGE_VDDSHV7 (1 << 9) +#define OMAP1610_CONF_VOLTAGE_VDDSHV8 (1 << 10) +#define OMAP1610_CONF_VOLTAGE_VDDSHV9 (1 << 11) +#define OMAP1610_SUBLVDS_CONF_VALID (1 << 13) /* * --------------------------------------------------------------------------- @@ -61,13 +74,13 @@ * --------------------------------------------------------------------------- */ -#define OMAP_TIPB_SWITCH 0xfffbc800 -#define TIPB_BRIDGE_INT 0xfffeca00 /* Private TIPB_CNTL */ -#define PRIVATE_MPU_TIPB_CNTL 0xfffeca08 -#define TIPB_BRIDGE_EXT 0xfffed300 /* Public (Shared) TIPB_CNTL */ -#define PUBLIC_MPU_TIPB_CNTL 0xfffed308 -#define TIPB_SWITCH_CFG OMAP_TIPB_SWITCH -#define MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_CFG + 0x160) +#define OMAP1610_TIPB_SWITCH 0xfffbc800 +#define OMAP1610_TIPB_BRIDGE_INT 0xfffeca00 /* Private TIPB_CNTL */ +#define OMAP1610_PRIVATE_MPU_TIPB_CNTL 0xfffeca08 +#define OMAP1610_TIPB_BRIDGE_EXT 0xfffed300 /* Public (Shared) TIPB_CNTL */ +#define OMAP1610_PUBLIC_MPU_TIPB_CNTL 0xfffed308 +#define OMAP1610_TIPB_SWITCH_CFG OMAP_TIPB_SWITCH +#define OMAP1610_MMCSD2_SSW_MPU_CONF (TIPB_SWITCH_CFG + 0x160) #endif /* __ASM_ARCH_OMAP1610_H */ diff --git a/include/asm-arm/arch-omap/omap5912.h b/include/asm-arm/arch-omap/omap5912.h new file mode 100644 index 000000000000..aa72dd5c2453 --- /dev/null +++ b/include/asm-arm/arch-omap/omap5912.h @@ -0,0 +1,61 @@ +/* linux/include/asm-arm/arch-omap/omap5912.h + * + * Hardware definitions for TI OMAP5912 processor. + * + * Written by Dirk Behme <dirk.behme@de.bosch.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_ARCH_OMAP5912_H +#define __ASM_ARCH_OMAP5912_H + +/* + * ---------------------------------------------------------------------------- + * Base addresses + * ---------------------------------------------------------------------------- + */ + +/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ + +/* OMAP5912 internal SRAM size is 250kByte */ +#define OMAP5912_SRAM_BASE 0xD0000000 +#define OMAP5912_SRAM_SIZE 0x3E800 +#define OMAP5912_SRAM_START 0x20000000 + +#define OMAP5912_DSP_BASE 0xE0000000 +#define OMAP5912_DSP_SIZE 0x50000 +#define OMAP5912_DSP_START 0xE0000000 + +#define OMAP5912_DSPREG_BASE 0xE1000000 +#define OMAP5912_DSPREG_SIZE SZ_128K +#define OMAP5912_DSPREG_START 0xE1000000 + +/* + * ---------------------------------------------------------------------------- + * System control registers + * ---------------------------------------------------------------------------- + */ + +#define OMAP5912_ARM_IDLECT3 (CLKGEN_RESET_BASE + 0x24) + +#endif /* __ASM_ARCH_OMAP5912_H */ + diff --git a/include/asm-arm/arch-omap/omap730.h b/include/asm-arm/arch-omap/omap730.h index c3d33ce6548e..82aca67e2367 100644 --- a/include/asm-arm/arch-omap/omap730.h +++ b/include/asm-arm/arch-omap/omap730.h @@ -36,15 +36,77 @@ /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ -#define OMAP_SRAM_BASE 0xD0000000 -#define OMAP_SRAM_SIZE (SZ_128K + SZ_64K + SZ_8K) -#define OMAP_SRAM_START 0x20000000 +#define OMAP730_SRAM_BASE 0xD0000000 +#define OMAP730_SRAM_SIZE (SZ_128K + SZ_64K + SZ_8K) +#define OMAP730_SRAM_START 0x20000000 -#define OMAP_MCBSP1_BASE 0xfffb1000 -#define OMAP_MCBSP1_SIZE (SZ_1K * 2) -#define OMAP_MCBSP1_START 0xfffb1000 +#define OMAP730_MCBSP1_BASE 0xfffb1000 +#define OMAP730_MCBSP1_SIZE (SZ_1K * 2) +#define OMAP730_MCBSP1_START 0xfffb1000 -#define OMAP_MCBSP2_BASE 0xfffb1800 +#define OMAP730_MCBSP2_BASE 0xfffb1800 + +#define OMAP730_DSP_BASE 0xE0000000 +#define OMAP730_DSP_SIZE 0x50000 +#define OMAP730_DSP_START 0xE0000000 + +#define OMAP730_DSPREG_BASE 0xE1000000 +#define OMAP730_DSPREG_SIZE SZ_128K +#define OMAP730_DSPREG_START 0xE1000000 + +/* + * ---------------------------------------------------------------------------- + * OMAP730 specific configuration registers + * ---------------------------------------------------------------------------- + */ +#define OMAP730_CONFIG_BASE 0xfffe1000 +#define OMAP730_IO_CONF_0 0xfffe1070 +#define OMAP730_IO_CONF_1 0xfffe1074 +#define OMAP730_IO_CONF_2 0xfffe1078 +#define OMAP730_IO_CONF_3 0xfffe107c +#define OMAP730_IO_CONF_4 0xfffe1080 +#define OMAP730_IO_CONF_5 0xfffe1084 +#define OMAP730_IO_CONF_6 0xfffe1088 +#define OMAP730_IO_CONF_7 0xfffe108c +#define OMAP730_IO_CONF_8 0xfffe1090 +#define OMAP730_IO_CONF_9 0xfffe1094 +#define OMAP730_IO_CONF_10 0xfffe1098 +#define OMAP730_IO_CONF_11 0xfffe109c +#define OMAP730_IO_CONF_12 0xfffe10a0 +#define OMAP730_IO_CONF_13 0xfffe10a4 + +#define OMAP730_MODE_1 0xfffe1010 +#define OMAP730_MODE_2 0xfffe1014 + +/* CSMI specials: in terms of base + offset */ +#define OMAP730_MODE2_OFFSET 0x14 + +/* + * ---------------------------------------------------------------------------- + * OMAP730 traffic controller configuration registers + * ---------------------------------------------------------------------------- + */ +#define OMAP730_FLASH_CFG_0 0xfffecc10 +#define OMAP730_FLASH_ACFG_0 0xfffecc50 +#define OMAP730_FLASH_CFG_1 0xfffecc14 +#define OMAP730_FLASH_ACFG_1 0xfffecc54 + +/* + * ---------------------------------------------------------------------------- + * OMAP730 DSP control registers + * ---------------------------------------------------------------------------- + */ +#define OMAP730_ICR_BASE 0xfffbb800 +#define OMAP730_DSP_M_CTL 0xfffbb804 +#define OMAP730_DSP_MMU_BASE 0xfffed200 + +/* + * ---------------------------------------------------------------------------- + * OMAP730 PCC_UPLD configuration registers + * ---------------------------------------------------------------------------- + */ +#define OMAP730_PCC_UPLD_CTRL_REG_BASE (0xfffe0900) +#define OMAP730_PCC_UPLD_CTRL_REG (OMAP730_PCC_UPLD_CTRL_REG_BASE + 0x00) #endif /* __ASM_ARCH_OMAP730_H */ diff --git a/include/asm-arm/arch-omap/pm.h b/include/asm-arm/arch-omap/pm.h index 26f2079f0bee..2976b46c3a3d 100644 --- a/include/asm-arm/arch-omap/pm.h +++ b/include/asm-arm/arch-omap/pm.h @@ -35,8 +35,8 @@ * More ones like CP and general purpose register values are preserved * with the stack pointer in sleep.S. */ -#ifndef __ASM_ARCH_OMAP1510_PM_H -#define __ASM_ARCH_OMAP1510_PM_H +#ifndef __ASM_ARCH_OMAP_PM_H +#define __ASM_ARCH_OMAP_PM_H #define ARM_REG_BASE (0xfffece00) #define ARM_ASM_IDLECT1 (ARM_REG_BASE + 0x4) @@ -50,29 +50,53 @@ #define TCMIF_BASE 0xfffecc00 #define EMIFS_ASM_CONFIG_REG (TCMIF_BASE + 0x0c) #define EMIFF_ASM_SDRAM_CONFIG (TCMIF_BASE + 0x20) -#define IRQ_MIR1 (volatile unsigned int *)(OMAP_IH1_BASE + IRQ_MIR) -#define IRQ_MIR2 (volatile unsigned int *)(OMAP_IH2_BASE + IRQ_MIR) +#define IRQ_MIR1 (OMAP_IH1_BASE + IRQ_MIR) + +#ifdef CONFIG_ARCH_OMAP1510 +#define IRQ_MIR2 (OMAP_IH2_BASE + IRQ_MIR) +#else /* CONFIG_ARCH_OMAP1610 */ +#define IRQ_MIR2_0 (OMAP_IH2_0_BASE + IRQ_MIR) +#define IRQ_MIR2_1 (OMAP_IH2_1_BASE + IRQ_MIR) +#define IRQ_MIR2_2 (OMAP_IH2_2_BASE + IRQ_MIR) +#define IRQ_MIR2_3 (OMAP_IH2_3_BASE + IRQ_MIR) +#endif -#define IDLE_WAIT_CYCLES 0x000000ff +#define IDLE_WAIT_CYCLES 0x00000fff #define PERIPHERAL_ENABLE 0x2 + +#ifdef CONFIG_ARCH_OMAP1510 +#define DEEP_SLEEP_REQUEST 0x0ec7 #define BIG_SLEEP_REQUEST 0x0cc5 #define IDLE_LOOP_REQUEST 0x0c00 +#define IDLE_CLOCK_DOMAINS 0x2 +#else /* CONFIG_ARCH_OMAP1610 */ +#define DEEP_SLEEP_REQUEST 0x17c7 +#define BIG_SLEEP_REQUEST TBD +#define IDLE_LOOP_REQUEST 0x0400 +#define IDLE_CLOCK_DOMAINS 0x09c7 +#endif + #define SELF_REFRESH_MODE 0x0c000001 #define IDLE_EMIFS_REQUEST 0xc -#define IDLE_CLOCK_DOMAINS 0x2 #define MODEM_32K_EN 0x1 #ifndef __ASSEMBLER__ -extern void omap1510_pm_idle(void); +extern void omap_pm_idle(void); extern void omap_pm_suspend(void); -extern int omap1510_cpu_suspend(void); -extern int omap1510_idle_loop_suspend(void); +extern int omap_cpu_suspend(unsigned short, unsigned short); +extern int omap_idle_loop_suspend(void); extern struct async_struct *omap_pm_sercons; extern unsigned int serial_in(struct async_struct *, int); extern unsigned int serial_out(struct async_struct *, int, int); -#define OMAP1510_SRAM_IDLE_SUSPEND 0xd002F000 -#define OMAP1510_SRAM_API_SUSPEND 0xd002F200 +#ifdef CONFIG_ARCH_OMAP1510 +#define OMAP_SRAM_IDLE_SUSPEND 0xd002F000 +#define OMAP_SRAM_API_SUSPEND 0xd002F200 +#else /* CONFIG_ARCH_OMAP1610 */ +#define OMAP_SRAM_IDLE_SUSPEND 0xd0000400 +#define OMAP_SRAM_API_SUSPEND 0xd0000600 +#endif + #define CPU_SUSPEND_SIZE 200 #define ARM_REG_BASE (0xfffece00) #define ARM_ASM_IDLECT1 (ARM_REG_BASE + 0x4) @@ -82,10 +106,17 @@ extern unsigned int serial_out(struct async_struct *, int, int); #define ARM_ASM_SYSST (ARM_REG_BASE + 0x18) #define TCMIF_BASE 0xfffecc00 -#define PM_EMIFS_CONFIG_REG (volatile unsigned int *)(TCMIF_BASE + 0x0c) -#define PM_EMIFF_SDRAM_CONFIG (volatile unsigned int *)(TCMIF_BASE + 0x20) - -#define ULPD_LOW_POWER_REQ 0x3 +#define PM_EMIFS_CONFIG_REG (TCMIF_BASE + 0x0c) +#define PM_EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20) +#define FUNC_MUX_CTRL_LOW_PWR (0xfffe1020) + +#ifdef CONFIG_ARCH_OMAP1510 +#define ULPD_LOW_POWER_REQ 0x0001 +#else /* CONFIG_ARCH_OMAP1610 */ +#define ULPD_LOW_POWER_REQ 0x3 +#endif +#define ULPD_LOW_PWR 0x1000 +#define ULPD_LOW_POWER_EN 0x0001 #define DSP_IDLE_DELAY 10 #define DSP_IDLE 0x0040 @@ -98,16 +129,16 @@ extern unsigned int serial_out(struct async_struct *, int, int); #define EMIFF_CONFIG_REG EMIFF_SDRAM_CONFIG -#define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = (unsigned short)*x -#define ARM_RESTORE(x) *x = (unsigned short)arm_sleep_save[ARM_SLEEP_SAVE_##x] +#define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readw(x) +#define ARM_RESTORE(x) omap_writew((unsigned short)arm_sleep_save[ARM_SLEEP_SAVE_##x], x) #define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] -#define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = (unsigned short)*x -#define ULPD_RESTORE(x) *x = (unsigned short)ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] +#define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x) +#define ULPD_RESTORE(x) omap_writew((unsigned short)ulpd_sleep_save[ULPD_SLEEP_SAVE_##x], x) #define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] -#define MPUI_SAVE(x) mpui_sleep_save[MPUI_SLEEP_SAVE_##x] = (unsigned int)*x -#define MPUI_RESTORE(x) *x = (unsigned int)mpui_sleep_save[MPUI_SLEEP_SAVE_##x] +#define MPUI_SAVE(x) mpui_sleep_save[MPUI_SLEEP_SAVE_##x] = omap_readl(x) +#define MPUI_RESTORE(x) omap_writel((unsigned int)mpui_sleep_save[MPUI_SLEEP_SAVE_##x], x) #define MPUI_SHOW(x) (unsigned int)mpui_sleep_save[MPUI_SLEEP_SAVE_##x] enum arm_save_state { @@ -124,7 +155,7 @@ enum arm_save_state { }; enum ulpd_save_state { - ULDP_SLEEP_SAVE_START = 0, + ULPD_SLEEP_SAVE_START = 0, ULPD_SLEEP_SAVE_ULPD_IT_STATUS_REG, ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL_REG, ULPD_SLEEP_SAVE_ULPD_SOFT_REQ_REG, ULPD_SLEEP_SAVE_ULPD_STATUS_REQ_REG, ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL_REG, ULPD_SLEEP_SAVE_ULPD_POWER_CTRL_REG, @@ -140,7 +171,15 @@ enum mpui_save_state { MPUI_SLEEP_SAVE_MPUI_DSP_STATUS_REG, MPUI_SLEEP_SAVE_PM_EMIFF_SDRAM_CONFIG, MPUI_SLEEP_SAVE_PM_EMIFS_CONFIG_REG, - MPUI_SLEEP_SAVE_IRQ_MIR1, MPUI_SLEEP_SAVE_IRQ_MIR2, + MPUI_SLEEP_SAVE_IRQ_MIR1, +#ifdef CONFIG_ARCH_OMAP1510 + MPUI_SLEEP_SAVE_IRQ_MIR2, +#else /* CONFIG_ARCH_OMAP1610 */ + MPUI_SLEEP_SAVE_IRQ_MIR2_0, + MPUI_SLEEP_SAVE_IRQ_MIR2_1, + MPUI_SLEEP_SAVE_IRQ_MIR2_2, + MPUI_SLEEP_SAVE_IRQ_MIR2_3, +#endif MPUI_SLEEP_SAVE_SIZE }; diff --git a/include/asm-arm/arch-omap/serial.h b/include/asm-arm/arch-omap/serial.h index e1436506c4f0..d37271884065 100644 --- a/include/asm-arm/arch-omap/serial.h +++ b/include/asm-arm/arch-omap/serial.h @@ -9,136 +9,17 @@ #ifndef __ASM_ARCH_SERIAL_H #define __ASM_ARCH_SERIAL_H - -#define OMAP1510_UART1_BASE (unsigned char *)0xfffb0000 -#define OMAP1510_UART2_BASE (unsigned char *)0xfffb0800 -#define OMAP1510_UART3_BASE (unsigned char *)0xfffb9800 - -#define OMAP730_UART1_BASE (unsigned char *)0xfffb0000 -#define OMAP730_UART2_BASE (unsigned char *)0xfffb0800 - -#if defined(CONFIG_ARCH_OMAP1510) || defined(CONFIG_ARCH_OMAP1610) -#define OMAP_SERIAL_REG_SHIFT 2 -#else -#define OMAP_SERIAL_REG_SHIFT 0 -#endif - +#define OMAP_UART1_BASE (unsigned char *)0xfffb0000 +#define OMAP_UART2_BASE (unsigned char *)0xfffb0800 +#define OMAP_UART3_BASE (unsigned char *)0xfffb9800 #ifndef __ASSEMBLY__ #include <asm/arch/hardware.h> #include <asm/irq.h> - -/* UART3 Registers Maping through MPU bus */ -#define OMAP_MPU_UART3_BASE 0xFFFB9800 /* UART3 through MPU bus */ -#define UART3_RHR (OMAP_MPU_UART3_BASE + 0) -#define UART3_THR (OMAP_MPU_UART3_BASE + 0) -#define UART3_DLL (OMAP_MPU_UART3_BASE + 0) -#define UART3_IER (OMAP_MPU_UART3_BASE + 4) -#define UART3_DLH (OMAP_MPU_UART3_BASE + 4) -#define UART3_IIR (OMAP_MPU_UART3_BASE + 8) -#define UART3_FCR (OMAP_MPU_UART3_BASE + 8) -#define UART3_EFR (OMAP_MPU_UART3_BASE + 8) -#define UART3_LCR (OMAP_MPU_UART3_BASE + 0x0C) -#define UART3_MCR (OMAP_MPU_UART3_BASE + 0x10) -#define UART3_XON1_ADDR1 (OMAP_MPU_UART3_BASE + 0x10) -#define UART3_XON2_ADDR2 (OMAP_MPU_UART3_BASE + 0x14) -#define UART3_LSR (OMAP_MPU_UART3_BASE + 0x14) -#define UART3_TCR (OMAP_MPU_UART3_BASE + 0x18) -#define UART3_MSR (OMAP_MPU_UART3_BASE + 0x18) -#define UART3_XOFF1 (OMAP_MPU_UART3_BASE + 0x18) -#define UART3_XOFF2 (OMAP_MPU_UART3_BASE + 0x1C) -#define UART3_SPR (OMAP_MPU_UART3_BASE + 0x1C) -#define UART3_TLR (OMAP_MPU_UART3_BASE + 0x1C) -#define UART3_MDR1 (OMAP_MPU_UART3_BASE + 0x20) -#define UART3_MDR2 (OMAP_MPU_UART3_BASE + 0x24) -#define UART3_SFLSR (OMAP_MPU_UART3_BASE + 0x28) -#define UART3_TXFLL (OMAP_MPU_UART3_BASE + 0x28) -#define UART3_RESUME (OMAP_MPU_UART3_BASE + 0x2C) -#define UART3_TXFLH (OMAP_MPU_UART3_BASE + 0x2C) -#define UART3_SFREGL (OMAP_MPU_UART3_BASE + 0x30) -#define UART3_RXFLL (OMAP_MPU_UART3_BASE + 0x30) -#define UART3_SFREGH (OMAP_MPU_UART3_BASE + 0x34) -#define UART3_RXFLH (OMAP_MPU_UART3_BASE + 0x34) -#define UART3_BLR (OMAP_MPU_UART3_BASE + 0x38) -#define UART3_ACREG (OMAP_MPU_UART3_BASE + 0x3C) -#define UART3_DIV16 (OMAP_MPU_UART3_BASE + 0x3C) -#define UART3_SCR (OMAP_MPU_UART3_BASE + 0x40) -#define UART3_SSR (OMAP_MPU_UART3_BASE + 0x44) -#define UART3_EBLR (OMAP_MPU_UART3_BASE + 0x48) -#define UART3_OSC_12M_SEL (OMAP_MPU_UART3_BASE + 0x4C) -#define UART3_MVR (OMAP_MPU_UART3_BASE + 0x50) - -#ifdef CONFIG_ARCH_OMAP1510 -#define BASE_BAUD (12000000/16) -#endif - -#ifdef CONFIG_ARCH_OMAP1610 -#define BASE_BAUD (48000000/16) -#endif - -#ifdef CONFIG_ARCH_OMAP730 -#define BASE_BAUD (48000000/16) - -#define RS_TABLE_SIZE 2 - -#define STD_COM_FLAGS (ASYNC_SKIP_TEST) - -#define STD_SERIAL_PORT_DEFNS \ - { \ - .uart = PORT_OMAP, \ - .baud_base = BASE_BAUD, \ - .iomem_base = OMAP730_UART1_BASE, \ - .iomem_reg_shift = 0, \ - .io_type = SERIAL_IO_MEM, \ - .irq = INT_UART1, \ - .flags = STD_COM_FLAGS, \ - }, { \ - .uart = PORT_OMAP, \ - .baud_base = BASE_BAUD, \ - .iomem_base = OMAP730_UART2_BASE, \ - .iomem_reg_shift = 0, \ - .io_type = SERIAL_IO_MEM, \ - .irq = INT_UART2, \ - .flags = STD_COM_FLAGS, \ - } - -#else - -#define RS_TABLE_SIZE 3 - -#define STD_COM_FLAGS (ASYNC_SKIP_TEST) - -#define STD_SERIAL_PORT_DEFNS \ - { \ - .uart = PORT_OMAP, \ - .baud_base = BASE_BAUD, \ - .iomem_base = OMAP1510_UART1_BASE, \ - .iomem_reg_shift = 2, \ - .io_type = SERIAL_IO_MEM, \ - .irq = INT_UART1, \ - .flags = STD_COM_FLAGS, \ - }, { \ - .uart = PORT_OMAP, \ - .baud_base = BASE_BAUD, \ - .iomem_base = OMAP1510_UART2_BASE, \ - .iomem_reg_shift = 2, \ - .io_type = SERIAL_IO_MEM, \ - .irq = INT_UART2, \ - .flags = STD_COM_FLAGS, \ - }, { \ - .uart = PORT_OMAP, \ - .baud_base = BASE_BAUD, \ - .iomem_base = OMAP1510_UART3_BASE, \ - .iomem_reg_shift = 2, \ - .io_type = SERIAL_IO_MEM, \ - .irq = INT_UART3, \ - .flags = STD_COM_FLAGS, \ - } -#endif /* CONFIG_ARCH_OMAP730 */ - -#define EXTRA_SERIAL_PORT_DEFNS +#define OMAP1510_BASE_BAUD (12000000/16) +#define OMAP1610_BASE_BAUD (48000000/16) /* OMAP FCR trigger redefinitions */ #define UART_FCR_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 8 */ @@ -163,5 +44,9 @@ #define UART_FCR_T_TRIGGER_32 0x20 /* Mask for transmit trigger set at 32 */ #define UART_FCR_T_TRIGGER_56 0x30 /* Mask for transmit trigger set at 56 */ +#define STD_SERIAL_PORT_DEFNS +#define EXTRA_SERIAL_PORT_DEFNS +#define BASE_BAUD 0 + #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARCH_SERIAL_H */ diff --git a/include/asm-arm/arch-omap/system.h b/include/asm-arm/arch-omap/system.h index 9d1f4eacd647..17a2c4825f07 100644 --- a/include/asm-arm/arch-omap/system.h +++ b/include/asm-arm/arch-omap/system.h @@ -14,7 +14,7 @@ static inline void arch_idle(void) static inline void arch_reset(char mode) { - *(volatile u16 *)(ARM_RSTCT1) = 1; + omap_writew(1, ARM_RSTCT1); } #endif diff --git a/include/asm-arm/arch-omap/time.h b/include/asm-arm/arch-omap/time.h index 26743eb927d5..9e3cc951ebb4 100644 --- a/include/asm-arm/arch-omap/time.h +++ b/include/asm-arm/arch-omap/time.h @@ -51,16 +51,16 @@ typedef struct { } mputimer_regs_t; #define mputimer_base(n) \ - ((volatile mputimer_regs_t*)(OMAP_MPUTIMER_BASE + \ + ((volatile mputimer_regs_t*)IO_ADDRESS(OMAP_MPUTIMER_BASE + \ (n)*OMAP_MPUTIMER_OFF)) static inline unsigned long timer32k_read(int reg) { unsigned long val; - val = (inw(IO_ADDRESS((reg) + OMAP_32kHz_TIMER_BASE))); + val = omap_readw(reg + OMAP_32kHz_TIMER_BASE); return val; } static inline void timer32k_write(int reg,int val) { - outw( (val), (IO_ADDRESS( (reg) + OMAP_32kHz_TIMER_BASE))); + omap_writew(val, reg + OMAP_32kHz_TIMER_BASE); } /* diff --git a/include/asm-arm/arch-omap/uncompress.h b/include/asm-arm/arch-omap/uncompress.h index b37eb47a2cf5..7585602594df 100644 --- a/include/asm-arm/arch-omap/uncompress.h +++ b/include/asm-arm/arch-omap/uncompress.h @@ -24,6 +24,7 @@ #include <asm/hardware.h> #include <asm/arch/serial.h> +#define UART_OMAP_MDR1 0x08 /* mode definition register */ #define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0) @@ -35,9 +36,12 @@ puts(const char *s) /* Determine which serial port to use */ do { - if (machine_is_innovator()) { + if (machine_is_omap_innovator() || machine_is_omap_osk()) { shift = 2; - uart = (volatile u8 *)(OMAP1510_UART1_BASE); + uart = (volatile u8 *)(OMAP_UART1_BASE); + } else if (machine_is_omap_perseus2()) { + shift = 0; + uart = (volatile u8 *)(OMAP_UART1_BASE); } else { /* Assume nothing for unknown machines. * Add an entry for your machine to select diff --git a/include/asm-arm/arch-omap/vmalloc.h b/include/asm-arm/arch-omap/vmalloc.h index 198e246c661b..c6a83581a2fc 100644 --- a/include/asm-arm/arch-omap/vmalloc.h +++ b/include/asm-arm/arch-omap/vmalloc.h @@ -30,3 +30,4 @@ #define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) #define VMALLOC_VMADDR(x) ((unsigned long)(x)) #define VMALLOC_END (PAGE_OFFSET + 0x10000000) + diff --git a/include/asm-arm/numnodes.h b/include/asm-arm/numnodes.h index 609f73b00b6a..c523acc15809 100644 --- a/include/asm-arm/numnodes.h +++ b/include/asm-arm/numnodes.h @@ -10,7 +10,10 @@ #ifndef __ASM_ARM_NUMNODES_H #define __ASM_ARM_NUMNODES_H -/* Max 4 Nodes */ -#define NODES_SHIFT 2 +#ifdef CONFIG_ARCH_LH7A40X +# define NODES_SHIFT 4 /* Max 16 nodes for the Sharp CPUs */ +#else +# define NODES_SHIFT 2 /* Normally, Max 4 Nodes */ +#endif #endif diff --git a/include/asm-arm/setup.h b/include/asm-arm/setup.h index 4680c39be96f..8dd08bb844d2 100644 --- a/include/asm-arm/setup.h +++ b/include/asm-arm/setup.h @@ -188,7 +188,11 @@ static struct tagtable __tagtable_##fn __tag = { tag, fn } /* * Memory map description */ -#define NR_BANKS 8 +#ifdef CONFIG_ARCH_LH7A40X +# define NR_BANKS 16 +#else +# define NR_BANKS 8 +#endif struct meminfo { int nr_banks; |