diff options
| author | Dave Jones <davej@redhat.com> | 2003-08-29 04:12:06 +0100 |
|---|---|---|
| committer | Dave Jones <davej@hardwired.(none)> | 2003-08-29 04:12:06 +0100 |
| commit | b9bf6a33adefa9d32cbe584375c0991761f45281 (patch) | |
| tree | cbc0f25a2ec94d0ed1d4446648785a5e87300154 | |
| parent | 94e7b66d3b2a215a72c9dc4b3818ac6ac6ea6a59 (diff) | |
[AGPGART] Make AMD64 GART driver marchitecture compliant.
X86_64 -> AMD64
| -rw-r--r-- | drivers/char/agp/agp.h | 11 | ||||
| -rw-r--r-- | drivers/char/agp/amd-k8-agp.c | 20 |
2 files changed, 16 insertions, 15 deletions
diff --git a/drivers/char/agp/agp.h b/drivers/char/agp/agp.h index 5a501997632e..2a4b9e0dc363 100644 --- a/drivers/char/agp/agp.h +++ b/drivers/char/agp/agp.h @@ -297,11 +297,12 @@ struct agp_bridge_data { #define AMD_TLBFLUSH 0x0c /* In mmio region (32-bit register) */ #define AMD_CACHEENTRY 0x10 /* In mmio region (32-bit register) */ -#define AMD_X86_64_GARTAPERTURECTL 0x90 -#define AMD_X86_64_GARTAPERTUREBASE 0x94 -#define AMD_X86_64_GARTTABLEBASE 0x98 -#define AMD_X86_64_GARTCACHECTL 0x9c -#define AMD_X86_64_GARTEN 1<<0 +/* AMD64 registers */ +#define AMD64_GARTAPERTURECTL 0x90 +#define AMD64_GARTAPERTUREBASE 0x94 +#define AMD64_GARTTABLEBASE 0x98 +#define AMD64_GARTCACHECTL 0x9c +#define AMD64_GARTEN 1<<0 /* ALi registers */ #define ALI_AGPCTRL 0xb8 diff --git a/drivers/char/agp/amd-k8-agp.c b/drivers/char/agp/amd-k8-agp.c index 3b5b6c2f8346..d147b09056bc 100644 --- a/drivers/char/agp/amd-k8-agp.c +++ b/drivers/char/agp/amd-k8-agp.c @@ -46,9 +46,9 @@ static void flush_x86_64_tlb(struct pci_dev *dev) { u32 tmp; - pci_read_config_dword (dev, AMD_X86_64_GARTCACHECTL, &tmp); + pci_read_config_dword (dev, AMD64_GARTCACHECTL, &tmp); tmp |= INVGART; - pci_write_config_dword (dev, AMD_X86_64_GARTCACHECTL, tmp); + pci_write_config_dword (dev, AMD64_GARTCACHECTL, tmp); } static void amd_x86_64_tlbflush(struct agp_memory *temp) @@ -135,7 +135,7 @@ static int amd_x86_64_fetch_size(void) if (dev==NULL) return 0; - pci_read_config_dword(dev, AMD_X86_64_GARTAPERTURECTL, &temp); + pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp); temp = (temp & 0xe); values = A_SIZE_32(x86_64_aperture_sizes); @@ -162,7 +162,7 @@ static u64 amd_x86_64_configure (struct pci_dev *hammer, u64 gatt_table) u64 addr, aper_base; /* Address to map to */ - pci_read_config_dword (hammer, AMD_X86_64_GARTAPERTUREBASE, &tmp); + pci_read_config_dword (hammer, AMD64_GARTAPERTUREBASE, &tmp); aperturebase = tmp << 25; aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK); @@ -171,13 +171,13 @@ static u64 amd_x86_64_configure (struct pci_dev *hammer, u64 gatt_table) addr >>= 12; tmp = (u32) addr<<4; tmp &= ~0xf; - pci_write_config_dword (hammer, AMD_X86_64_GARTTABLEBASE, tmp); + pci_write_config_dword (hammer, AMD64_GARTTABLEBASE, tmp); /* Enable GART translation for this hammer. */ - pci_read_config_dword(hammer, AMD_X86_64_GARTAPERTURECTL, &tmp); + pci_read_config_dword(hammer, AMD64_GARTAPERTURECTL, &tmp); tmp |= GARTEN; tmp &= ~(DISGARTCPU | DISGARTIO); - pci_write_config_dword(hammer, AMD_X86_64_GARTAPERTURECTL, tmp); + pci_write_config_dword(hammer, AMD64_GARTAPERTURECTL, tmp); /* keep CPU's coherent. */ flush_x86_64_tlb (hammer); @@ -216,9 +216,9 @@ static void amd_8151_cleanup(void) for_each_nb() { /* disable gart translation */ - pci_read_config_dword (hammers[gart_iterator], AMD_X86_64_GARTAPERTURECTL, &tmp); - tmp &= ~(AMD_X86_64_GARTEN); - pci_write_config_dword (hammers[gart_iterator], AMD_X86_64_GARTAPERTURECTL, tmp); + pci_read_config_dword (hammers[gart_iterator], AMD64_GARTAPERTURECTL, &tmp); + tmp &= ~AMD64_GARTEN; + pci_write_config_dword (hammers[gart_iterator], AMD64_GARTAPERTURECTL, tmp); } } |