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authorPaul Mackerras <paulus@samba.org>2003-05-25 15:44:51 +1000
committerPaul Mackerras <paulus@samba.org>2003-05-25 15:44:51 +1000
commitd8e48cd0dcd3ec778b241fccd04f89dc39740713 (patch)
treed3c4cac74053086a9f4c489e834b032f4aa277f3
parentaf75709ac2e8fc62ee00be0078bff1f72deb16e7 (diff)
Fix preempt on PPC32 - have to set PREEMPT_ACTIVE when preempting kernel stuff.
-rw-r--r--arch/ppc/kernel/entry.S32
-rw-r--r--arch/ppc/kernel/l2cr.S8
2 files changed, 24 insertions, 16 deletions
diff --git a/arch/ppc/kernel/entry.S b/arch/ppc/kernel/entry.S
index 04d274804278..463ed868c626 100644
--- a/arch/ppc/kernel/entry.S
+++ b/arch/ppc/kernel/entry.S
@@ -531,12 +531,27 @@ restore_user:
resume_kernel:
/* check current_thread_info->preempt_count */
rlwinm r9,r1,0,0,18
- lwz r3,TI_PREEMPT(r9)
- cmpwi 0,r3,0 /* if non-zero, just restore regs and return */
+ lwz r0,TI_PREEMPT(r9)
+ cmpwi 0,r0,0 /* if non-zero, just restore regs and return */
bne restore
- lwz r9,TI_FLAGS(r9)
- andi. r0,r9,_TIF_NEED_RESCHED
- bne do_resched
+ lwz r0,TI_FLAGS(r9)
+ andi. r0,r0,_TIF_NEED_RESCHED
+ beq+ restore
+ andi. r0,r3,MSR_EE /* interrupts off? */
+ beq restore /* don't schedule if so */
+1: lis r0,PREEMPT_ACTIVE@h
+ stw r0,TI_PREEMPT(r9)
+ ori r10,r10,MSR_EE
+ SYNC
+ MTMSRD(r10) /* hard-enable interrupts */
+ bl schedule
+ LOAD_MSR_KERNEL(r10,MSR_KERNEL)
+ SYNC
+ MTMSRD(r10) /* disable interrupts */
+ rlwinm r9,r1,0,0,18
+ lwz r0,TI_FLAGS(r9)
+ andi. r0,r0,_TIF_NEED_RESCHED
+ bne- 1b
#else
resume_kernel:
#endif /* CONFIG_PREEMPT */
@@ -740,13 +755,6 @@ recheck:
lwz r9,TI_FLAGS(r9)
andi. r0,r9,_TIF_NEED_RESCHED
bne- do_resched
-
-#ifdef CONFIG_PREEMPT
- lwz r0,_MSR(r1)
- andi. r0,r0,MSR_PR
- beq restore
-#endif
-
andi. r0,r9,_TIF_SIGPENDING
beq restore_user
do_user_signal: /* r10 contains MSR_KERNEL here */
diff --git a/arch/ppc/kernel/l2cr.S b/arch/ppc/kernel/l2cr.S
index c1fbb0c5cb0b..f669eab7662f 100644
--- a/arch/ppc/kernel/l2cr.S
+++ b/arch/ppc/kernel/l2cr.S
@@ -272,10 +272,6 @@ BEGIN_FTR_SECTION
blr
END_FTR_SECTION_IFCLR(CPU_FTR_L3CR)
- /* Stop DST streams */
- DSSALL
- sync
-
/* Turn off interrupts and data relocation. */
mfmsr r7 /* Save MSR in r7 */
rlwinm r4,r7,0,17,15
@@ -284,6 +280,10 @@ END_FTR_SECTION_IFCLR(CPU_FTR_L3CR)
mtmsr r4
isync
+ /* Stop DST streams */
+ DSSALL
+ sync
+
/* Get the current enable bit of the L3CR into r4 */
mfspr r4,SPRN_L3CR