diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-04-01 19:37:49 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-04-10 20:15:04 +0300 |
| commit | efaa1177c31be89483dfd3919348b3535f602b5e (patch) | |
| tree | 472604ec7ab8af8cdbf11898797d6d36c0db01ad | |
| parent | d35b913f0e1cb003b658827f5a900d648b092c5b (diff) | |
drm/i915: Apply the combo PLL frac w/a on DG1
DG1 apparently needs the combo PLL fractional divider w/a
with 38.4 MHz refclk as well. This isn't listed in bspec, but
looking at the hsd it looks like it was possibly just missed
due to no one having a DG1 around at the time.
This gives us slightly more accurate clocks on DG1.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250401163752.6412-2-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index ec7feef1ef59..76ab55ee4b80 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -2604,6 +2604,7 @@ ehl_combo_pll_div_frac_wa_needed(struct intel_display *display) { return ((display->platform.elkhartlake && IS_DISPLAY_STEP(display, STEP_B0, STEP_FOREVER)) || + display->platform.dg1 || display->platform.tigerlake || display->platform.alderlake_s || display->platform.alderlake_p) && |