diff options
| author | Timur Tabi <ttabi@nvidia.com> | 2026-01-22 16:28:40 -0600 |
|---|---|---|
| committer | Alexandre Courbot <acourbot@nvidia.com> | 2026-01-24 08:45:13 +0900 |
| commit | f6507640b0cddfd90d398e3996321b1a735f98be (patch) | |
| tree | d8764cbc0aca1a327cdbcd653d0c406f6f745f2d | |
| parent | 121ea04cd9f22ae8fb405d4929f6a7faefefe553 (diff) | |
gpu: nova-core: add NV_PFALCON_FALCON_DMATRFCMD::with_falcon_mem()
The with_falcon_mem() method initializes the 'imem' and 'sec' fields of
the NV_PFALCON_FALCON_DMATRFCMD register based on the value of
the FalconMem type.
Signed-off-by: Timur Tabi <ttabi@nvidia.com>
Reviewed-by: John Hubbard <jhubbard@nvidia.com>
Reviewed-by: Gary Guo <gary@garyguo.net>
Acked-by: Danilo Krummrich <dakr@kernel.org>
Link: https://patch.msgid.link/20260122222848.2555890-6-ttabi@nvidia.com
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
| -rw-r--r-- | drivers/gpu/nova-core/falcon.rs | 14 | ||||
| -rw-r--r-- | drivers/gpu/nova-core/regs.rs | 9 |
2 files changed, 12 insertions, 11 deletions
diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs index 1d902ec62a6e..34b36f7b3bfd 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -458,7 +458,6 @@ impl<E: FalconEngine + 'static> Falcon<E> { fw: &F, target_mem: FalconMem, load_offsets: FalconLoadTarget, - sec: bool, ) -> Result { const DMA_LEN: u32 = 256; @@ -526,8 +525,7 @@ impl<E: FalconEngine + 'static> Falcon<E> { let cmd = regs::NV_PFALCON_FALCON_DMATRFCMD::default() .set_size(DmaTrfCmdSize::Size256B) - .set_imem(target_mem != FalconMem::Dmem) - .set_sec(if sec { 1 } else { 0 }); + .with_falcon_mem(target_mem); for pos in (0..num_transfers).map(|i| i * DMA_LEN) { // Perform a transfer of size `DMA_LEN`. @@ -568,14 +566,8 @@ impl<E: FalconEngine + 'static> Falcon<E> { .set_mem_type(FalconFbifMemType::Physical) }); - self.dma_wr( - bar, - fw, - FalconMem::ImemSecure, - fw.imem_sec_load_params(), - true, - )?; - self.dma_wr(bar, fw, FalconMem::Dmem, fw.dmem_load_params(), true)?; + self.dma_wr(bar, fw, FalconMem::ImemSecure, fw.imem_sec_load_params())?; + self.dma_wr(bar, fw, FalconMem::Dmem, fw.dmem_load_params())?; self.hal.program_brom(self, bar, &fw.brom_params())?; diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 82cc6c0790e5..b8ddfe2e5ae7 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -16,6 +16,7 @@ use crate::{ FalconCoreRevSubversion, FalconFbifMemType, FalconFbifTarget, + FalconMem, FalconModSelAlgo, FalconSecurityModel, PFalcon2Base, @@ -325,6 +326,14 @@ register!(NV_PFALCON_FALCON_DMATRFCMD @ PFalconBase[0x00000118] { 16:16 set_dmtag as u8; }); +impl NV_PFALCON_FALCON_DMATRFCMD { + /// Programs the `imem` and `sec` fields for the given FalconMem + pub(crate) fn with_falcon_mem(self, mem: FalconMem) -> Self { + self.set_imem(mem != FalconMem::Dmem) + .set_sec(if mem == FalconMem::ImemSecure { 1 } else { 0 }) + } +} + register!(NV_PFALCON_FALCON_DMATRFFBOFFS @ PFalconBase[0x0000011c] { 31:0 offs as u32; }); |
