[PATCH] add L1_CACHE_SHIFT_MAX

zone->lock and zone->lru_lock are two of the hottest locks in the
kernel.  Their usage patterns are quite independent.  And they have
just been put into the same structure.  It is essential that they not
fall into the same cacheline.

That could be fixed by padding with L1_CACHE_BYTES.  But the problem
with this is that a kernel which was configured for (say) a PIII will
perform poorly on SMP PIV.  This will cause problems for kernel
vendors.  For example, RH currently ship PII and Athlon binaries.  To
get best SMP performance they will end up needing to ship a lot of
differently configured kernels.

To solve this we need to know, at compile time, the maximum L1 size
which this kernel will ever run on.

This patch adds L1_CACHE_SHIFT_MAX to every architecture's cache.h.

Of course it'll break when newer chips come out with increased
cacheline sizes.   Better suggestions are welcome.

18 files changed, 32 insertions, 0 deletions

diff --git a/include/asm-alpha/cache.h b/include/asm-alpha/cache.h
index e6d4d1695e25..f74d7ece132e 100644
--- a/include/asm-alpha/cache.h
+++ b/include/asm-alpha/cache.h
@@ -20,5 +20,6 @@
 
 #define L1_CACHE_ALIGN(x)  (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
 #define SMP_CACHE_BYTES    L1_CACHE_BYTES
+#define L1_CACHE_SHIFT_MAX 6	/* largest L1 which this arch supports */
 
 #endif
diff --git a/include/asm-arm/cache.h b/include/asm-arm/cache.h
index a56ffb7c214e..ce375d2d0f2f 100644
--- a/include/asm-arm/cache.h
+++ b/include/asm-arm/cache.h
@@ -16,4 +16,6 @@
 		 __section__(".data.cacheline_aligned")))
 #endif
 
+#define L1_CACHE_SHIFT_MAX 5	/* largest L1 which this arch supports */
+
 #endif
diff --git a/include/asm-cris/cache.h b/include/asm-cris/cache.h
index 222f5d5316b0..1899bd77461d 100644
--- a/include/asm-cris/cache.h
+++ b/include/asm-cris/cache.h
@@ -7,4 +7,6 @@
 
 #define L1_CACHE_BYTES 32
 
+#define L1_CACHE_SHIFT_MAX 5	/* largest L1 which this arch supports */
+
 #endif /* _ASM_CACHE_H */
diff --git a/include/asm-i386/cache.h b/include/asm-i386/cache.h
index 615911e5bd24..849788710feb 100644
--- a/include/asm-i386/cache.h
+++ b/include/asm-i386/cache.h
@@ -10,4 +10,6 @@
 #define L1_CACHE_SHIFT	(CONFIG_X86_L1_CACHE_SHIFT)
 #define L1_CACHE_BYTES	(1 << L1_CACHE_SHIFT)
 
+#define L1_CACHE_SHIFT_MAX 7	/* largest L1 which this arch supports */
+
 #endif
diff --git a/include/asm-ia64/cache.h b/include/asm-ia64/cache.h
index 40dd25195d65..666d8f175cb3 100644
--- a/include/asm-ia64/cache.h
+++ b/include/asm-ia64/cache.h
@@ -12,6 +12,8 @@
 #define L1_CACHE_SHIFT		CONFIG_IA64_L1_CACHE_SHIFT
 #define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
 
+#define L1_CACHE_SHIFT_MAX 7	/* largest L1 which this arch supports */
+
 #ifdef CONFIG_SMP
 # define SMP_CACHE_SHIFT	L1_CACHE_SHIFT
 # define SMP_CACHE_BYTES	L1_CACHE_BYTES
diff --git a/include/asm-m68k/cache.h b/include/asm-m68k/cache.h
index fed3fd30de7e..6161fd3d8600 100644
--- a/include/asm-m68k/cache.h
+++ b/include/asm-m68k/cache.h
@@ -8,4 +8,6 @@
 #define        L1_CACHE_SHIFT  4
 #define        L1_CACHE_BYTES  (1<< L1_CACHE_SHIFT)
 
+#define L1_CACHE_SHIFT_MAX 4	/* largest L1 which this arch supports */
+
 #endif
diff --git a/include/asm-mips/cache.h b/include/asm-mips/cache.h
index 28f08756ed0e..05fc11d65ca9 100644
--- a/include/asm-mips/cache.h
+++ b/include/asm-mips/cache.h
@@ -35,5 +35,6 @@ struct cache_desc {
 #endif
 
 #define SMP_CACHE_BYTES		L1_CACHE_BYTES
+#define L1_CACHE_SHIFT_MAX 5	/* largest L1 which this arch supports */
 
 #endif /* _ASM_CACHE_H */
diff --git a/include/asm-mips64/cache.h b/include/asm-mips64/cache.h
index 6cf56e2ea8ed..8ad6af396241 100644
--- a/include/asm-mips64/cache.h
+++ b/include/asm-mips64/cache.h
@@ -11,5 +11,6 @@
 
 /* bytes per L1 cache line */
 #define L1_CACHE_BYTES		(1 << CONFIG_L1_CACHE_SHIFT)
+#define L1_CACHE_SHIFT_MAX 7	/* largest L1 which this arch supports */
 
 #endif /* _ASM_CACHE_H */
diff --git a/include/asm-parisc/cache.h b/include/asm-parisc/cache.h
index 2460121b66a3..c8de938ee602 100644
--- a/include/asm-parisc/cache.h
+++ b/include/asm-parisc/cache.h
@@ -34,6 +34,7 @@
 #define L1_CACHE_ALIGN(x)       (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
 
 #define SMP_CACHE_BYTES L1_CACHE_BYTES
+#define L1_CACHE_SHIFT_MAX 5	/* largest L1 which this arch supports */
 
 #define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES)))
 
diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h
index ff25338b1077..b2289fe3c207 100644
--- a/include/asm-ppc/cache.h
+++ b/include/asm-ppc/cache.h
@@ -29,6 +29,7 @@
 #define	L1_CACHE_BYTES L1_CACHE_LINE_SIZE
 #define L1_CACHE_SHIFT LG_L1_CACHE_LINE_SIZE
 #define	SMP_CACHE_BYTES L1_CACHE_BYTES
+#define L1_CACHE_SHIFT_MAX 7	/* largest L1 which this arch supports */
 
 #define	L1_CACHE_ALIGN(x)       (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
 #define	L1_CACHE_PAGES		8
diff --git a/include/asm-ppc64/cache.h b/include/asm-ppc64/cache.h
index cebb1eb14668..e7c07b44e140 100644
--- a/include/asm-ppc64/cache.h
+++ b/include/asm-ppc64/cache.h
@@ -12,5 +12,6 @@
 #define L1_CACHE_BYTES	(1 << L1_CACHE_SHIFT)
 
 #define SMP_CACHE_BYTES L1_CACHE_BYTES
+#define L1_CACHE_SHIFT_MAX 7	/* largest L1 which this arch supports */
 
 #endif
diff --git a/include/asm-s390/cache.h b/include/asm-s390/cache.h
index ae5338ec5064..dbe2584a3358 100644
--- a/include/asm-s390/cache.h
+++ b/include/asm-s390/cache.h
@@ -13,5 +13,6 @@
 
 #define L1_CACHE_BYTES     256
 #define L1_CACHE_SHIFT     8
+#define L1_CACHE_SHIFT_MAX 8	/* largest L1 which this arch supports */
 
 #endif
diff --git a/include/asm-s390x/cache.h b/include/asm-s390x/cache.h
index ae5338ec5064..dbe2584a3358 100644
--- a/include/asm-s390x/cache.h
+++ b/include/asm-s390x/cache.h
@@ -13,5 +13,6 @@
 
 #define L1_CACHE_BYTES     256
 #define L1_CACHE_SHIFT     8
+#define L1_CACHE_SHIFT_MAX 8	/* largest L1 which this arch supports */
 
 #endif
diff --git a/include/asm-sh/cache.h b/include/asm-sh/cache.h
index 46e915386d64..1c9b364a6c10 100644
--- a/include/asm-sh/cache.h
+++ b/include/asm-sh/cache.h
@@ -14,4 +14,6 @@
 #define        L1_CACHE_BYTES  32
 #endif
 
+#define L1_CACHE_SHIFT_MAX 5	/* largest L1 which this arch supports */
+
 #endif /* __ASM_SH_CACHE_H */
diff --git a/include/asm-sparc/cache.h b/include/asm-sparc/cache.h
index 0c282c249e46..86fd491b42a6 100644
--- a/include/asm-sparc/cache.h
+++ b/include/asm-sparc/cache.h
@@ -13,6 +13,7 @@
 #define L1_CACHE_SHIFT 5
 #define L1_CACHE_BYTES 32
 #define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)))
+#define L1_CACHE_SHIFT_MAX 5	/* largest L1 which this arch supports */
 
 #define SMP_CACHE_BYTES 32
 
diff --git a/include/asm-sparc64/cache.h b/include/asm-sparc64/cache.h
index 40c1d13aa382..c4ba581b7af1 100644
--- a/include/asm-sparc64/cache.h
+++ b/include/asm-sparc64/cache.h
@@ -9,6 +9,7 @@
 #define        L1_CACHE_BYTES	32 /* Two 16-byte sub-blocks per line. */
 
 #define        L1_CACHE_ALIGN(x)       (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
+#define		L1_CACHE_SHIFT_MAX 5	/* largest L1 which this arch supports */
 
 #define        SMP_CACHE_BYTES_SHIFT	6
 #define        SMP_CACHE_BYTES		(1 << SMP_CACHE_BYTES_SHIFT) /* L2 cache line size. */
diff --git a/include/asm-x86_64/cache.h b/include/asm-x86_64/cache.h
index b4a2401de77b..eda62bae1240 100644
--- a/include/asm-x86_64/cache.h
+++ b/include/asm-x86_64/cache.h
@@ -9,5 +9,6 @@
 /* L1 cache line size */
 #define L1_CACHE_SHIFT	(CONFIG_X86_L1_CACHE_SHIFT)
 #define L1_CACHE_BYTES	(1 << L1_CACHE_SHIFT)
+#define L1_CACHE_SHIFT_MAX 6	/* largest L1 which this arch supports */
 
 #endif
diff --git a/include/linux/cache.h b/include/linux/cache.h
index 37d7a6fe4b6e..95faa6ec3aa7 100644
--- a/include/linux/cache.h
+++ b/include/linux/cache.h
@@ -44,4 +44,13 @@
 #endif /* CONFIG_SMP */
 #endif
 
+#if !defined(____cacheline_maxaligned_in_smp)
+#if defined(CONFIG_SMP)
+#define ____cacheline_maxaligned_in_smp \
+	__attribute__((__aligned__(1 << (L1_CACHE_SHIFT_MAX))))
+#else
+#define ____cacheline_maxaligned_in_smp
+#endif
+#endif
+
 #endif /* __LINUX_CACHE_H */