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authorBiju Das <biju.das.jz@bp.renesas.com>2026-02-03 10:45:38 +0000
committerJakub Kicinski <kuba@kernel.org>2026-02-04 18:38:43 -0800
commitd2adcbdae5f6d4da445f32ea61f21fdd146670d9 (patch)
treeb0617d528681f9f199977016731815bc3c4487da /Documentation
parentd713ed0f102b69d052366fe2017f11b955bc63ea (diff)
dt-bindings: net: renesas,rzv2h-gbeth: Document Renesas RZ/G3L RMII{tx,rx} clocks
As per the RZ/G3L Hardware manual, CPG_CLKON_ETH register bits{12,13} are to control the RMII{tx, rx} clocks. Document the rmii{tx.rx} clocks for RZ/G3L SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260203104541.264759-1-biju.das.jz@bp.renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml8
1 files changed, 6 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml
index fb60f745a1ff..2125b5ddf73d 100644
--- a/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml
+++ b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml
@@ -58,6 +58,8 @@ properties:
- description: TX clock phase-shifted by 180 degrees
- description: RX clock phase-shifted by 180 degrees
- description: RMII clock
+ - description: RMII TX clock
+ - description: RMII RX clock
minItems: 7
@@ -77,6 +79,8 @@ properties:
- const: tx-180
- const: rx-180
- const: rmii
+ - const: rmii_tx
+ - const: rmii_rx
minItems: 7
@@ -170,10 +174,10 @@ allOf:
then:
properties:
clocks:
- minItems: 8
+ minItems: 10
clock-names:
- minItems: 8
+ minItems: 10
interrupts:
minItems: 15