diff options
| author | Sascha Hauer <sascha@de.rmk.(none)> | 2004-08-14 18:52:19 +0100 |
|---|---|---|
| committer | Russell King <rmk@flint.arm.linux.org.uk> | 2004-08-14 18:52:19 +0100 |
| commit | 9c496bde802b19db40325bbde356be62e66dc125 (patch) | |
| tree | 10786cd45f036d580309e7f8e22f838ad55059fe /arch/arm/kernel | |
| parent | f9df54d94e6ecb83d812b2e9fba6c6e8fc0d927c (diff) | |
[ARM PATCH] 1955/3: Motorola i.MX architecture support
Patch from Sascha Hauer
This patch adds support for the Motorola i.MX SoC. It has board
support included for the MX1ADS Eval Board, but the patch has been
tested on two other custom boards as well.
Things changed since Patch 1955/2:
- fixed according to Russell's comments.
- removed unnecassary files from include/asm-arm/arch-imx.
- removed cpufreq support (it needs rework).
- made myself the Maintainer of mx1ads
Sascha Hauer
Diffstat (limited to 'arch/arm/kernel')
| -rw-r--r-- | arch/arm/kernel/debug.S | 24 | ||||
| -rw-r--r-- | arch/arm/kernel/entry-armv.S | 25 |
2 files changed, 49 insertions, 0 deletions
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S index 822dbde5af8c..1b3d22136fb4 100644 --- a/arch/arm/kernel/debug.S +++ b/arch/arm/kernel/debug.S @@ -615,6 +615,30 @@ tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy bne 1001b .endm + +#elif defined(CONFIG_ARCH_IMX) + + .macro addruart,rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + moveq \rx, #0x00000000 @ physical + movne \rx, #0xe0000000 @ virtual + orr \rx, \rx, #0x00200000 + orr \rx, \rx, #0x00006000 @ UART1 offset + .endm + + .macro senduart,rd,rx + str \rd, [\rx, #0x40] @ TXDATA + .endm + + .macro waituart,rd,rx + .endm + + .macro busyuart,rd,rx +1002: ldr \rd, [\rx, #0x98] @ SR2 + tst \rd, #1 << 3 @ TXDC + beq 1002b @ wait until transmit done + .endm #else #error Unknown architecture #endif diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index fe2a550e800f..755e4464effd 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -884,6 +884,31 @@ ENTRY(soft_irq_mask) .macro irq_prio_table .endm +#elif defined(CONFIG_ARCH_IMX) + + .macro disable_fiq + .endm +#define AITC_NIVECSR 0x40 + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \irqstat, =IO_ADDRESS(IMX_AITC_BASE) + @ Load offset & priority of the highest priority + @ interrupt pending. + ldr \irqnr, [\irqstat, #AITC_NIVECSR] + @ Shift off the priority leaving the offset or + @ "interrupt number" + mov \irqnr, \irqnr, lsr #16 + ldr \irqstat, =1 @ dummy compare + ldr \base, =0xFFFF // invalid interrupt + cmp \irqnr, \base + bne 1001f + ldr \irqstat, =0 +1001: + tst \irqstat, #1 @ to make the condition code = TRUE + .endm + + .macro irq_prio_table + .endm + #else #error Unknown architecture #endif |