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authorKumar Gala <galak@freescale.com>2005-03-13 00:24:06 -0800
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-03-13 00:24:06 -0800
commit82c7633ae8d2d99cf5ba235ddc01e89e9e09678f (patch)
tree03590ddfa0e3f5e613edf0f2b8bd40f38f45fc08 /arch/ppc/kernel/misc.S
parent70fc7b77c21bb703af6d7cc8329fa0a1669bdbcd (diff)
[PATCH] ppc32: Remove SPR short-hand defines
Removed the Special purpose register (SPR) short-hand defines to help with name space pollution. All SPRs are now referenced as SPRN_<foo>. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/ppc/kernel/misc.S')
-rw-r--r--arch/ppc/kernel/misc.S16
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S
index 3105f54c4ed2..73f7c23b0dd4 100644
--- a/arch/ppc/kernel/misc.S
+++ b/arch/ppc/kernel/misc.S
@@ -216,10 +216,10 @@ _GLOBAL(low_choose_750fx_pll)
/* If switching to PLL1, disable HID0:BTIC */
cmplwi cr0,r3,0
beq 1f
- mfspr r5,HID0
+ mfspr r5,SPRN_HID0
rlwinm r5,r5,0,27,25
sync
- mtspr HID0,r5
+ mtspr SPRN_HID0,r5
isync
sync
@@ -241,10 +241,10 @@ _GLOBAL(low_choose_750fx_pll)
/* If switching to PLL0, enable HID0:BTIC */
cmplwi cr0,r3,0
bne 1f
- mfspr r5,HID0
+ mfspr r5,SPRN_HID0
ori r5,r5,HID0_BTIC
sync
- mtspr HID0,r5
+ mtspr SPRN_HID0,r5
isync
sync
@@ -579,7 +579,7 @@ _GLOBAL(flush_instruction_cache)
#if defined(CONFIG_8xx)
isync
lis r5, IDC_INVALL@h
- mtspr IC_CST, r5
+ mtspr SPRN_IC_CST, r5
#elif defined(CONFIG_4xx)
#ifdef CONFIG_403GCX
li r3, 512
@@ -597,14 +597,14 @@ _GLOBAL(flush_instruction_cache)
ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
mtspr SPRN_L1CSR1,r3
#else
- mfspr r3,PVR
+ mfspr r3,SPRN_PVR
rlwinm r3,r3,16,16,31
cmpwi 0,r3,1
beqlr /* for 601, do nothing */
/* 603/604 processor - use invalidate-all bit in HID0 */
- mfspr r3,HID0
+ mfspr r3,SPRN_HID0
ori r3,r3,HID0_ICFI
- mtspr HID0,r3
+ mtspr SPRN_HID0,r3
#endif /* CONFIG_8xx/4xx */
isync
blr