diff options
| author | Linus Torvalds <torvalds@athlon.transmeta.com> | 2002-02-04 18:11:38 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@athlon.transmeta.com> | 2002-02-04 18:11:38 -0800 |
| commit | 1a0153507ffae9cf3350e76c12d441788c0191e1 (patch) | |
| tree | d05a502b4fc05202c84c1667019460c08ea088cd /arch/sparc64/kernel/pci_impl.h | |
| parent | b0683ac8928c4cf40646a6ce3eb6ffe94605acfa (diff) | |
v2.4.3.2 -> v2.4.3.3
- Hui-Fen Hsu: sis900 driver update
- NIIBE Yutaka: Super-H update
- Alan Cox: more resyncs (ARM down, but more to go)
- David Miller: network zerocopy, Sparc sync, qlogic,FC fix, etc.
- David Miller/me: get rid of various drivers hacks to do mmap
alignment behind the back of the VM layer. Create a real
protocol for it.
Diffstat (limited to 'arch/sparc64/kernel/pci_impl.h')
| -rw-r--r-- | arch/sparc64/kernel/pci_impl.h | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/arch/sparc64/kernel/pci_impl.h b/arch/sparc64/kernel/pci_impl.h index 54a8952b8f4b..415af23fd89f 100644 --- a/arch/sparc64/kernel/pci_impl.h +++ b/arch/sparc64/kernel/pci_impl.h @@ -1,4 +1,4 @@ -/* $Id: pci_impl.h,v 1.6 2000/03/25 05:18:11 davem Exp $ +/* $Id: pci_impl.h,v 1.7 2001/03/28 10:56:34 davem Exp $ * pci_impl.h: Helper definitions for PCI controller support. * * Copyright (C) 1999 David S. Miller (davem@redhat.com) @@ -41,6 +41,7 @@ extern void pci_scan_for_parity_error(struct pci_controller_info *, struct pci_p /* Configuration space access. */ extern spinlock_t pci_poke_lock; extern volatile int pci_poke_in_progress; +extern volatile int pci_poke_cpu; extern volatile int pci_poke_faulted; static __inline__ void pci_config_read8(u8 *addr, u8 *ret) @@ -49,6 +50,7 @@ static __inline__ void pci_config_read8(u8 *addr, u8 *ret) u8 byte; spin_lock_irqsave(&pci_poke_lock, flags); + pci_poke_cpu = smp_processor_id(); pci_poke_in_progress = 1; pci_poke_faulted = 0; __asm__ __volatile__("membar #Sync\n\t" @@ -58,6 +60,7 @@ static __inline__ void pci_config_read8(u8 *addr, u8 *ret) : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) : "memory"); pci_poke_in_progress = 0; + pci_poke_cpu = -1; if (!pci_poke_faulted) *ret = byte; spin_unlock_irqrestore(&pci_poke_lock, flags); @@ -69,6 +72,7 @@ static __inline__ void pci_config_read16(u16 *addr, u16 *ret) u16 word; spin_lock_irqsave(&pci_poke_lock, flags); + pci_poke_cpu = smp_processor_id(); pci_poke_in_progress = 1; pci_poke_faulted = 0; __asm__ __volatile__("membar #Sync\n\t" @@ -78,6 +82,7 @@ static __inline__ void pci_config_read16(u16 *addr, u16 *ret) : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) : "memory"); pci_poke_in_progress = 0; + pci_poke_cpu = -1; if (!pci_poke_faulted) *ret = word; spin_unlock_irqrestore(&pci_poke_lock, flags); @@ -89,6 +94,7 @@ static __inline__ void pci_config_read32(u32 *addr, u32 *ret) u32 dword; spin_lock_irqsave(&pci_poke_lock, flags); + pci_poke_cpu = smp_processor_id(); pci_poke_in_progress = 1; pci_poke_faulted = 0; __asm__ __volatile__("membar #Sync\n\t" @@ -98,6 +104,7 @@ static __inline__ void pci_config_read32(u32 *addr, u32 *ret) : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) : "memory"); pci_poke_in_progress = 0; + pci_poke_cpu = -1; if (!pci_poke_faulted) *ret = dword; spin_unlock_irqrestore(&pci_poke_lock, flags); @@ -108,6 +115,7 @@ static __inline__ void pci_config_write8(u8 *addr, u8 val) unsigned long flags; spin_lock_irqsave(&pci_poke_lock, flags); + pci_poke_cpu = smp_processor_id(); pci_poke_in_progress = 1; pci_poke_faulted = 0; __asm__ __volatile__("membar #Sync\n\t" @@ -117,6 +125,7 @@ static __inline__ void pci_config_write8(u8 *addr, u8 val) : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) : "memory"); pci_poke_in_progress = 0; + pci_poke_cpu = -1; spin_unlock_irqrestore(&pci_poke_lock, flags); } @@ -125,6 +134,7 @@ static __inline__ void pci_config_write16(u16 *addr, u16 val) unsigned long flags; spin_lock_irqsave(&pci_poke_lock, flags); + pci_poke_cpu = smp_processor_id(); pci_poke_in_progress = 1; pci_poke_faulted = 0; __asm__ __volatile__("membar #Sync\n\t" @@ -134,6 +144,7 @@ static __inline__ void pci_config_write16(u16 *addr, u16 val) : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) : "memory"); pci_poke_in_progress = 0; + pci_poke_cpu = -1; spin_unlock_irqrestore(&pci_poke_lock, flags); } @@ -142,6 +153,7 @@ static __inline__ void pci_config_write32(u32 *addr, u32 val) unsigned long flags; spin_lock_irqsave(&pci_poke_lock, flags); + pci_poke_cpu = smp_processor_id(); pci_poke_in_progress = 1; pci_poke_faulted = 0; __asm__ __volatile__("membar #Sync\n\t" @@ -151,6 +163,7 @@ static __inline__ void pci_config_write32(u32 *addr, u32 val) : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) : "memory"); pci_poke_in_progress = 0; + pci_poke_cpu = -1; spin_unlock_irqrestore(&pci_poke_lock, flags); } |
